CIRCT
Circuit IR Compilers and Tools
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Doxygen
GitHub
Code Documentation
Code Documentation Docs
CommandGuide
CIRCT Charter
Dialects
Getting Started with the CIRCT Project
Passes
PyCDE
Static scheduling infrastructure
Symbol and Inner Symbol Rationale
Using the Python Bindings
Verilog and SystemVerilog Generation
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Home
Talks and Related Publications
Getting Started
Code Documentation
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CommandGuide
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handshake-runner
CIRCT Charter
Dialects
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'calyx' Dialect
'chirrtl' Dialect
'comb' Dialect
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`comb` Dialect Rationale
'esi' Dialect
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ESI cosimulation model
ESI data types and communication types
ESI Global Services
ESI Software APIs
Miscellaneous Notes
The Elastic Silicon Interconnect dialect
'firrtl' Dialect
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FIRRTL Annotations
FIRRTL Dialect Rationale
Intrinsics
'fsm' Dialect
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FSM Dialect Rationale
'handshake' Dialect
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Handshake Dialect Rationale
'hw' Dialect
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HW Dialect Rationale
'hwarith' Dialect
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HW Arith Dialect Rationale
'llhd' Dialect
'moore' Dialect
'msft' Dialect
'pipeline' Dialect
'seq' Dialect
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Seq(uential) Dialect Rationale
'ssp' Dialect
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SSP Dialect Rationale
'sv' Dialect
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SV Dialect Rationale
'systemc' Dialect
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SystemC Dialect Rationale
Interop Dialect
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Interoperability Dialect Rationale
Getting Started with the CIRCT Project
Passes
PyCDE
Static scheduling infrastructure
Symbol and Inner Symbol Rationale
Using the Python Bindings
Verilog and SystemVerilog Generation