'arc' Dialect
Canonical representation of state transfer in a circuit
This is the arc
dialect, useful for representing state transfer functions
in a circuit.
Operation definition ¶
arc.alloc_memory
(circt::arc::AllocMemoryOp) ¶
Allocate a memory
Syntax:
operation ::= `arc.alloc_memory` $storage attr-dict `:` functional-type($storage, $memory)
Interfaces: MemoryEffectOpInterface (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{MemoryEffects::Allocate on ::mlir::SideEffects::DefaultResource}
Operands: ¶
Operand | Description |
---|---|
storage |
Results: ¶
Result | Description |
---|---|
memory |
arc.alloc_state
(circt::arc::AllocStateOp) ¶
Allocate internal state
Syntax:
operation ::= `arc.alloc_state` $storage (`tap` $tap^)? attr-dict `:` functional-type($storage, $state)
Interfaces: MemoryEffectOpInterface (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{MemoryEffects::Allocate on ::mlir::SideEffects::DefaultResource}
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
tap | ::mlir::UnitAttr | unit attribute |
Operands: ¶
Operand | Description |
---|---|
storage |
Results: ¶
Result | Description |
---|---|
state |
arc.alloc_storage
(circt::arc::AllocStorageOp) ¶
Allocate contiguous storage space from a larger storage space
Syntax:
operation ::= `arc.alloc_storage` $input (`[` $offset^ `]`)? attr-dict `:` functional-type($input, $output)
Interfaces: MemoryEffectOpInterface (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{MemoryEffects::Allocate on ::mlir::SideEffects::DefaultResource}
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
offset | ::mlir::IntegerAttr | 32-bit signless integer attribute |
Operands: ¶
Operand | Description |
---|---|
input |
Results: ¶
Result | Description |
---|---|
output |
arc.call
(circt::arc::CallOp) ¶
calls an arc
Syntax:
operation ::= `arc.call` $arc `(` $inputs `)` attr-dict `:` functional-type(operands, results)
Traits: AlwaysSpeculatableImplTrait, MemRefsNormalizable
Interfaces: CallOpInterface, CallOpMutableInterface, ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface), SymbolUserOpInterface
Effects: MemoryEffects::Effect{}
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
arc | ::mlir::FlatSymbolRefAttr | flat symbol reference attribute |
Operands: ¶
Operand | Description |
---|---|
inputs | any type |
Results: ¶
Result | Description |
---|---|
outputs | any type |
arc.clock_domain
(circt::arc::ClockDomainOp) ¶
a clock domain
Syntax:
operation ::= `arc.clock_domain` ` ` `(` $inputs `)` `clock` $clock attr-dict `:`
functional-type($inputs, results) $body
Traits: IsolatedFromAbove, RecursiveMemoryEffects, SingleBlockImplicitTerminator arc::OutputOp
Interfaces: RegionKindInterface
Operands: ¶
Operand | Description |
---|---|
inputs | any type |
clock | 1-bit signless integer |
Results: ¶
Result | Description |
---|---|
outputs | any type |
arc.clock_gate
(circt::arc::ClockGateOp) ¶
Clock gate
Syntax:
operation ::= `arc.clock_gate` $input `,` $enable attr-dict
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
input | 1-bit signless integer |
enable | 1-bit signless integer |
Results: ¶
Result | Description |
---|---|
output | 1-bit signless integer |
arc.clock_tree
(circt::arc::ClockTreeOp) ¶
A clock tree
Syntax:
operation ::= `arc.clock_tree` $clock attr-dict-with-keyword $body
Traits: NoRegionArguments, NoTerminator
Operands: ¶
Operand | Description |
---|---|
clock | 1-bit signless integer |
arc.define
(circt::arc::DefineOp) ¶
State transfer arc definition
Traits: HasParent mlir::ModuleOp, IsolatedFromAbove, SingleBlockImplicitTerminator arc::OutputOp
Interfaces: CallableOpInterface, FunctionOpInterface, RegionKindInterface, Symbol
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
sym_name | ::mlir::StringAttr | string attribute |
function_type | ::mlir::TypeAttr | type attribute of function type |
arg_attrs | ::mlir::ArrayAttr | Array of dictionary attributes |
res_attrs | ::mlir::ArrayAttr | Array of dictionary attributes |
arc.lut
(circt::arc::LutOp) ¶
A lookup-table.
Syntax:
operation ::= `arc.lut` `(` $inputs `)` `:` functional-type($inputs, $output)
attr-dict-with-keyword $body
Represents a lookup-table as one operation. The operations that map the lookup/input values to the corresponding table-entry are collected inside the body of this operation. Note that the operation is marked to be isolated from above to guarantee that all input values have to be passed as an operand. This allows for simpler analyses and canonicalizations of the LUT as well as lowering. Only combinational operations are allowed inside the LUT, i.e., no side-effects, state, time delays, etc.
Traits: AlwaysSpeculatableImplTrait, IsolatedFromAbove, SingleBlockImplicitTerminator arc::OutputOp
Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
inputs | signless integer |
Results: ¶
Result | Description |
---|---|
output | signless integer |
arc.memory
(circt::arc::MemoryOp) ¶
Memory
Syntax:
operation ::= `arc.memory` type($memory) attr-dict
Interfaces: MemoryEffectOpInterface (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{MemoryEffects::Allocate on ::mlir::SideEffects::DefaultResource}
Results: ¶
Result | Description |
---|---|
memory |
arc.memory_read
(circt::arc::MemoryReadOp) ¶
Read word from memory
Syntax:
operation ::= `arc.memory_read` $memory `[` $address `]` attr-dict `:` type($memory)
Interfaces: InferTypeOpInterface, MemoryEffectOpInterface (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{MemoryEffects::Read on ::mlir::SideEffects::DefaultResource}
Operands: ¶
Operand | Description |
---|---|
memory | |
address | integer |
Results: ¶
Result | Description |
---|---|
data | integer |
arc.memory_read_port
(circt::arc::MemoryReadPortOp) ¶
Read port from a memory
Syntax:
operation ::= `arc.memory_read_port` $memory `[` $address `]` attr-dict `:` type($memory)
Represents a combinatorial memory read port. No memory read side-effect trait is necessary because at the stage of the Arc lowering where this operation is legal to be present, it is guaranteed that all reads from the same address produce the same output. This is because all writes are reordered to happen at the end of the cycle in LegalizeStateUpdates (or alternatively produce the necessary temporaries).
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
memory | |
address | integer |
Results: ¶
Result | Description |
---|---|
data | integer |
arc.memory_write
(circt::arc::MemoryWriteOp) ¶
Write word to memory
Syntax:
operation ::= `arc.memory_write` $memory `[` $address `]` `,` $data (`if` $enable^)?
attr-dict `:` type($memory)
Interfaces: MemoryEffectOpInterface (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{MemoryEffects::Write on ::mlir::SideEffects::DefaultResource}
Operands: ¶
Operand | Description |
---|---|
memory | |
address | integer |
enable | 1-bit signless integer |
data | integer |
arc.memory_write_port
(circt::arc::MemoryWritePortOp) ¶
Write port to a memory
Syntax:
operation ::= `arc.memory_write_port` $memory `,` $arc `(` $inputs `)` (`clock` $clock^)? (`enable` $enable^)?
(`mask` $mask^)? `lat` $latency attr-dict `:`
type($memory) `,` type($inputs)
Traits: AttrSizedOperandSegments
Interfaces: CallOpInterface, CallOpMutableInterface, ClockedOpInterface, MemoryEffectOpInterface (MemoryEffectOpInterface), SymbolUserOpInterface
Effects: MemoryEffects::Effect{MemoryEffects::Write on ::mlir::SideEffects::DefaultResource}
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
arc | ::mlir::FlatSymbolRefAttr | flat symbol reference attribute |
enable | ::mlir::UnitAttr | unit attribute |
mask | ::mlir::UnitAttr | unit attribute |
latency | ::mlir::IntegerAttr | 32-bit signless integer attribute |
Operands: ¶
Operand | Description |
---|---|
memory | |
inputs | any type |
clock | 1-bit signless integer |
arc.model
(circt::arc::ModelOp) ¶
A model with stratified clocks
Syntax:
operation ::= `arc.model` $name attr-dict-with-keyword $body
Traits: IsolatedFromAbove, NoTerminator
Interfaces: RegionKindInterface
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
name | ::mlir::StringAttr | string attribute |
arc.output
(circt::arc::OutputOp) ¶
Arc terminator
Syntax:
operation ::= `arc.output` attr-dict ($outputs^ `:` qualified(type($outputs)))?
Traits: AlwaysSpeculatableImplTrait, HasParent<DefineOp, LutOp, ClockDomainOp>, ReturnLike, Terminator
Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
outputs | any type |
arc.passthrough
(circt::arc::PassThroughOp) ¶
Clock-less logic that is on the pass-through path
Syntax:
operation ::= `arc.passthrough` attr-dict-with-keyword $body
Traits: NoRegionArguments, NoTerminator
arc.root_input
(circt::arc::RootInputOp) ¶
A root input
Syntax:
operation ::= `arc.root_input` $name `,` $storage attr-dict `:` functional-type($storage, $state)
Interfaces: OpAsmOpInterface
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
name | ::mlir::StringAttr | string attribute |
Operands: ¶
Operand | Description |
---|---|
storage |
Results: ¶
Result | Description |
---|---|
state |
arc.root_output
(circt::arc::RootOutputOp) ¶
A root output
Syntax:
operation ::= `arc.root_output` $name `,` $storage attr-dict `:` functional-type($storage, $state)
Interfaces: OpAsmOpInterface
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
name | ::mlir::StringAttr | string attribute |
Operands: ¶
Operand | Description |
---|---|
storage |
Results: ¶
Result | Description |
---|---|
state |
arc.state
(circt::arc::StateOp) ¶
State transfer arc
Syntax:
operation ::= `arc.state` $arc `(` $inputs `)` (`clock` $clock^)? (`enable` $enable^)?
(`reset` $reset^)? `lat` $latency attr-dict
`:` functional-type($inputs, results)
Traits: AttrSizedOperandSegments, MemRefsNormalizable
Interfaces: CallOpInterface, CallOpMutableInterface, ClockedOpInterface, SymbolUserOpInterface
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
arc | ::mlir::FlatSymbolRefAttr | flat symbol reference attribute |
latency | ::mlir::IntegerAttr | 32-bit signless integer attribute |
Operands: ¶
Operand | Description |
---|---|
clock | 1-bit signless integer |
enable | 1-bit signless integer |
reset | 1-bit signless integer |
inputs | any type |
Results: ¶
Result | Description |
---|---|
outputs | any type |
arc.state_read
(circt::arc::StateReadOp) ¶
Get a state’s current value
Syntax:
operation ::= `arc.state_read` $state attr-dict `:` type($state)
Interfaces: InferTypeOpInterface, MemoryEffectOpInterface (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{MemoryEffects::Read on ::mlir::SideEffects::DefaultResource}
Operands: ¶
Operand | Description |
---|---|
state |
Results: ¶
Result | Description |
---|---|
value | integer |
arc.state_write
(circt::arc::StateWriteOp) ¶
Update a state’s value
Syntax:
operation ::= `arc.state_write` $state `=` $value (`if` $condition^)? attr-dict `:` type($state)
Changes the value of a state. This operation is treated as a deferred
assignment by most transformation passes, which allows them to change the
order of arc.state_read
and arc.state_write
ops on the same state
without affecting the correctness of the model. The reads are always assumed
to produce the current value of the state and writes to be deferred until
all operations in the model have been executed for the current time step.
The only exceptions to this are the state update legalization pass, which
inserts the necessary temporary variables such that writes can be performed
immediately without affecting correctness. This allows later lowering passes
to treat arc.state_write
as an immediate assignment (without defering).
Interfaces: MemoryEffectOpInterface (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{MemoryEffects::Write on ::mlir::SideEffects::DefaultResource}
Operands: ¶
Operand | Description |
---|---|
state | |
value | integer |
condition | 1-bit signless integer |
arc.storage.get
(circt::arc::StorageGetOp) ¶
Access an allocated state, memory, or storage slice
Syntax:
operation ::= `arc.storage.get` $storage `[` $offset `]` attr-dict
`:` qualified(type($storage)) `->` type($result)
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
offset | ::mlir::IntegerAttr | 32-bit signless integer attribute |
Operands: ¶
Operand | Description |
---|---|
storage |
Results: ¶
Result | Description |
---|---|
result | or or |
arc.tap
(circt::arc::TapOp) ¶
A tracker op to observe a value under a given name
Syntax:
operation ::= `arc.tap` $value attr-dict `:` type($value)
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
name | ::mlir::StringAttr | string attribute |
Operands: ¶
Operand | Description |
---|---|
value | signless integer |
arc.zero_count
(circt::arc::ZeroCountOp) ¶
leading/trailing zero count operation
Syntax:
operation ::= `arc.zero_count` $predicate $input attr-dict `:` type($input)
Traits: AlwaysSpeculatableImplTrait, SameOperandsAndResultType
Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
predicate | circt::arc::ZeroCountPredicateAttr | arc.zero_count predicate |
Operands: ¶
Operand | Description |
---|---|
input | signless integer |
Results: ¶
Result | Description |
---|---|
output | signless integer |
Type definition ¶
MemoryType ¶
Syntax:
!arc.memory<
unsigned, # numWords
::mlir::IntegerType, # wordType
::mlir::IntegerType # addressType
>
Parameters: ¶
Parameter | C++ type | Description |
---|---|---|
numWords | unsigned | |
wordType | ::mlir::IntegerType | |
addressType | ::mlir::IntegerType |
StateType ¶
Syntax:
!arc.state<
::mlir::IntegerType # type
>
Parameters: ¶
Parameter | C++ type | Description |
---|---|---|
type | ::mlir::IntegerType |
StorageType ¶
Syntax:
!arc.storage<
unsigned # size
>
Parameters: ¶
Parameter | C++ type | Description |
---|---|---|
size | unsigned |