CIRCT

Circuit IR Compilers and Tools

'chirrtl' Dialect

Types and operations for the chirrtl dialect This dialect defines the chirrtl dialect, which contains high-level memory defintions which can be lowered to FIRRTL.

Type constraint definition 

a behavioral memory port 

Syntax:

cmemoryport-type ::= `cmemoryport`

The value of a cmemoryport type represents a port which has been declared on a cmemory. This value is used to set the memory port access conditions.

a behavioral memory 

Syntax:

cmemory-type ::= `cmemory` `<` element-type, element-count `>`

The value of a cmemory type represents a behavioral memory with unknown ports. This is produced by combmem and seqmem declarations and used by memoryport declarations to define memories and their ports. A CMemory is similar to a vector of passive element types.

Examples:

!chirrtl.cmemory<uint<32>, 16>
!chirrtl.cmemory<bundle<a : uint<1>>, 16>

Operation definition 

chirrtl.combmem (::circt::chirrtl::CombMemOp) 

Define a new combinational memory

Syntax:

operation ::= `chirrtl.combmem` (`sym` $inner_sym^)? custom<CombMemOp>(attr-dict) `:` type($result)

Define a new behavioral combinational memory. Combinational memories have a write latency of 1 and a read latency of 0.

Attributes: 

AttributeMLIR TypeDescription
name::mlir::StringAttrstring attribute
annotations::mlir::ArrayAttr
inner_sym::mlir::StringAttrstring attribute

Results: 

ResultDescription
resulta behavioral memory

chirrtl.memoryport.access (::circt::chirrtl::MemoryPortAccessOp) 

Enables a memory port

Syntax:

operation ::= `chirrtl.memoryport.access` $port `[` $index `]` `,` $clock attr-dict `:` type(operands)

This operation is used to conditionally enable a memory port, and associate it with a clock and index. The memory port will be actuve on the positive edge of the clock. The index is the address of the memory accessed. See the FIRRTL rational for more information about why this operation exists.

Operands: 

OperandDescription
porta behavioral memory port
indexsint or uint type
clockclock

chirrtl.memoryport (::circt::chirrtl::MemoryPortOp) 

Defines a memory port on CHIRRTL memory

Syntax:

operation ::= `chirrtl.memoryport` $direction $memory custom<MemoryPortOp>(attr-dict) `:`
              functional-type(operands, results)

This operation defines a new memory port on a seqmem or combmemCHISEL. data is the data returned from the memory port.

The memory port requires an access point, which sets the enable condition of the port, the clock, and the address. This is done by passing the the port argument to a chirrtl.memoryport.access operation.

Interfaces: InferTypeOpInterface, OpAsmOpInterface

Attributes: 

AttributeMLIR TypeDescription
direction::MemDirAttrAttrMemory Direction Enum
name::mlir::StringAttrstring attribute
annotations::mlir::ArrayAttr

Operands: 

OperandDescription
memorya behavioral memory

Results: 

ResultDescription
dataFIRRTLType
porta behavioral memory port

chirrtl.seqmem (::circt::chirrtl::SeqMemOp) 

Define a new sequential memory

Syntax:

operation ::= `chirrtl.seqmem` (`sym` $inner_sym^)? $ruw custom<SeqMemOp>(attr-dict) `:` type($result)

Define a new behavioral sequential memory. Sequential memories have a write latency and a read latency of 1.

Attributes: 

AttributeMLIR TypeDescription
ruw::RUWAttrAttrRead Under Write Enum
name::mlir::StringAttrstring attribute
annotations::mlir::ArrayAttr
inner_sym::mlir::StringAttrstring attribute

Results: 

ResultDescription
resulta behavioral memory

Type definition 

CMemoryPortType 

a behavioral memory port

Syntax:

cmemoryport-type ::= `cmemoryport`

The value of a cmemoryport type represents a port which has been declared on a cmemory. This value is used to set the memory port access conditions.

CMemoryType 

a behavioral memory

Syntax:

cmemory-type ::= `cmemory` `<` element-type, element-count `>`

The value of a cmemory type represents a behavioral memory with unknown ports. This is produced by combmem and seqmem declarations and used by memoryport declarations to define memories and their ports. A CMemory is similar to a vector of passive element types.

Examples:

!chirrtl.cmemory<uint<32>, 16>
!chirrtl.cmemory<bundle<a : uint<1>>, 16>

Parameters: 

ParameterC++ typeDescription
elementTypefirrtl::FIRRTLType
numElementsunsigned

‘firrtl’ Dialect

Types and operations for firrtl dialect This dialect defines the firrtl dialect, which is used to lower from Chisel code to Verilog. For more information, see the FIRRTL GitHub page.

Attribute definition 

AugmentedBooleanTypeAttr 

Parameters: 

ParameterC++ typeDescription
underlyingDictionaryAttr

AugmentedBundleTypeAttr 

Parameters: 

ParameterC++ typeDescription
underlyingDictionaryAttr

AugmentedDeletedTypeAttr 

Parameters: 

ParameterC++ typeDescription
underlyingDictionaryAttr

AugmentedDoubleTypeAttr 

Parameters: 

ParameterC++ typeDescription
underlyingDictionaryAttr

AugmentedGroundTypeAttr 

Parameters: 

ParameterC++ typeDescription
underlyingDictionaryAttr

AugmentedIntegerTypeAttr 

Parameters: 

ParameterC++ typeDescription
underlyingDictionaryAttr

AugmentedLiteralTypeAttr 

Parameters: 

ParameterC++ typeDescription
underlyingDictionaryAttr

AugmentedStringTypeAttr 

Parameters: 

ParameterC++ typeDescription
underlyingDictionaryAttr

AugmentedVectorTypeAttr 

Parameters: 

ParameterC++ typeDescription
underlyingDictionaryAttr

InvalidValueAttr 

A constant value of firrtl.invalid type

Represents an firrtl.invalidvalue value, whose type is specified by the type of the attribute.

Parameters: 

ParameterC++ typeDescription
type::mlir::Type

ParamDeclAttr 

module or instance parameter definition

Parameters: 

ParameterC++ typeDescription
name::mlir::StringAttr
type::mlir::TypeAttr
value::mlir::Attribute

SubAnnotationAttr 

An Annotation that targets part of what it’s attached to

An Annotation that is only applicable to part of what it is attached to. This uses a field ID to indicate to which field it is applicable.

Parameters: 

ParameterC++ typeDescription
fieldIDint64_t
annotationsDictionaryAttr

Type constraint definition 

analog type 

Reset 

AsyncReset 

BundleType 

clock 

FIRRTLType 

FVectorType 

sint or uint type 

UInt<1>, SInt<1>, or Analog<1> 

a passive type (contain no flips) 

Reset 

sint type 

UInt<1> or UInt 

uint type