CIRCT

Circuit IR Compilers and Tools

'calyx' Dialect

Types and operations for the Calyx dialect Calyx is an intermediate language and infrastructure for building compilers that generate custom hardware accelerators. For more information, visit the documentation .

Operation definition 

calyx.assign (::circt::calyx::AssignOp) 

Calyx Assignment

Syntax:

operation ::= `calyx.assign` $dest `=` $src (`,` $guard^ `?`)? attr-dict `:` type($dest)

The “calyx.assign” operation represents a non-blocking assignment. An assignment may optionally be guarded, which controls when the assignment should be active. This operation should only be instantiated in the “calyx.wires” section or a “calyx.group”.

  calyx.assign %1 = %2 : i16
  calyx.assign %1 = %2, %guard ? : i16

Operands: 

OperandDescription
destany type
srcany type
guard1-bit signless integer

calyx.cell (::circt::calyx::CellOp) 

Calyx Cell

Syntax:

operation ::= `calyx.cell` $instanceName $componentName attr-dict (`:` type($results)^)?

Represents a cell (or instance) of a Calyx component or primitive, which may include state. Some cells may optionally have parameters attributed to them.

  %name.in, %name.out = calyx.cell "name" @MyComponent : i64, i16

Attributes: 

AttributeMLIR TypeDescription
instanceName::mlir::StringAttrstring attribute
componentName::mlir::FlatSymbolRefAttrflat symbol reference attribute

Results: 

ResultDescription
resultsany type

calyx.component (::circt::calyx::ComponentOp) 

Calyx Component

The “calyx.component” operation represents an overall Calyx component containing: (1) In- and output port definitions that define the interface. (2) The cells, wires, and control schedule.

A Calyx component requires the following ports with bit width 1:

  • Input ports: go, clk, and reset.
  • Output ports: done.
  calyx.component @MyComponent(%in: i32, %go: i1, %clk: i1, %reset: i1) -> (%out: i16, %done: i1) {
    ...
    calyx.wires { ... }
    calyx.control { ... }
  }

Attributes: 

AttributeMLIR TypeDescription
inPortNames::mlir::ArrayAttrarray attribute
outPortNames::mlir::ArrayAttrarray attribute

calyx.control (::circt::calyx::ControlOp) 

Calyx Control

Syntax:

operation ::= `calyx.control` $body attr-dict

The “calyx.control” operation represents the execution schedule defined for the given component, i.e. when each group executes.

  calyx.control {
    calyx.seq {
      calyx.enable @GroupA
    }
  }

calyx.enable (::circt::calyx::EnableOp) 

Calyx Enable

Syntax:

operation ::= `calyx.enable` $groupName attr-dict

The “calyx.enable” operation represents the execution of a group defined explicitly in the “calyx.wires” section.

The ‘compiledGroups’ attribute is used in the Compile Control pass to track which groups are compiled within the new compilation group.

  calyx.enable @SomeGroup

Attributes: 

AttributeMLIR TypeDescription
groupName::mlir::FlatSymbolRefAttrflat symbol reference attribute
compiledGroups::mlir::ArrayAttrarray attribute

calyx.group_done (::circt::calyx::GroupDoneOp) 

Calyx Group Done Port

Syntax:

operation ::= `calyx.group_done` $src (`,` $guard^ `?`)? attr-dict `:` type($src)

The “calyx.group_done” operation represents a port on a Calyx group that signifies when the group is finished. A done operation may optionally be guarded, which controls when the group’s done operation should be active.

  calyx.group_done %v1 : i1
  calyx.group_done %v2, %guard ? : i1

Operands: 

OperandDescription
src1-bit signless integer
guard1-bit signless integer

calyx.group_go (::circt::calyx::GroupGoOp) 

Calyx Group Go Port

Syntax:

operation ::= `calyx.group_go` $src (`,` $guard^ `?`)? attr-dict `:` type($src)

The “calyx.group_go” operation represents a port on a Calyx group that signifies when the group begins. A go operation may optionally be guarded, which controls when the group’s go operation should be active. The go operation should only be inserted during the Go Insertion pass. It does not receive a source until the Compile Control pass.

  %group_name1.go = calyx.group_go %0 : i1
  %group_name2.go = calyx.group_go %3, %guard ? : i1

Operands: 

OperandDescription
src1-bit signless integer
guard1-bit signless integer

Results: 

ResultDescription
«unnamed»1-bit signless integer

calyx.group (::circt::calyx::GroupOp) 

Calyx Group

Syntax:

operation ::= `calyx.group` $sym_name $body attr-dict

Represents a Calyx group, which is a collection of assignments that are only active when the group is run from the control execution schedule. A group signifies its termination with a special port named a “done” port.

  calyx.group @MyGroup {
    calyx.assign %1 = %2 : i32
    calyx.group_done %3 : i1
  }

Attributes: 

AttributeMLIR TypeDescription
sym_name::mlir::StringAttrstring attribute

calyx.program (::circt::calyx::ProgramOp) 

Calyx Program

Syntax:

operation ::= `calyx.program` $body attr-dict

The “calyx.program” operation represents an overall Calyx program, containing a list of Calyx components. This must include a “main” component, the entry point of the program.

calyx.register (::circt::calyx::RegisterOp) 

Defines a register

Syntax:

operation ::= `calyx.register` $name attr-dict `:` type($in)

The “calyx.register” op defines a register.

  %r.in, %r.write_en, %r.clk, %r.reset, %r.out, %r.done = calyx.register "r" : i32

Attributes: 

AttributeMLIR TypeDescription
name::mlir::StringAttrstring attribute

Results: 

ResultDescription
inany type
write_en1-bit signless integer
clk1-bit signless integer
reset1-bit signless integer
outany type
done1-bit signless integer

calyx.seq (::circt::calyx::SeqOp) 

Calyx Sequential

Syntax:

operation ::= `calyx.seq` $body attr-dict

The “calyx.seq” operation executes the control within its region sequentially.

  calyx.seq {
    // G2 will not begin execution until G1 is done.
    calyx.enable @G1
    calyx.enable @G2
  }

calyx.undef (::circt::calyx::UndefinedOp) 

Calyx Undefined Value

Syntax:

operation ::= `calyx.undef` attr-dict `:` type($res)

The “undef” operation represents an undefined value that may be used when a specific source or destination does not have an assignment yet. This is used to avoid pulling in the entire LLVMIR dialect for a single operation.

  %0 = calyx.undef : i1

Results: 

ResultDescription
resany type

calyx.wires (::circt::calyx::WiresOp) 

Calyx Wires

Syntax:

operation ::= `calyx.wires` $body attr-dict

The “calyx.wires” operation represents a set of guarded connections between component instances, which may be placed within groups.

  calyx.wires {
    calyx.group @A { ... }
    calyx.assign %1 = %2 : i16
  }