CIRCT

Circuit IR Compilers and Tools

'firrtl' Dialect

This dialect defines the firrtl dialect, which is used to lower from Chisel code to Verilog. For more information, see the FIRRTL GitHub page.

Operation Definitions – Structure

firrtl.circuit (::circt::firrtl::CircuitOp)

FIRRTL Circuit

Syntax:

operation ::= `firrtl.circuit` $name `` custom<CircuitOpAttrs>(attr-dict) $body

The “firrtl.circuit” operation represents an overall Verilog circuit, containing a list of modules.

Traits: InnerRefNamespace, IsolatedFromAbove, NoRegionArguments, NoTerminator, SingleBlock, SymbolTable

Attributes:

AttributeMLIR TypeDescription
name::mlir::StringAttrstring attribute
annotations::mlir::ArrayAttrAnnotation array attribute

firrtl.class (::circt::firrtl::ClassOp)

FIRRTL Class

The “firrtl.class” operation defines a class of property-only objects, including a given name, a list of ports, and a body that represents the connections within the class.

A class may only have property ports, and its body may only be ops that act on properties, such as propassign ops.

Traits: HasParent<CircuitOp>, InnerSymbolTable, IsolatedFromAbove, NoTerminator, SingleBlock

Interfaces: ClassLike, FModuleLike, InstanceGraphModuleOpInterface, ModuleOpInterface, OpAsmOpInterface, PortList, SymbolOpInterface, SymbolUserOpInterface, Symbol

Attributes:

AttributeMLIR TypeDescription
sym_name::mlir::StringAttrstring attribute
portDirections::mlir::DenseBoolArrayAttri1 dense array attribute
portNames::mlir::ArrayAttrarray attribute
portTypes::mlir::ArrayAttrarray attribute
portSyms::mlir::ArrayAttrarray attribute
portLocations::mlir::ArrayAttrarray attribute

firrtl.extclass (::circt::firrtl::ExtClassOp)

FIRRTL external class

The “firrtl.extclass” operation represents a reference to an external firrtl class, and includes a given name, as well as a list of ports. Just as usual firrtl.class definitions, An ext.class may only have property ports.

example:

firrtl.extclass @MyImportedClass(in in_str: !firrtl.string, out out_str: !firrtl.string)

Traits: HasParent<CircuitOp>, InnerSymbolTable, IsolatedFromAbove

Interfaces: ClassLike, FModuleLike, InstanceGraphModuleOpInterface, ModuleOpInterface, OpAsmOpInterface, PortList, SymbolOpInterface, SymbolUserOpInterface, Symbol

Attributes:

AttributeMLIR TypeDescription
sym_name::mlir::StringAttrstring attribute
portDirections::mlir::DenseBoolArrayAttri1 dense array attribute
portNames::mlir::ArrayAttrarray attribute
portTypes::mlir::ArrayAttrarray attribute
portSyms::mlir::ArrayAttrarray attribute
portLocations::mlir::ArrayAttrarray attribute

firrtl.extmodule (::circt::firrtl::FExtModuleOp)

FIRRTL external module

The “firrtl.extmodule” operation represents an external reference to a Verilog module, including a given name and a list of ports. LowerAnnotations can add RefType ports to it. Each RefType port must have a corresponding entry in the internalPaths attribute. The internalPaths attribute is used to represent opaque internal paths into the external module, to be used for generating XMRs. Each RefType port must be removed by LowerXMR pass.

Traits: HasParent<CircuitOp>, InnerSymbolTable, IsolatedFromAbove

Interfaces: FModuleLike, InstanceGraphModuleOpInterface, ModuleOpInterface, OpAsmOpInterface, PortList, SymbolUserOpInterface, Symbol

Attributes:

AttributeMLIR TypeDescription
defname::mlir::StringAttrstring attribute
parameters::mlir::ArrayAttrparameter array attribute
convention::circt::firrtl::ConventionAttrlowering convention
portDirections::mlir::DenseBoolArrayAttri1 dense array attribute
portLocations::mlir::ArrayAttrarray attribute
portAnnotations::mlir::ArrayAttrarray attribute
portSyms::mlir::ArrayAttrarray attribute
portNames::mlir::ArrayAttrarray attribute
portTypes::mlir::ArrayAttrarray attribute
annotations::mlir::ArrayAttrAnnotation array attribute
layers::mlir::ArrayAttran array of layers
internalPaths::mlir::ArrayAttrInternalPath array attribute

firrtl.intmodule (::circt::firrtl::FIntModuleOp)

FIRRTL intrinsic module

The “firrtl.intmodule” operation represents a compiler intrinsic.

Traits: HasParent<CircuitOp>, InnerSymbolTable, IsolatedFromAbove

Interfaces: FModuleLike, InstanceGraphModuleOpInterface, ModuleOpInterface, OpAsmOpInterface, PortList, SymbolUserOpInterface, Symbol

Attributes:

AttributeMLIR TypeDescription
intrinsic::mlir::StringAttrstring attribute
parameters::mlir::ArrayAttrparameter array attribute
portDirections::mlir::DenseBoolArrayAttri1 dense array attribute
portLocations::mlir::ArrayAttrarray attribute
portAnnotations::mlir::ArrayAttrarray attribute
portSyms::mlir::ArrayAttrarray attribute
portNames::mlir::ArrayAttrarray attribute
portTypes::mlir::ArrayAttrarray attribute
annotations::mlir::ArrayAttrAnnotation array attribute
layers::mlir::ArrayAttran array of layers
internalPaths::mlir::ArrayAttrInternalPath array attribute

firrtl.memmodule (::circt::firrtl::FMemModuleOp)

FIRRTL Generated Memory Module

The “firrtl.memmodule” operation represents an external reference to a memory module. See the “firrtl.mem” op for a deeper explantation of the parameters.

A “firrtl.mem” operation is typically lowered to this operation when they are not directly lowered to registers by the compiler.

Traits: HasParent<CircuitOp>, InnerSymbolTable, IsolatedFromAbove

Interfaces: FModuleLike, InstanceGraphModuleOpInterface, ModuleOpInterface, OpAsmOpInterface, PortList, SymbolUserOpInterface, Symbol

Attributes:

AttributeMLIR TypeDescription
numReadPorts::mlir::IntegerAttr32-bit unsigned integer attribute
numWritePorts::mlir::IntegerAttr32-bit unsigned integer attribute
numReadWritePorts::mlir::IntegerAttr32-bit unsigned integer attribute
dataWidth::mlir::IntegerAttr32-bit unsigned integer attribute
maskBits::mlir::IntegerAttr32-bit unsigned integer attribute
readLatency::mlir::IntegerAttr32-bit unsigned integer attribute
writeLatency::mlir::IntegerAttr32-bit unsigned integer attribute
depth::mlir::IntegerAttr64-bit unsigned integer attribute
extraPorts::mlir::ArrayAttrarray attribute
portDirections::mlir::DenseBoolArrayAttri1 dense array attribute
portLocations::mlir::ArrayAttrarray attribute
portAnnotations::mlir::ArrayAttrarray attribute
portSyms::mlir::ArrayAttrarray attribute
portNames::mlir::ArrayAttrarray attribute
portTypes::mlir::ArrayAttrarray attribute
annotations::mlir::ArrayAttrAnnotation array attribute
layers::mlir::ArrayAttran array of layers

firrtl.module (::circt::firrtl::FModuleOp)

FIRRTL Module

The “firrtl.module” operation represents a Verilog module, including a given name, a list of ports, and a body that represents the connections within the module.

Traits: HasParent<CircuitOp>, InnerSymbolTable, IsolatedFromAbove, NoTerminator, SingleBlock

Interfaces: FModuleLike, InstanceGraphModuleOpInterface, ModuleOpInterface, OpAsmOpInterface, PortList, SymbolUserOpInterface, Symbol

Attributes:

AttributeMLIR TypeDescription
convention::circt::firrtl::ConventionAttrlowering convention
portDirections::mlir::DenseBoolArrayAttri1 dense array attribute
portLocations::mlir::ArrayAttrarray attribute
portAnnotations::mlir::ArrayAttrarray attribute
portSyms::mlir::ArrayAttrarray attribute
portNames::mlir::ArrayAttrarray attribute
portTypes::mlir::ArrayAttrarray attribute
annotations::mlir::ArrayAttrAnnotation array attribute
layers::mlir::ArrayAttran array of layers

firrtl.layer (::circt::firrtl::LayerOp)

A layer definition

Syntax:

operation ::= `firrtl.layer` $sym_name $convention attr-dict-with-keyword $body

The firrtl.layer operation defines a layer and a lowering convention for that layer. Layers are a feature of FIRRTL that add verification or debugging code to an existing module at runtime.

A firrtl.layer operation only defines the layer and any layers nested under it. Functionality is added to modules using the firrtl.group operation.

Traits: HasParent<firrtl::CircuitOp, firrtl::LayerOp>, IsolatedFromAbove, NoTerminator, SingleBlock, SymbolTable

Interfaces: Symbol

Attributes:

AttributeMLIR TypeDescription
sym_name::mlir::StringAttrstring attribute
convention::circt::firrtl::LayerConventionAttrlayer convention

firrtl.option_case (::circt::firrtl::OptionCaseOp)

A configuration option value definition

Syntax:

operation ::= `firrtl.option_case` $sym_name attr-dict

firrtl.option_case defines an acceptable value to be provided for an option. Ops reference it to define their behavior when this case is active.

Traits: HasParent<firrtl::OptionOp>

Interfaces: Symbol

Attributes:

AttributeMLIR TypeDescription
sym_name::mlir::StringAttrstring attribute

firrtl.option (::circt::firrtl::OptionOp)

An option group definition

Syntax:

operation ::= `firrtl.option` $sym_name attr-dict-with-keyword $body

The firrtl.option operation defines a specializable parameter with a known set of values, represented by the firrtl.option_case operations nested underneath.

Operations which support specialization reference the option and its cases to define the specializations they support.

Example:


firrtl.circuit {
  firrtl.option @Target {
    firrtl.option_case @FPGA
    firrtl.option_case @ASIC
  }
}

Traits: HasParent<firrtl::CircuitOp>, IsolatedFromAbove, NoTerminator, SymbolTable

Interfaces: Symbol

Attributes:

AttributeMLIR TypeDescription
sym_name::mlir::StringAttrstring attribute

Operation Definitions – Declarations

firrtl.instance_choice (::circt::firrtl::InstanceChoiceOp)

Creates an instance of a module based on a option

The instance choice operation creates an instance choosing the target based on the value of an option if one is specified, instantiating a default target otherwise.

The port lists of all instance targets must match exactly.

Examples:

%0 = firrtl.instance_choice foo @Foo alternatives @Opt { @FPGA -> @FPGAFoo }
  (in io: !firrtl.uint)

Traits: HasParent<firrtl::FModuleOp, firrtl::LayerBlockOp, firrtl::WhenOp, firrtl::MatchOp>

Interfaces: FNamableOp, HasCustomSSAName, InnerSymbolOpInterface, SymbolUserOpInterface

Attributes:

AttributeMLIR TypeDescription
moduleNames::mlir::ArrayAttrflat symbol ref array attribute
caseNames::mlir::ArrayAttrsymbol ref array attribute
name::mlir::StringAttrstring attribute
nameKind::circt::firrtl::NameKindEnumAttrname kind
portDirections::mlir::DenseBoolArrayAttri1 dense array attribute
portNames::mlir::ArrayAttrstring array attribute
annotations::mlir::ArrayAttrAnnotation array attribute
portAnnotations::mlir::ArrayAttrPort annotations attribute
layers::mlir::ArrayAttran array of layers
inner_sym::circt::hw::InnerSymAttrInner symbol definition

Results:

ResultDescription
resultsvariadic of any type

firrtl.instance (::circt::firrtl::InstanceOp)

Instantiate an instance of a module

This represents an instance of a module. The results are the modules inputs and outputs. The inputs have flip type, the outputs do not.

Examples:

%0 = firrtl.instance foo @Foo(in io: !firrtl.uint)

Traits: HasParent<firrtl::FModuleOp, firrtl::LayerBlockOp, firrtl::WhenOp, firrtl::MatchOp>

Interfaces: FInstanceLike, FNamableOp, HasCustomSSAName, InnerSymbolOpInterface, InstanceGraphInstanceOpInterface, InstanceOpInterface, SymbolUserOpInterface

Attributes:

AttributeMLIR TypeDescription
moduleName::mlir::FlatSymbolRefAttrflat symbol reference attribute
name::mlir::StringAttrstring attribute
nameKind::circt::firrtl::NameKindEnumAttrname kind
portDirections::mlir::DenseBoolArrayAttri1 dense array attribute
portNames::mlir::ArrayAttrstring array attribute
annotations::mlir::ArrayAttrAnnotation array attribute
portAnnotations::mlir::ArrayAttrPort annotations attribute
layers::mlir::ArrayAttran array of layers
lowerToBind::mlir::UnitAttrunit attribute
inner_sym::circt::hw::InnerSymAttrInner symbol definition

Results:

ResultDescription
resultsvariadic of any type

firrtl.mem (::circt::firrtl::MemOp)

Define a new mem

Syntax:

operation ::= `firrtl.mem` (`sym` $inner_sym^)? `` custom<NameKind>($nameKind)
              $ruw `` custom<MemOp>(attr-dict) `:` qualified(type($results))

Traits: HasParent<firrtl::FModuleOp, firrtl::LayerBlockOp, firrtl::WhenOp, firrtl::MatchOp>

Interfaces: FNamableOp, HasCustomSSAName, InnerSymbolOpInterface

Attributes:

AttributeMLIR TypeDescription
readLatency::mlir::IntegerAttr32-bit signless integer attribute whose minimum value is 0
writeLatency::mlir::IntegerAttr32-bit signless integer attribute whose minimum value is 1
depth::mlir::IntegerAttr64-bit signless integer attribute whose minimum value is 1
ruw::circt::firrtl::RUWAttrAttrRead Under Write Enum
portNames::mlir::ArrayAttrstring array attribute
name::mlir::StringAttrstring attribute
nameKind::circt::firrtl::NameKindEnumAttrname kind
annotations::mlir::ArrayAttrAnnotation array attribute
portAnnotations::mlir::ArrayAttrPort annotations attribute
inner_sym::circt::hw::InnerSymAttrInner symbol definition
init::circt::firrtl::MemoryInitAttrInformation about the initial state of a memory
prefix::mlir::StringAttrstring attribute

Results:

ResultDescription
resultsvariadic of FIRRTLType

firrtl.node (::circt::firrtl::NodeOp)

No-op to name a value

Syntax:

operation ::= `firrtl.node` (`sym` $inner_sym^)? `` custom<NameKind>($nameKind)
              $input (`forceable` $forceable^)? `` custom<FIRRTLImplicitSSAName>(attr-dict) `:` qualified(type($input))

A node is simply a named intermediate value in a circuit. The node must be initialized to a value with a passive type and cannot be connected to. Nodes are often used to split a complicated compound expression into named subexpressions.

  %result = firrtl.node %input : t1

Traits: HasParent<firrtl::FModuleOp, firrtl::LayerBlockOp, firrtl::WhenOp, firrtl::MatchOp>

Interfaces: FNamableOp, Forceable, HasCustomSSAName, InferTypeOpInterface, InnerSymbolOpInterface

Attributes:

AttributeMLIR TypeDescription
name::mlir::StringAttrstring attribute
nameKind::circt::firrtl::NameKindEnumAttrname kind
annotations::mlir::ArrayAttrAnnotation array attribute
inner_sym::circt::hw::InnerSymAttrInner symbol definition
forceable::mlir::UnitAttrunit attribute

Operands:

OperandDescription
inputa passive base type (contain no flips)

Results:

ResultDescription
resulta base type
refreference type

firrtl.object (::circt::firrtl::ObjectOp)

Instantiate a class to produce an object

Syntax:

operation ::= `firrtl.object` `` custom<ImplicitSSAName>(attr-dict) custom<ClassInterface>(type($result))

This represents an instance of a class. The results is the instantiated object.

Examples:

%0 = firrtl.object @Foo(in io: !firrtl.uint)

Traits: HasParent<firrtl::FModuleOp, firrtl::ClassOp>

Interfaces: FInstanceLike, InstanceGraphInstanceOpInterface, InstanceOpInterface, OpAsmOpInterface, SymbolUserOpInterface

Attributes:

AttributeMLIR TypeDescription
name::mlir::StringAttrstring attribute

Results:

ResultDescription
resultclass type

firrtl.reg (::circt::firrtl::RegOp)

Define a new register

Syntax:

operation ::= `firrtl.reg` (`sym` $inner_sym^)? `` custom<NameKind>($nameKind)
              operands (`forceable` $forceable^)? `` custom<FIRRTLImplicitSSAName>(attr-dict) `:` type($clockVal) `,` qualified(type($result)) (`,` qualified(type($ref))^)?

Declare a new register:

%name = firrtl.reg %clockVal : !firrtl.clock, t1

Traits: HasParent<firrtl::FModuleOp, firrtl::LayerBlockOp, firrtl::WhenOp, firrtl::MatchOp>

Interfaces: FNamableOp, Forceable, HasCustomSSAName, InnerSymbolOpInterface

Attributes:

AttributeMLIR TypeDescription
name::mlir::StringAttrstring attribute
nameKind::circt::firrtl::NameKindEnumAttrname kind
annotations::mlir::ArrayAttrAnnotation array attribute
inner_sym::circt::hw::InnerSymAttrInner symbol definition
forceable::mlir::UnitAttrunit attribute

Operands:

OperandDescription
clockValclock

Results:

ResultDescription
resulta passive non-‘const’ base type that does not contain analog
refreference type

firrtl.regreset (::circt::firrtl::RegResetOp)

Define a new register with a reset

Syntax:

operation ::= `firrtl.regreset` (`sym` $inner_sym^)? `` custom<NameKind>($nameKind)
              operands (`forceable` $forceable^)? `` custom<FIRRTLImplicitSSAName>(attr-dict)
              `:` type($clockVal) `,` qualified(type($resetSignal)) `,` qualified(type($resetValue)) `,` qualified(type($result)) (`,` qualified(type($ref))^)?

Declare a new register:

  %name = firrtl.regreset %clockVal, %resetSignal, %resetValue : !firrtl.clock, t1

Traits: HasParent<firrtl::FModuleOp, firrtl::LayerBlockOp, firrtl::WhenOp, firrtl::MatchOp>

Interfaces: FNamableOp, Forceable, HasCustomSSAName, InnerSymbolOpInterface

Attributes:

AttributeMLIR TypeDescription
name::mlir::StringAttrstring attribute
nameKind::circt::firrtl::NameKindEnumAttrname kind
annotations::mlir::ArrayAttrAnnotation array attribute
inner_sym::circt::hw::InnerSymAttrInner symbol definition
forceable::mlir::UnitAttrunit attribute

Operands:

OperandDescription
clockValclock
resetSignalReset
resetValuea base type

Results:

ResultDescription
resulta passive non-‘const’ base type that does not contain analog
refreference type

firrtl.wire (::circt::firrtl::WireOp)

Define a new wire

Syntax:

operation ::= `firrtl.wire` (`sym` $inner_sym^)? `` custom<NameKind>($nameKind)
              (`forceable` $forceable^)? `` custom<FIRRTLImplicitSSAName>(attr-dict) `:`
              qualified(type($result)) (`,` qualified(type($ref))^)?

Declare a new wire:

  %name = firrtl.wire : t1

Traits: HasParent<firrtl::FModuleOp, firrtl::LayerBlockOp, firrtl::WhenOp, firrtl::MatchOp>

Interfaces: FNamableOp, Forceable, HasCustomSSAName, InnerSymbolOpInterface, SymbolUserOpInterface

Attributes:

AttributeMLIR TypeDescription
name::mlir::StringAttrstring attribute
nameKind::circt::firrtl::NameKindEnumAttrname kind
annotations::mlir::ArrayAttrAnnotation array attribute
inner_sym::circt::hw::InnerSymAttrInner symbol definition
forceable::mlir::UnitAttrunit attribute

Results:

ResultDescription
resultany type
refreference type

Statement Operation – Statements

firrtl.assert (::circt::firrtl::AssertOp)

Assert Verification Statement

Syntax:

operation ::= `firrtl.assert` $clock `,` $predicate `,` $enable `,`
              $message (`(` $substitutions^ `)`)? `:` type($clock) `,` type($predicate) `,` type($enable) (`,` qualified(type($substitutions))^)?
              custom<VerifAttrs>(attr-dict)

Attributes:

AttributeMLIR TypeDescription
message::mlir::StringAttrstring attribute
name::mlir::StringAttrstring attribute
isConcurrent::mlir::BoolAttrbool attribute
eventControl::circt::firrtl::EventControlAttredge control trigger

Operands:

OperandDescription
clockclock
predicate1-bit uint
enable1-bit uint
substitutionsvariadic of any type

firrtl.assume (::circt::firrtl::AssumeOp)

Assume Verification Statement

Syntax:

operation ::= `firrtl.assume` $clock `,` $predicate `,` $enable `,`
              $message (`(` $substitutions^ `)`)? `:` type($clock) `,` type($predicate) `,` type($enable) (`,` qualified(type($substitutions))^)?
              custom<VerifAttrs>(attr-dict)

Attributes:

AttributeMLIR TypeDescription
message::mlir::StringAttrstring attribute
name::mlir::StringAttrstring attribute
isConcurrent::mlir::BoolAttrbool attribute
eventControl::circt::firrtl::EventControlAttredge control trigger

Operands:

OperandDescription
clockclock
predicate1-bit uint
enable1-bit uint
substitutionsvariadic of any type

firrtl.attach (::circt::firrtl::AttachOp)

Analog Attach Statement

Syntax:

operation ::= `firrtl.attach` $attached attr-dict `:` qualified(type($attached))

Operands:

OperandDescription
attachedvariadic of analog type

firrtl.connect (::circt::firrtl::ConnectOp)

Connect two signals

Syntax:

operation ::= `firrtl.connect` $dest `,` $src  attr-dict `:` qualified(type($dest)) `,` qualified(type($src))

Connect Operation:

  firrtl.connect %dest, %src : t1, t2

Interfaces: FConnectLike

Operands:

OperandDescription
desta base type or foreign type
srca base type or foreign type

firrtl.cover (::circt::firrtl::CoverOp)

Cover Verification Statement

Syntax:

operation ::= `firrtl.cover` $clock `,` $predicate `,` $enable `,`
              $message (`(` $substitutions^ `)`)? `:` type($clock) `,` type($predicate) `,` type($enable) (`,` qualified(type($substitutions))^)?
              custom<VerifAttrs>(attr-dict)

Attributes:

AttributeMLIR TypeDescription
message::mlir::StringAttrstring attribute
name::mlir::StringAttrstring attribute
isConcurrent::mlir::BoolAttrbool attribute
eventControl::circt::firrtl::EventControlAttredge control trigger

Operands:

OperandDescription
clockclock
predicate1-bit uint
enable1-bit uint
substitutionsvariadic of any type

firrtl.force (::circt::firrtl::ForceOp)

Force procedural statement

Syntax:

operation ::= `firrtl.force` $dest `,` $src attr-dict `:` qualified(type($dest)) `,` qualified(type($src))

Maps to the corresponding sv.force operation. Traits: SameTypeOperands

Operands:

OperandDescription
desta base type
srca base type

firrtl.layerblock (::circt::firrtl::LayerBlockOp)

A definition of a layer block

Syntax:

operation ::= `firrtl.layerblock` $layerName $region attr-dict

The firrtl.layerblock operation defines optional code that is conditionally part of a firrtl.module if its referenced firrtl.layer is enabled. This is typically used to store verification or debugging code that is lowered to a module that is “enabled” using the firrtl.layer’s convention (e.g., remote instantiation via SystemVerilog bind). A layer block can read from (capture) values defined in parent layer blocks or in the parent module, but may not write to hardware declared outside the layer block.

A firrtl.layerblock must refer to an existing layer definition (firrtl.layer) via a symbol reference. A nested firrtl.layerblock refers to a nested layer definition via a nested symbol reference.

Traits: HasParent<firrtl::FModuleOp, firrtl::LayerBlockOp>, NoRegionArguments, NoTerminator, SingleBlock

Interfaces: SymbolUserOpInterface

Attributes:

AttributeMLIR TypeDescription
layerName::mlir::SymbolRefAttrsymbol reference attribute

firrtl.match (::circt::firrtl::MatchOp)

Match Statement

The “firrtl.match” operation represents a pattern matching statement on a enumeration. This operation does not return a value and cannot be used as an expression. Last connect semantics work similarly to a when statement.

Example:

  firrtl.match %in : !firrtl.enum<Some: uint<1>, None: uint<0>> {
    case Some(%arg0) {
      !firrtl.strictconnect %w, %arg0 : !firrtl.uint<1>
    }
    case None(%arg0) {
      !firrt.strictconnect %w, %c1 : !firrtl.uint<1>
    }
  }

Traits: NoTerminator, RecursiveMemoryEffects, RecursivelySpeculatableImplTrait, SingleBlock

Interfaces: ConditionallySpeculatable

Attributes:

AttributeMLIR TypeDescription
tags::mlir::ArrayAttr32-bit integer array attribute

Operands:

OperandDescription
inputenum type

firrtl.printf (::circt::firrtl::PrintFOp)

Formatted Print Statement

Syntax:

operation ::= `firrtl.printf` $clock `,` $cond `,` $formatString `` custom<PrintfAttrs>(attr-dict) ` `
              (`(` $substitutions^ `)`)? `:` type($clock) `,` type($cond) (`,` qualified(type($substitutions))^)?

Attributes:

AttributeMLIR TypeDescription
formatString::mlir::StringAttrstring attribute
name::mlir::StringAttrstring attribute

Operands:

OperandDescription
clockclock
cond1-bit uint
substitutionsvariadic of a base type

firrtl.propassign (::circt::firrtl::PropAssignOp)

Assign to a sink property value.

Syntax:

operation ::= `firrtl.propassign` $dest `,` $src attr-dict `:` qualified(type($dest))

Assign an output property value. The types must match exactly.

Example:

  firrtl.propassign %dest, %src : !firrtl.string

Traits: HasParent<FModuleOp, ClassOp, LayerBlockOp>, SameTypeOperands

Interfaces: FConnectLike

Operands:

OperandDescription
destproperty type
srcproperty type

firrtl.ref.define (::circt::firrtl::RefDefineOp)

FIRRTL Define References

Syntax:

operation ::= `firrtl.ref.define` $dest `,` $src  attr-dict `:` qualified(type($dest))

Define a target reference to the source reference:

  firrtl.ref.define %dest, %src : ref<t1>

Used to statically route reference from source to destination through the design, one module at a time.

Similar to “connect” but cannot have multiple define’s to same destination and the define is never conditional even if under a “when”.

Source and destination must resolve statically.

Traits: SameTypeOperands

Interfaces: FConnectLike

Operands:

OperandDescription
destreference type
srcreference type

firrtl.ref.force_initial (::circt::firrtl::RefForceInitialOp)

FIRRTL force_initial statement

Syntax:

operation ::= `firrtl.ref.force_initial` $predicate `,` $dest `,` $src attr-dict `:` type($predicate) `,` qualified(type($src))

Force a RWProbe to the specified value continuously.

Operands:

OperandDescription
predicate1-bit uint
destrwprobe type
srca base type

firrtl.ref.force (::circt::firrtl::RefForceOp)

FIRRTL force statement

Syntax:

operation ::= `firrtl.ref.force` $clock `,` $predicate `,` $dest `,` $src attr-dict `:` type($clock) `,` type($predicate) `,` qualified(type($src))

Force a RWProbe to the specified value using the specified clock and predicate.

Operands:

OperandDescription
clockclock
predicate1-bit uint
destrwprobe type
srca base type

firrtl.ref.release_initial (::circt::firrtl::RefReleaseInitialOp)

FIRRTL release_initial statement

Syntax:

operation ::= `firrtl.ref.release_initial` $predicate `,` $dest attr-dict `:` type($predicate) `,` qualified(type($dest))

Release the target RWProbe.

Operands:

OperandDescription
predicate1-bit uint
destrwprobe type

firrtl.ref.release (::circt::firrtl::RefReleaseOp)

FIRRTL release statement

Syntax:

operation ::= `firrtl.ref.release` $clock `,` $predicate `,` $dest attr-dict `:` type($clock) `,` type($predicate) `,` qualified(type($dest))

Release the target RWProbe using the specified clock and predicate.

Operands:

OperandDescription
clockclock
predicate1-bit uint
destrwprobe type

firrtl.skip (::circt::firrtl::SkipOp)

Skip statement

Syntax:

operation ::= `firrtl.skip` attr-dict

Skip Statement:

   %firrtl.skip

This is a no-op statement.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

firrtl.stop (::circt::firrtl::StopOp)

Stop Statement

Syntax:

operation ::= `firrtl.stop` $clock `,` $cond `,` $exitCode `` custom<StopAttrs>(attr-dict) `:` type($clock) `,` type($cond)

Attributes:

AttributeMLIR TypeDescription
exitCode::mlir::IntegerAttr32-bit signless integer attribute
name::mlir::StringAttrstring attribute

Operands:

OperandDescription
clockclock
cond1-bit uint

firrtl.strictconnect (::circt::firrtl::StrictConnectOp)

Connect two signals

Syntax:

operation ::= `firrtl.strictconnect` $dest `,` $src  attr-dict `:`
              custom<OptionalBinaryOpTypes>(type($dest), type($src))

Connect two values with strict constraints:

  firrtl.strictconnect %dest, %src : t1
  firrtl.strictconnect %dest, %src : t1, !firrtl.alias<foo, t1>

Interfaces: FConnectLike

Operands:

OperandDescription
desta sized passive base type (contains no uninferred widths, or flips) or foreign type
srca sized passive base type (contains no uninferred widths, or flips) or foreign type

firrtl.int.verif.assert (::circt::firrtl::VerifAssertIntrinsicOp)

FIRRTL variant of verif.assert

Syntax:

operation ::= `firrtl.int.verif.assert` operands attr-dict `:` type(operands)

See verif.assert op in the Verif dialect.

Attributes:

AttributeMLIR TypeDescription
label::mlir::StringAttrstring attribute

Operands:

OperandDescription
property1-bit uint

firrtl.int.verif.assume (::circt::firrtl::VerifAssumeIntrinsicOp)

FIRRTL variant of verif.assume

Syntax:

operation ::= `firrtl.int.verif.assume` operands attr-dict `:` type(operands)

See verif.assume op in the Verif dialect.

Attributes:

AttributeMLIR TypeDescription
label::mlir::StringAttrstring attribute

Operands:

OperandDescription
property1-bit uint

firrtl.int.verif.cover (::circt::firrtl::VerifCoverIntrinsicOp)

FIRRTL variant of verif.cover

Syntax:

operation ::= `firrtl.int.verif.cover` operands attr-dict `:` type(operands)

See verif.cover op in the Verif dialect.

Attributes:

AttributeMLIR TypeDescription
label::mlir::StringAttrstring attribute

Operands:

OperandDescription
property1-bit uint

firrtl.when (::circt::firrtl::WhenOp)

When Statement

Syntax:

operation ::= `firrtl.when` $condition `:` type($condition) $thenRegion (`else` $elseRegion^)? attr-dict-with-keyword

The “firrtl.when” operation represents a conditional. Connections within a conditional statement that connect to previously declared components hold only when the given condition is high. The condition must have a 1-bit unsigned integer type.

Traits: NoRegionArguments, NoTerminator, SingleBlock

Operands:

OperandDescription
condition1-bit uint

Operation Definitions – Expressions

firrtl.add (::circt::firrtl::AddPrimOp)

Syntax:

operation ::= `firrtl.add` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Traits: AlwaysSpeculatableImplTrait, Commutative, SameOperandsIntTypeKind

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhssint or uint type

Results:

ResultDescription
resultsint or uint type

firrtl.aggregateconstant (::circt::firrtl::AggregateConstantOp)

Produce a constant of a passive aggregate value

Syntax:

operation ::= `firrtl.aggregateconstant` $fields attr-dict `:` type($result)

The constant operation produces a constant value of an aggregate type. The type must be passive. Clock and reset values are supported. For nested aggregates, embedded arrays are used.

  %result = firrtl.aggregateconstant [1, 2, 3] : !firrtl.bundle<a: uint<8>, b: uint<5>, c: uint<4>>
  %result = firrtl.aggregateconstant [1, 2, 3] : !firrtl.vector<uint<8>, 3>
  %result = firrtl.aggregateconstant [[1, 2], [3, 5]] : !firrtl.vector<!firrtl.bundle<a: uint<8>, b: uint<5>>, 2>

Traits: AlwaysSpeculatableImplTrait, ConstantLike

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
fields::mlir::ArrayAttrarray attribute

Results:

ResultDescription
resulta aggregate type

firrtl.and (::circt::firrtl::AndPrimOp)

Syntax:

operation ::= `firrtl.and` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Traits: AlwaysSpeculatableImplTrait, Commutative, SameOperandsIntTypeKind

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhssint or uint type

Results:

ResultDescription
resultuint type

firrtl.andr (::circt::firrtl::AndRPrimOp)

Syntax:

operation ::= `firrtl.andr` $input attr-dict `:` functional-type($input, $result)

Horizontally reduce a value to one bit, using the ‘and’ operation to merge bits. andr(x) is equivalent to concat(x, 1b1) == ~0. As such, it returns 1 for zero-bit-wide operands.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
inputsint or uint type

Results:

ResultDescription
result1-bit uint

firrtl.asAsyncReset (::circt::firrtl::AsAsyncResetPrimOp)

Syntax:

operation ::= `firrtl.asAsyncReset` $input attr-dict `:` functional-type($input, $result)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
input1-bit uint/sint/analog, reset, asyncreset, or clock

Results:

ResultDescription
resultasync reset type

firrtl.asClock (::circt::firrtl::AsClockPrimOp)

Syntax:

operation ::= `firrtl.asClock` $input attr-dict `:` functional-type($input, $result)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
input1-bit uint/sint/analog, reset, asyncreset, or clock

Results:

ResultDescription
resultclock

firrtl.asSInt (::circt::firrtl::AsSIntPrimOp)

Syntax:

operation ::= `firrtl.asSInt` $input attr-dict `:` functional-type($input, $result)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
inputa base type

Results:

ResultDescription
resultsint type

firrtl.asUInt (::circt::firrtl::AsUIntPrimOp)

Syntax:

operation ::= `firrtl.asUInt` $input attr-dict `:` functional-type($input, $result)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
inputa base type

Results:

ResultDescription
resultuint type

firrtl.bitcast (::circt::firrtl::BitCastOp)

Reinterpret one value to another value of the same size and potentially different type. This op is lowered to hw::BitCastOp.

Syntax:

operation ::= `firrtl.bitcast` $input attr-dict `:` functional-type($input, $result)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
inputa base type

Results:

ResultDescription
resulta passive base type (contain no flips)

firrtl.bits (::circt::firrtl::BitsPrimOp)

Syntax:

operation ::= `firrtl.bits` $input $hi `to` $lo attr-dict `:` functional-type($input, $result)

The bits operation extracts the bits between hi (inclusive) and lo (inclusive) from input. hi must be greater than or equal to lo. Both hi and lo must be non-negative and less than the bit width of input. The result is hi - lo + 1 bits wide.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
hi::mlir::IntegerAttr32-bit signless integer attribute
lo::mlir::IntegerAttr32-bit signless integer attribute

Operands:

OperandDescription
inputsint or uint type

Results:

ResultDescription
resultuint type

firrtl.bool (::circt::firrtl::BoolConstantOp)

Produce a constant boolean value

Syntax:

operation ::= `firrtl.bool` $value attr-dict

Produces a constant value of boolean type.

Example:

%0 = firrtl.bool true

Traits: AlwaysSpeculatableImplTrait, ConstantLike

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
value::mlir::BoolAttrbool attribute

Results:

ResultDescription
resultboolean type

firrtl.bundlecreate (::circt::firrtl::BundleCreateOp)

Produce a bundle value

Syntax:

operation ::= `firrtl.bundlecreate` $fields attr-dict `:` functional-type($fields, $result)

Create an bundle from component values. This is equivalent in terms of flow to creating a node.

  %result = firrtl.bundlecreate %1, %2, %3 : !firrtl.bundle<a: uint<8>, b: uint<5>, c: uint<4>>

Operands:

OperandDescription
fieldsvariadic of a base type

Results:

ResultDescription
resultbundle type

firrtl.cat (::circt::firrtl::CatPrimOp)

Syntax:

operation ::= `firrtl.cat` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Traits: AlwaysSpeculatableImplTrait, SameOperandsIntTypeKind

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhssint or uint type

Results:

ResultDescription
resultuint type

firrtl.constCast (::circt::firrtl::ConstCastOp)

Syntax:

operation ::= `firrtl.constCast` $input attr-dict `:` functional-type($input, $result)

Cast from a ‘const’ to a non-‘const’ type.

%result = firrtl.constCast %in : (!firrtl.const.t1) -> !firrtl.t1

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
inputa passive base type (contain no flips)

Results:

ResultDescription
resulta passive base type (contain no flips)

firrtl.constant (::circt::firrtl::ConstantOp)

Produce a constant value

The constant operation produces a constant value of SInt or UInt type, it never produces a zero bit wide result.

  %result = firrtl.constant 42 : t1

Traits: AlwaysSpeculatableImplTrait, ConstantLike, FirstAttrDerivedResultType

Interfaces: ConditionallySpeculatable, HasCustomSSAName, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
value::mlir::IntegerAttrarbitrary integer attribute with sign

Results:

ResultDescription
resultsint or uint type

firrtl.cvt (::circt::firrtl::CvtPrimOp)

Syntax:

operation ::= `firrtl.cvt` $input attr-dict `:` functional-type($input, $result)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
inputsint or uint type

Results:

ResultDescription
resultsint type

firrtl.dshl (::circt::firrtl::DShlPrimOp)

Syntax:

operation ::= `firrtl.dshl` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

A dynamic shift left operation. The width of $result is expanded to width($lhs) + 1 << width($rhs) - 1.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhsuint type

Results:

ResultDescription
resultsint or uint type

firrtl.dshlw (::circt::firrtl::DShlwPrimOp)

Syntax:

operation ::= `firrtl.dshlw` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

A dynamic shift left operation same as ‘dshl’ but with different width rule. The width of $result is equal to $lhs.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhsuint type

Results:

ResultDescription
resultsint or uint type

firrtl.dshr (::circt::firrtl::DShrPrimOp)

Syntax:

operation ::= `firrtl.dshr` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhsuint type

Results:

ResultDescription
resultsint or uint type

firrtl.div (::circt::firrtl::DivPrimOp)

Syntax:

operation ::= `firrtl.div` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Divides the first argument (the numerator) by the second argument (the denominator) truncating the result (rounding towards zero).

If the denominator is zero, the result is undefined.

The compiler may optimize this undefined behavior in any way it wants. Notably div(a, a) will be optimized to 1. This may cause erroneous formal equivalence mismatches between unoptimized and optimized FIRRTL dialects that are separately converted to Verilog.

Traits: AlwaysSpeculatableImplTrait, SameOperandsIntTypeKind

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhssint or uint type

Results:

ResultDescription
resultsint or uint type

firrtl.double (::circt::firrtl::DoubleConstantOp)

Produce a constant double value

Syntax:

operation ::= `firrtl.double` $value attr-dict

Produces a constant value of double type.

Example:

%0 = firrtl.double 3.2

Traits: AlwaysSpeculatableImplTrait, ConstantLike

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
value::mlir::FloatAttrdouble-precision float

Results:

ResultDescription
resultdouble type

firrtl.eq (::circt::firrtl::EQPrimOp)

Syntax:

operation ::= `firrtl.eq` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Traits: AlwaysSpeculatableImplTrait, Commutative, SameOperandsIntTypeKind

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhssint or uint type

Results:

ResultDescription
result1-bit uint

firrtl.elementwise_and (::circt::firrtl::ElementwiseAndPrimOp)

Syntax:

operation ::= `firrtl.elementwise_and` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Traits: AlwaysSpeculatableImplTrait, Commutative

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhs1d vector with Int element type
rhs1d vector with Int element type

Results:

ResultDescription
result1d vector with UInt element type

firrtl.elementwise_or (::circt::firrtl::ElementwiseOrPrimOp)

Syntax:

operation ::= `firrtl.elementwise_or` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Traits: AlwaysSpeculatableImplTrait, Commutative

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhs1d vector with Int element type
rhs1d vector with Int element type

Results:

ResultDescription
result1d vector with UInt element type

firrtl.elementwise_xor (::circt::firrtl::ElementwiseXorPrimOp)

Syntax:

operation ::= `firrtl.elementwise_xor` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Traits: AlwaysSpeculatableImplTrait, Commutative

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhs1d vector with UInt element type
rhs1d vector with Int element type

Results:

ResultDescription
result1d vector with UInt element type

firrtl.enumcreate (::circt::firrtl::FEnumCreateOp)

Produce a enum value

Create an enum from tag and value.

  %result = firrtl.enumcreate field-name(%input) : !firrtl.enum<None: uint<0>, Some: uint<8>>

Attributes:

AttributeMLIR TypeDescription
fieldIndex::mlir::IntegerAttr32-bit signless integer attribute

Operands:

OperandDescription
inputa base type

Results:

ResultDescription
resultenum type

firrtl.integer (::circt::firrtl::FIntegerConstantOp)

Produce a constant integer value

Produces a constant value of integer type.

Example:

%0 = firrtl.integer 42

Traits: AlwaysSpeculatableImplTrait, ConstantLike

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
value::mlir::IntegerAttrarbitrary integer attribute with sign

Results:

ResultDescription
resultinteger type

firrtl.geq (::circt::firrtl::GEQPrimOp)

Syntax:

operation ::= `firrtl.geq` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Traits: AlwaysSpeculatableImplTrait, SameOperandsIntTypeKind

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhssint or uint type

Results:

ResultDescription
result1-bit uint

firrtl.gt (::circt::firrtl::GTPrimOp)

Syntax:

operation ::= `firrtl.gt` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Traits: AlwaysSpeculatableImplTrait, SameOperandsIntTypeKind

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhssint or uint type

Results:

ResultDescription
result1-bit uint

firrtl.hwStructCast (::circt::firrtl::HWStructCastOp)

Syntax:

operation ::= `firrtl.hwStructCast` $input attr-dict `:` functional-type($input, $result)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
inputany type

Results:

ResultDescription
resultany type

firrtl.head (::circt::firrtl::HeadPrimOp)

Syntax:

operation ::= `firrtl.head` $input `,` $amount attr-dict `:` functional-type($input, $result)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
amount::mlir::IntegerAttr32-bit signless integer attribute

Operands:

OperandDescription
inputsint or uint type

Results:

ResultDescription
resultuint type

firrtl.integer.add (::circt::firrtl::IntegerAddOp)

Add two FIntegerType values

Syntax:

operation ::= `firrtl.integer.add` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

The add operation result is the arbitrary precision signed integer arithmetic sum of the two operands.

Example:

%2 = firrtl.integer.add %0, %1 : (!firrtl.integer, !firrtl.integer) ->
                                     !firrtl.integer

Traits: AlwaysSpeculatableImplTrait, Commutative, SameOperandsAndResultType

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhsinteger type
rhsinteger type

Results:

ResultDescription
resultinteger type

firrtl.integer.mul (::circt::firrtl::IntegerMulOp)

Multiply two FIntegerType values

Syntax:

operation ::= `firrtl.integer.mul` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

The multiply operation result is the arbitrary precision signed integer arithmetic product of the two operands.

Example:

%2 = firrtl.integer.mul %0, %1 : (!firrtl.integer, !firrtl.integer) ->
                                     !firrtl.integer

Traits: AlwaysSpeculatableImplTrait, Commutative, SameOperandsAndResultType

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhsinteger type
rhsinteger type

Results:

ResultDescription
resultinteger type

firrtl.integer.shr (::circt::firrtl::IntegerShrOp)

Shift an FIntegerType value right by an FIntegerType value

Syntax:

operation ::= `firrtl.integer.shr` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

The shift right operation result is the arbitrary precision signed integer arithmetic shift right of the lhs operand by the rhs operand. The rhs operand must be non-negative.

Example:

%2 = firrtl.integer.shr %0, %1 : (!firrtl.integer, !firrtl.integer) ->
                                     !firrtl.integer

Traits: AlwaysSpeculatableImplTrait, SameOperandsAndResultType

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhsinteger type
rhsinteger type

Results:

ResultDescription
resultinteger type

firrtl.invalidvalue (::circt::firrtl::InvalidValueOp)

InvalidValue primitive

Syntax:

operation ::= `firrtl.invalidvalue` attr-dict `:` qualified(type($result))

The InvalidValue operation returns an invalid value of a specified type:

  %result = firrtl.invalid : !firrtl.uint<1>

This corresponds to the FIRRTL invalidate operation without the implicit connect semantics. Each invalid op produces a unique invalid value. InvalidOp is not constant-like

Interfaces: HasCustomSSAName, MemoryEffectOpInterface (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{MemoryEffects::Allocate on ::mlir::SideEffects::DefaultResource}

Results:

ResultDescription
resulta base type

firrtl.istag (::circt::firrtl::IsTagOp)

Test the active variant of an enumeration

This operation is used to test the active variant of an enumeration. The tag tested for must be one of the possible variants of the input type. If the tag is the currently active variant the result will be 1, otherwise the result will be 0.

Example:

  %0 = firrtl.istag A %v : !firrtl.enum<A: UInt<0>, B: UInt<0>>

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
fieldIndex::mlir::IntegerAttr32-bit signless integer attribute

Operands:

OperandDescription
inputenum type

Results:

ResultDescription
result1-bit uint

firrtl.leq (::circt::firrtl::LEQPrimOp)

Syntax:

operation ::= `firrtl.leq` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Traits: AlwaysSpeculatableImplTrait, SameOperandsIntTypeKind

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhssint or uint type

Results:

ResultDescription
result1-bit uint

firrtl.int.ltl.and (::circt::firrtl::LTLAndIntrinsicOp)

FIRRTL variant of ltl.and

Syntax:

operation ::= `firrtl.int.ltl.and` operands attr-dict `:` functional-type(operands, results)

See ltl.and op in the LTL dialect. Traits: AlwaysSpeculatableImplTrait, Commutative

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhs1-bit uint
rhs1-bit uint

Results:

ResultDescription
result1-bit uint

firrtl.int.ltl.clock (::circt::firrtl::LTLClockIntrinsicOp)

FIRRTL variant of ltl.clock

Syntax:

operation ::= `firrtl.int.ltl.clock` $input `,` $clock attr-dict `:` functional-type(operands, results)

See ltl.clock op in the LTL dialect. Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
input1-bit uint
clockclock

Results:

ResultDescription
result1-bit uint

firrtl.int.ltl.concat (::circt::firrtl::LTLConcatIntrinsicOp)

FIRRTL variant of ltl.concat

Syntax:

operation ::= `firrtl.int.ltl.concat` operands attr-dict `:` functional-type(operands, results)

See ltl.concat op in the LTL dialect. Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhs1-bit uint
rhs1-bit uint

Results:

ResultDescription
result1-bit uint

firrtl.int.ltl.delay (::circt::firrtl::LTLDelayIntrinsicOp)

FIRRTL variant of ltl.delay

Syntax:

operation ::= `firrtl.int.ltl.delay` $input `,` $delay (`,` $length^)? attr-dict `:`
              functional-type(operands, results)

See ltl.delay op in the LTL dialect. Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
delay::mlir::IntegerAttr64-bit signless integer attribute
length::mlir::IntegerAttr64-bit signless integer attribute

Operands:

OperandDescription
input1-bit uint

Results:

ResultDescription
result1-bit uint

firrtl.int.ltl.disable (::circt::firrtl::LTLDisableIntrinsicOp)

FIRRTL variant of ltl.disable

Syntax:

operation ::= `firrtl.int.ltl.disable` operands attr-dict `:` functional-type(operands, results)

See ltl.disable op in the LTL dialect. Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhs1-bit uint
rhs1-bit uint

Results:

ResultDescription
result1-bit uint

firrtl.int.ltl.eventually (::circt::firrtl::LTLEventuallyIntrinsicOp)

FIRRTL variant of ltl.eventually

Syntax:

operation ::= `firrtl.int.ltl.eventually` operands attr-dict `:` functional-type(operands, results)

See ltl.eventually op in the LTL dialect. Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
input1-bit uint

Results:

ResultDescription
result1-bit uint

firrtl.int.ltl.implication (::circt::firrtl::LTLImplicationIntrinsicOp)

FIRRTL variant of ltl.implication

Syntax:

operation ::= `firrtl.int.ltl.implication` operands attr-dict `:` functional-type(operands, results)

See ltl.implication op in the LTL dialect. Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhs1-bit uint
rhs1-bit uint

Results:

ResultDescription
result1-bit uint

firrtl.int.ltl.not (::circt::firrtl::LTLNotIntrinsicOp)

FIRRTL variant of ltl.not

Syntax:

operation ::= `firrtl.int.ltl.not` operands attr-dict `:` functional-type(operands, results)

See ltl.not op in the LTL dialect. Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
input1-bit uint

Results:

ResultDescription
result1-bit uint

firrtl.int.ltl.or (::circt::firrtl::LTLOrIntrinsicOp)

FIRRTL variant of ltl.or

Syntax:

operation ::= `firrtl.int.ltl.or` operands attr-dict `:` functional-type(operands, results)

See ltl.or op in the LTL dialect. Traits: AlwaysSpeculatableImplTrait, Commutative

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhs1-bit uint
rhs1-bit uint

Results:

ResultDescription
result1-bit uint

firrtl.lt (::circt::firrtl::LTPrimOp)

Syntax:

operation ::= `firrtl.lt` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Traits: AlwaysSpeculatableImplTrait, SameOperandsIntTypeKind

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhssint or uint type

Results:

ResultDescription
result1-bit uint

firrtl.list.create (::circt::firrtl::ListCreateOp)

Produce a list value

Produces a value of list type containing the provided elements.

Example:

%3 = firrtl.list.create %0, %1, %2 : !firrtl.list<string>

Traits: AlwaysSpeculatableImplTrait, SameTypeOperands

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
elementsvariadic of property type

Results:

ResultDescription
resultlist type

firrtl.mul (::circt::firrtl::MulPrimOp)

Syntax:

operation ::= `firrtl.mul` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Traits: AlwaysSpeculatableImplTrait, Commutative, SameOperandsIntTypeKind

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhssint or uint type

Results:

ResultDescription
resultsint or uint type

firrtl.multibit_mux (::circt::firrtl::MultibitMuxOp)

Multibit multiplexer

The multibit mux expression dynamically selects operands. The index must be an expression with an unsigned integer type.

  %result = firrtl.multibit_mux %index,
            %v_{n-1}, ..., %v_2, %v_1, %v_0  : t1, t2

The order of operands is defined in the same way as hw dialect. For the example above, if %index is 0, then the value is %v_0.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
indexuint type
inputsvariadic of a base type

Results:

ResultDescription
resulta base type

firrtl.int.mux2cell (::circt::firrtl::Mux2CellIntrinsicOp)

An intrinsic lowered into 2-to-1 MUX cell in synthesis tools.

Syntax:

operation ::= `firrtl.int.mux2cell` `(` operands `)` attr-dict `:` functional-type(operands, $result)

This intrinsic exposes a low-level API to use 2-to-1 MUX cell in backend synthesis tool. At FIRRTL level, this operation participates the inference process in the same way as a normal mux operation.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
sel1-bit uint or uint with uninferred width
higha passive base type (contain no flips)
lowa passive base type (contain no flips)

Results:

ResultDescription
resulta passive base type (contain no flips)

firrtl.int.mux4cell (::circt::firrtl::Mux4CellIntrinsicOp)

An intrinsic lowered into 4-to-1 MUX cell in synthesis tools.

Syntax:

operation ::= `firrtl.int.mux4cell` `(` operands `)` attr-dict `:` functional-type(operands, $result)

This intrinsic exposes a low-level API to use 4-to-1 MUX cell in backend synthesis tool. At FIRRTL level, this operation participates the inference process as a sugar of mux operation chains.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
sel2-bit uint or uint with uninferred width
v3a passive base type (contain no flips)
v2a passive base type (contain no flips)
v1a passive base type (contain no flips)
v0a passive base type (contain no flips)

Results:

ResultDescription
resulta passive base type (contain no flips)

firrtl.mux (::circt::firrtl::MuxPrimOp)

Syntax:

operation ::= `firrtl.mux` `(` operands `)` attr-dict `:` functional-type(operands, $result)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
sel1-bit uint or uint with uninferred width
higha passive base type (contain no flips)
lowa passive base type (contain no flips)

Results:

ResultDescription
resulta passive base type (contain no flips)

firrtl.neq (::circt::firrtl::NEQPrimOp)

Syntax:

operation ::= `firrtl.neq` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Traits: AlwaysSpeculatableImplTrait, Commutative, SameOperandsIntTypeKind

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhssint or uint type

Results:

ResultDescription
result1-bit uint

firrtl.neg (::circt::firrtl::NegPrimOp)

Syntax:

operation ::= `firrtl.neg` $input attr-dict `:` functional-type($input, $result)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
inputsint or uint type

Results:

ResultDescription
resultsint type

firrtl.not (::circt::firrtl::NotPrimOp)

Syntax:

operation ::= `firrtl.not` $input attr-dict `:` functional-type($input, $result)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
inputsint or uint type

Results:

ResultDescription
resultuint type

firrtl.object.anyref_cast (::circt::firrtl::ObjectAnyRefCastOp)

Cast object reference to anyref.

Syntax:

operation ::= `firrtl.object.anyref_cast` $input attr-dict `:` type($input)

Cast any object reference to AnyRef type. This is needed for passing objects of a known class to sinks that accept any reference.

Example

  %0= firrtl.object.anyref_cast %object : !firrtl.class<@Foo()>

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
inputclass type

Results:

ResultDescription
resultany reference type

firrtl.object.subfield (::circt::firrtl::ObjectSubfieldOp)

Extract an element of an object

The object.subfield expression refers to a subelement of an object.

%field = firrtl.object.subfield %object[field] : !firrt.class<@Class(field: !firrtl.string)>

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
index::mlir::IntegerAttr32-bit signless integer attribute

Operands:

OperandDescription
inputclass type

Results:

ResultDescription
resultproperty type

firrtl.opensubfield (::circt::firrtl::OpenSubfieldOp)

Extract a subfield of another value

The subfield expression refers to a subelement of an expression with a bundle type.

  %result = firrtl.opensubfield %input[field-name] : !input-type

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
fieldIndex::mlir::IntegerAttr32-bit signless integer attribute

Operands:

OperandDescription
inputopen bundle type

Results:

ResultDescription
resultFIRRTLType

firrtl.opensubindex (::circt::firrtl::OpenSubindexOp)

Extract an element of a vector value

Syntax:

operation ::= `firrtl.opensubindex` $input `[` $index `]` attr-dict `:` qualified(type($input))

The subindex expression statically refers, by index, to a subelement of an expression with a vector type. The index must be a non-negative integer and cannot be equal to or exceed the length of the vector it indexes.

  %result = firrtl.opensubindex %input[index] : t1

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
index::mlir::IntegerAttr32-bit signless integer attribute

Operands:

OperandDescription
inputopen vector type

Results:

ResultDescription
resultFIRRTLType

firrtl.or (::circt::firrtl::OrPrimOp)

Syntax:

operation ::= `firrtl.or` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Traits: AlwaysSpeculatableImplTrait, Commutative, SameOperandsIntTypeKind

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhssint or uint type

Results:

ResultDescription
resultuint type

firrtl.orr (::circt::firrtl::OrRPrimOp)

Syntax:

operation ::= `firrtl.orr` $input attr-dict `:` functional-type($input, $result)

Horizontally reduce a value to one bit, using the ‘or’ operation to merge bits. orr(x) is equivalent to concat(x, 1b0) != 0. As such, it returns 0 for zero-bit-wide operands.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
inputsint or uint type

Results:

ResultDescription
result1-bit uint

firrtl.pad (::circt::firrtl::PadPrimOp)

Syntax:

operation ::= `firrtl.pad` $input `,` $amount attr-dict `:` functional-type($input, $result)

Pad the input out to an amount wide integer, sign extending or zero extending according to inputs type. If amount is less than the existing width of input, then input is unmodified.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
amount::mlir::IntegerAttr32-bit signless integer attribute

Operands:

OperandDescription
inputsint or uint type

Results:

ResultDescription
resultsint or uint type

firrtl.path (::circt::firrtl::PathOp)

Produce a path value

Syntax:

operation ::= `firrtl.path` $targetKind $target attr-dict

Produces a value which represents a path to the target in a design.

Example:

hw.hierpath @Path [@Foo::@bar, @Bar]
%wire = firrtl.wire {annotations = [ {class = "circt.tracker", id = distinct[0]<>, circt.nonlocal = @Path} ]} : !firrtl.uint<1>
%0 = firrtl.path reference distinct[0]<>

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
targetKind::circt::firrtl::TargetKindAttrobject model target kind
target::mlir::DistinctAttrdistinct attribute

Results:

ResultDescription
resultpath type

firrtl.ref.rwprobe (::circt::firrtl::RWProbeOp)

FIRRTL RWProbe

Syntax:

operation ::= `firrtl.ref.rwprobe` $target attr-dict `:` type($result)

Create a RWProbe for the target. Target must be local.

  %result = firrtl.ref.rwprobe @mod::@sym : firrtl.rwprobe<t>

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InnerRefUserOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
target::circt::hw::InnerRefAttrRefer to a name inside a module

Results:

ResultDescription
resultrwprobe type (with concrete resets only)

firrtl.ref.cast (::circt::firrtl::RefCastOp)

Cast between compatible reference types

Syntax:

operation ::= `firrtl.ref.cast` $input attr-dict `:` functional-type($input, $result)

Losslessly cast between compatible reference types. Source and destination must be recursively identical or destination has uninferred variants of the corresponding element in source.

  %result = firrtl.ref.cast %ref : (t1) -> t2

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
inputreference type

Results:

ResultDescription
resultreference type

firrtl.ref.resolve (::circt::firrtl::RefResolveOp)

FIRRTL Resolve a Reference

Syntax:

operation ::= `firrtl.ref.resolve` $ref attr-dict `:` qualified(type($ref))

Resolve a remote reference for reading a remote value. It takes a RefType input and returns the corresponding BaseType value. If an XMR is emitted for this reference, it will be at the location of this operation.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
refreference type

Results:

ResultDescription
resulta base type

firrtl.ref.send (::circt::firrtl::RefSendOp)

FIRRTL Send through Reference

Syntax:

operation ::= `firrtl.ref.send` $base attr-dict `:` qualified(type($base))

Endpoint of a remote reference. Send a value through a reference to be read from the firrtl.ref.resolve op. It takes a BaseType input and returns the corresponding RefType value.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
basea base type

Results:

ResultDescription
resultreference type

firrtl.ref.sub (::circt::firrtl::RefSubOp)

Extract an element of an aggregate RefType value

Syntax:

operation ::= `firrtl.ref.sub` $input `[` $index `]` attr-dict `:` qualified(type($input))

The refsub expression statically refers, by index, to a sub-element of an expression with a RefType. The index must be a non-negative integer and cannot be equal to or exceed the underlying vector size or number of elements in bundle.

  %result = firrtl.ref.sub %input[index] : t1

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
index::mlir::IntegerAttr32-bit signless integer attribute

Operands:

OperandDescription
inputreference type

Results:

ResultDescription
resultreference type

firrtl.rem (::circt::firrtl::RemPrimOp)

Syntax:

operation ::= `firrtl.rem` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Traits: AlwaysSpeculatableImplTrait, SameOperandsIntTypeKind

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhssint or uint type

Results:

ResultDescription
resultsint or uint type

firrtl.shl (::circt::firrtl::ShlPrimOp)

Syntax:

operation ::= `firrtl.shl` $input `,` $amount attr-dict `:` functional-type($input, $result)

The shl operation concatenates amount zero bits to the least significant end of input. amount must be non-negative.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
amount::mlir::IntegerAttr32-bit signless integer attribute

Operands:

OperandDescription
inputsint or uint type

Results:

ResultDescription
resultsint or uint type

firrtl.shr (::circt::firrtl::ShrPrimOp)

Syntax:

operation ::= `firrtl.shr` $input `,` $amount attr-dict `:` functional-type($input, $result)

The shr operation truncates least significant amount bits from input. If amount is greater than of equal to width(input), the value will be zero for unsigned types and the sign bit for signed types. amount must be non-negative.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
amount::mlir::IntegerAttr32-bit signless integer attribute

Operands:

OperandDescription
inputsint or uint type

Results:

ResultDescription
resultsint or uint type

firrtl.int.sizeof (::circt::firrtl::SizeOfIntrinsicOp)

Syntax:

operation ::= `firrtl.int.sizeof` $input attr-dict `:` functional-type($input, $result)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
inputa base type

Results:

ResultDescription
result32-bit uint

firrtl.specialconstant (::circt::firrtl::SpecialConstantOp)

Produce a constant Reset or Clock value

The constant operation produces a constant value of Reset, AsyncReset, or Clock type. The value can only be 0 or 1.

  %result = firrtl.specialconstant 1 : !firrtl.clock

Traits: AlwaysSpeculatableImplTrait, ConstantLike

Interfaces: ConditionallySpeculatable, HasCustomSSAName, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
value::mlir::BoolAttrbool attribute

Results:

ResultDescription
resultclock or reset type or async reset type

firrtl.string (::circt::firrtl::StringConstantOp)

Produce a constant string value

Syntax:

operation ::= `firrtl.string` $value attr-dict

Produces a constant value of string type.

Example:

%0 = firrtl.string "hello world"

Traits: AlwaysSpeculatableImplTrait, ConstantLike

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
value::mlir::StringAttrstring attribute

Results:

ResultDescription
resultstring type

firrtl.sub (::circt::firrtl::SubPrimOp)

Syntax:

operation ::= `firrtl.sub` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Traits: AlwaysSpeculatableImplTrait, SameOperandsIntTypeKind

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhssint or uint type

Results:

ResultDescription
resultsint or uint type

firrtl.subaccess (::circt::firrtl::SubaccessOp)

Extract a dynamic element of a vector value

Syntax:

operation ::= `firrtl.subaccess` $input `[` $index `]` attr-dict `:` qualified(type($input)) `,` qualified(type($index))

The subaccess expression dynamically refers to a subelement of a vector-typed expression using a calculated index. The index must be an expression with an unsigned integer type.

  %result = firrtl.subaccess %input[%idx] : t1, t2

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
inputvector type
indexuint type

Results:

ResultDescription
resulta base type

firrtl.subfield (::circt::firrtl::SubfieldOp)

Extract a subfield of another value

The subfield expression refers to a subelement of an expression with a bundle type.

  %result = firrtl.subfield %input[field-name] : !input-type

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
fieldIndex::mlir::IntegerAttr32-bit signless integer attribute

Operands:

OperandDescription
inputbundle type

Results:

ResultDescription
resulta base type

firrtl.subindex (::circt::firrtl::SubindexOp)

Extract an element of a vector value

Syntax:

operation ::= `firrtl.subindex` $input `[` $index `]` attr-dict `:` qualified(type($input))

The subindex expression statically refers, by index, to a subelement of an expression with a vector type. The index must be a non-negative integer and cannot be equal to or exceed the length of the vector it indexes.

  %result = firrtl.subindex %input[index] : t1

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
index::mlir::IntegerAttr32-bit signless integer attribute

Operands:

OperandDescription
inputvector type

Results:

ResultDescription
resulta base type

firrtl.subtag (::circt::firrtl::SubtagOp)

Extract an element of a enum value

The subtag expression refers to a subelement of a enum-typed expression.

  %result = firrtl.subtag %input[field-name] : !input-type

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
fieldIndex::mlir::IntegerAttr32-bit signless integer attribute

Operands:

OperandDescription
inputenum type

Results:

ResultDescription
resulta base type

firrtl.tagextract (::circt::firrtl::TagExtractOp)

Extract the tag from a value

Syntax:

operation ::= `firrtl.tagextract` $input attr-dict `:` qualified(type($input))

The tagextract expression returns the binary value of the current tag of an enum value.

  %result = firrtl.tagextract %input : !input-type

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
inputenum type

Results:

ResultDescription
resultuint type

firrtl.tail (::circt::firrtl::TailPrimOp)

Syntax:

operation ::= `firrtl.tail` $input `,` $amount attr-dict `:` functional-type($input, $result)

The tail operation truncates the amount most significant bits from input. amount must be non-negative and less than or equal to the bit width of e. The result is width(input)-amount bits wide.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
amount::mlir::IntegerAttr32-bit signless integer attribute

Operands:

OperandDescription
inputsint or uint type

Results:

ResultDescription
resultuint type

firrtl.resetCast (::circt::firrtl::UninferredResetCastOp)

Syntax:

operation ::= `firrtl.resetCast` $input attr-dict `:` functional-type($input, $result)

Cast between reset types. This is used to enable strictconnects early in the pipeline by isolating all uninferred reset connections to a single op.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
inputReset

Results:

ResultDescription
resultReset

firrtl.unresolved_path (::circt::firrtl::UnresolvedPathOp)

Produce a path value

Syntax:

operation ::= `firrtl.unresolved_path` $target attr-dict

Produces a value which represents a path to the target in a design.

Example:

0 = firrtl.unresolved_path "~Circuit|Module>w"

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
target::mlir::StringAttrstring attribute

Results:

ResultDescription
resultpath type

firrtl.vectorcreate (::circt::firrtl::VectorCreateOp)

Produce a vector value

Syntax:

operation ::= `firrtl.vectorcreate` $fields attr-dict `:` functional-type($fields, $result)

Create a vector from component values. This is equivalent in terms of flow to creating a node. The first operand indicates 0-th element of the result.

  %result = firrtl.vectorcreate %1, %2, %3 : !firrtl.vector<uint<8>, 3>

Operands:

OperandDescription
fieldsvariadic of a base type

Results:

ResultDescription
resultvector type

firrtl.verbatim.expr (::circt::firrtl::VerbatimExprOp)

Expression that expands to a value given SystemVerilog text

Syntax:

operation ::= `firrtl.verbatim.expr` $text (`(` $substitutions^ `)`)?
              `:` functional-type($substitutions, $result) attr-dict

This operation produces a typed value expressed by a string of SystemVerilog. This can be used to access macros and other values that are only sensible as Verilog text.

The text string is expected to have the highest precedence, so you should include parentheses in the string if it isn’t a single token. This is also assumed to not have side effects (use sv.verbatim if you need them).

firrtl.verbatim.expr allows operand substitutions with {{0}} syntax.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
text::mlir::StringAttrstring attribute
symbols::mlir::ArrayAttrname reference array attribute

Operands:

OperandDescription
substitutionsvariadic of any type

Results:

ResultDescription
resulta base type

firrtl.verbatim.wire (::circt::firrtl::VerbatimWireOp)

Expression with wire semantics that expands to a value given SystemVerilog text

Syntax:

operation ::= `firrtl.verbatim.wire` $text (`(` $substitutions^ `)`)?
              `:` functional-type($substitutions, $result) attr-dict

This operation produces a typed value with wire semantics, expressed by a string of SystemVerilog. This can be used to access macros and other values that are only sensible as Verilog text.

The text string is expected to have the highest precedence, so you should include parentheses in the string if it isn’t a single token. This is also assumed to not have side effects (use sv.verbatim if you need them).

firrtl.verbatim.wire allows operand substitutions with {{0}} syntax.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
text::mlir::StringAttrstring attribute
symbols::mlir::ArrayAttrname reference array attribute

Operands:

OperandDescription
substitutionsvariadic of any type

Results:

ResultDescription
resulta base type

firrtl.xmr.deref (::circt::firrtl::XMRDerefOp)

FIRRTL XMR operation, reading an XMR target.

Syntax:

operation ::= `firrtl.xmr.deref` $ref (`,` $verbatimSuffix^)? attr-dict `:` qualified(type($dest))

Attributes:

AttributeMLIR TypeDescription
ref::mlir::FlatSymbolRefAttrflat symbol reference attribute
verbatimSuffix::mlir::StringAttrstring attribute

Results:

ResultDescription
desta passive base type (contain no flips)

firrtl.xmr.ref (::circt::firrtl::XMRRefOp)

FIRRTL XMR operation, targetable by ref ops.

Syntax:

operation ::= `firrtl.xmr.ref` $ref (`,` $verbatimSuffix^)? attr-dict `:` qualified(type($dest))

Attributes:

AttributeMLIR TypeDescription
ref::mlir::FlatSymbolRefAttrflat symbol reference attribute
verbatimSuffix::mlir::StringAttrstring attribute

Results:

ResultDescription
destreference type

firrtl.xor (::circt::firrtl::XorPrimOp)

Syntax:

operation ::= `firrtl.xor` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Traits: AlwaysSpeculatableImplTrait, Commutative, SameOperandsIntTypeKind

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhssint or uint type

Results:

ResultDescription
resultuint type

firrtl.xorr (::circt::firrtl::XorRPrimOp)

Syntax:

operation ::= `firrtl.xorr` $input attr-dict `:` functional-type($input, $result)

Horizontally reduce a value to one bit, using the ‘xor’ operation to merge bits. xorr(x) is equivalent to popcount(concat(x, 1b0)) & 1. As such, it returns 0 for zero-bit-wide operands.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
inputsint or uint type

Results:

ResultDescription
result1-bit uint

Type Definitions

AnalogType

Analog signal

Parameters:

ParameterC++ typeDescription
widthOrSentinelint32_t
isConstbool

AnyRefType

A reference to an instance of any class.

A reference of type AnyRef can be used in ports, property assignments, and any other Property “plumbing” ops. But it is opaque, and references to objects of AnyRef type cannot be “dereferenced”. There is no information about the referred to object’s fields, so subfield access, etc. is illegal.

AsyncResetType

AsyncReset signal

Parameters:

ParameterC++ typeDescription
isConstbool

BaseTypeAliasType

type alias for firrtl base types

Parameters:

ParameterC++ typeDescription
nameStringAttr
innerType::circt::firrtl::FIRRTLBaseTypeAn inner type

BoolType

A boolean property. Not representable in hardware.

BundleType

an aggregate of named elements. This is effectively a struct.

Parameters:

ParameterC++ typeDescription
elementsArrayRef<BundleElement>
isConstbool

ClassType

An instance of a class.

Example:
```mlir
!firrtl.class<@Module(in p0: !firrtl.uint<8>, out p1: !firrtl.uint<8>)>
```

Parameters:

ParameterC++ typeDescription
nameFlatSymbolRefAttr
elements::llvm::ArrayRef<ClassElement>

ClockType

Clock signal

Parameters:

ParameterC++ typeDescription
isConstbool

DoubleType

A double property. Not representable in hardware.

FEnumType

a sum type of named elements.

Parameters:

ParameterC++ typeDescription
elementsArrayRef<EnumElement>
isConstbool

FVectorType

a fixed size collection of elements, like an array.

Parameters:

ParameterC++ typeDescription
elementType::circt::firrtl::FIRRTLBaseTypeType of vector elements
numElementssize_t
isConstbool

FIntegerType

An unlimited length signed integer type. Not representable in hardware.

ListType

A typed property list of any length. Not representable in hardware.

Parameters:

ParameterC++ typeDescription
elementTypecirct::firrtl::PropertyTypeelement type

OpenBundleType

an aggregate of named elements. This is effectively a struct.

Parameters:

ParameterC++ typeDescription
elementsArrayRef<BundleElement>
isConstbool

OpenVectorType

a fixed size collection of elements, like an array.

Parameters:

ParameterC++ typeDescription
elementType::circt::firrtl::FIRRTLTypeType of vector elements
numElementssize_t
isConstbool

PathType

A path to a hardware entity. Not representable in hardware.

RefType

A reference to a signal elsewhere.

A reference type, such as firrtl.probe<uint<1>> or firrtl.rwprobe<uint<2>>.

Used for remote reads and writes of the wrapped base type.

Parameterized over the referenced base type, with flips removed.

Not a base type.

Values of this type are used to capture dataflow paths, and do not represent a circuit element or entity.

Generally read-only (probe), optionally forceable (rwprobe).

Parameters:

ParameterC++ typeDescription
type::circt::firrtl::FIRRTLBaseTypeType of reference target
forceablebool
layer::mlir::SymbolRefAttr

ResetType

Reset Signal

Parameters:

ParameterC++ typeDescription
isConstbool

SIntType

A signed integer type, whose width may not be known.

Parameters:

ParameterC++ typeDescription
widthOrSentinelint32_t
isConstbool

StringType

An unlimited length string type. Not representable in hardware.

UIntType

An unsigned integer type, whose width may not be known.

Parameters:

ParameterC++ typeDescription
widthOrSentinelint32_t
isConstbool

Attribute Definitions

AugmentedBooleanTypeAttr

GrandCentral AugmentedBooleanType

Syntax:

#firrtl.augmentedBoolean<
  DictionaryAttr   # underlying
>

Used in the GrandCentralPass.

Parameters:

ParameterC++ typeDescription
underlyingDictionaryAttr

AugmentedBundleTypeAttr

GrandCentral AugmentedBundleType

Syntax:

#firrtl.augmentedBundle<
  DictionaryAttr   # underlying
>

Used in the GrandCentralPass.

Parameters:

ParameterC++ typeDescription
underlyingDictionaryAttr

AugmentedDeletedTypeAttr

GrandCentral AugmentedDeletedType

Syntax:

#firrtl.augmentedDeleted<
  DictionaryAttr   # underlying
>

Used in the GrandCentralPass.

Parameters:

ParameterC++ typeDescription
underlyingDictionaryAttr

AugmentedDoubleTypeAttr

GrandCentral AugmentedDoubleType

Syntax:

#firrtl.augmentedDouble<
  DictionaryAttr   # underlying
>

Used in the GrandCentralPass.

Parameters:

ParameterC++ typeDescription
underlyingDictionaryAttr

AugmentedGroundTypeAttr

GrandCentral AugmentedGroundType

Syntax:

#firrtl.augmentedGround<
  DictionaryAttr   # underlying
>

Used in the GrandCentralPass.

Parameters:

ParameterC++ typeDescription
underlyingDictionaryAttr

AugmentedIntegerTypeAttr

GrandCentral AugmentedIntegerType

Syntax:

#firrtl.augmentedInteger<
  DictionaryAttr   # underlying
>

Used in the GrandCentralPass.

Parameters:

ParameterC++ typeDescription
underlyingDictionaryAttr

AugmentedLiteralTypeAttr

GrandCentral AugmentedLiteralType

Syntax:

#firrtl.augmentedLiteral<
  DictionaryAttr   # underlying
>

Used in the GrandCentralPass.

Parameters:

ParameterC++ typeDescription
underlyingDictionaryAttr

AugmentedStringTypeAttr

GrandCentral AugmentedStringType

Syntax:

#firrtl.augmentedString<
  DictionaryAttr   # underlying
>

Used in the GrandCentralPass.

Parameters:

ParameterC++ typeDescription
underlyingDictionaryAttr

AugmentedVectorTypeAttr

GrandCentral AugmentedVectorType

Syntax:

#firrtl.augmentedVector<
  DictionaryAttr   # underlying
>

Used in the GrandCentralPass.

Parameters:

ParameterC++ typeDescription
underlyingDictionaryAttr

InternalPathAttr

Internal path for ref-type ports

Syntax:

#firrtl.internalpath<
  ::mlir::StringAttr   # path
>

Parameters:

ParameterC++ typeDescription
path::mlir::StringAttr

MemoryInitAttr

Information about the initial state of a memory

Syntax:

#firrtl.meminit<
  ::mlir::StringAttr,   # filename
  bool,   # isBinary
  bool   # isInline
>

This attribute captures information about the external initialization of a memory. This is the FIRRTL Dialect representation of both “firrtl.annotations.LoadMemoryFromFile” and “firrtl.annotations.MemoryFileInlineAnnotation”.

Parameters:

ParameterC++ typeDescription
filename::mlir::StringAttr
isBinarybool
isInlinebool

ParamDeclAttr

Module or instance parameter definition

An attribute describing a module parameter, or instance parameter specification.

Parameters:

ParameterC++ typeDescription
name::mlir::StringAttr
type::mlir::Type
value::mlir::Attribute

ClassLike (ClassLike)

Provide common class information.

Methods:

getInstanceType

ClassType getInstanceType();

Get the type for instances of this class NOTE: This method must be implemented by the user.

verifyType

LogicalResult verifyType(::circt::firrtl::ClassType type, ::llvm::function_ref<::mlir::InFlightDiagnostic()> emitError);

Verify that the given type agrees with this class NOTE: This method must be implemented by the user.

FConnectLike (FConnectLike)

Provide common connection information.

Methods:

getDest

Value getDest();

Return a destination of connection. NOTE: This method must be implemented by the user.

getSrc

Value getSrc();

Return a source of connection. NOTE: This method must be implemented by the user.

getConnectBehaviorKind

static ConnectBehaviorKind getConnectBehaviorKind();

Return connection behavior kind. NOTE: This method must be implemented by the user.

hasStaticSingleConnectBehavior

static bool hasStaticSingleConnectBehavior();

Returns true if ConnectBehavior is StaticSingleConnect.

hasLastConnectBehavior

static bool hasLastConnectBehavior();

Returns true if ConnectBehavior is LastConnect.

FInstanceLike (FInstanceLike)

Provide common instance information.

Methods:

getReferencedModuleName

::llvm::StringRef getReferencedModuleName();

Get the name of the instantiated module NOTE: This method must be implemented by the user.

getReferencedModuleNameAttr

::mlir::StringAttr getReferencedModuleNameAttr();

Get the name of the instantiated module NOTE: This method must be implemented by the user.

getReferencedOperation

::mlir::Operation *getReferencedOperation(const SymbolTable&symtbl);

Get the referenced module via a symbol table. NOTE: This method must be implemented by the user.

FModuleLike (FModuleLike)

Provide common module information.

Methods:

getParameters

ArrayAttr getParameters();

Get the parameters

getConventionAttr

ConventionAttr getConventionAttr();

Get the module’s instantiation convention NOTE: This method must be implemented by the user.

getConvention

Convention getConvention();

Get the module’s instantiation convention NOTE: This method must be implemented by the user.

getLayersAttr

ArrayAttr getLayersAttr();

Get the module’s enabled layers NOTE: This method must be implemented by the user.

getLayers

ArrayRef<Attribute> getLayers();

Get the module’s enabled layers. NOTE: This method must be implemented by the user.

getPortDirectionsAttr

mlir::DenseBoolArrayAttr getPortDirectionsAttr();

Get the port directions attribute NOTE: This method must be implemented by the user.

getPortDirections

ArrayRef<bool> getPortDirections();

Get the port directions NOTE: This method must be implemented by the user.

getPortDirection

Direction getPortDirection(size_t portIndex);

Get a port direction NOTE: This method must be implemented by the user.

getPortNamesAttr

ArrayAttr getPortNamesAttr();

Get the port names attribute NOTE: This method must be implemented by the user.

getPortNames

ArrayRef<Attribute> getPortNames();

Get the port names NOTE: This method must be implemented by the user.

getPortNameAttr

StringAttr getPortNameAttr(size_t portIndex);

Get a port name NOTE: This method must be implemented by the user.

getPortName

StringRef getPortName(size_t portIndex);

Get a port name NOTE: This method must be implemented by the user.

getPortTypesAttr

ArrayAttr getPortTypesAttr();

Get the port types attribute NOTE: This method must be implemented by the user.

getPortTypes

ArrayRef<Attribute> getPortTypes();

Get the port types NOTE: This method must be implemented by the user.

getPortTypeAttr

TypeAttr getPortTypeAttr(size_t portIndex);

Get a port type NOTE: This method must be implemented by the user.

getPortType

Type getPortType(size_t portIndex);

Get a port type NOTE: This method must be implemented by the user.

getPortAnnotationsAttr

ArrayAttr getPortAnnotationsAttr();

Get the port annotations attribute NOTE: This method must be implemented by the user.

getPortAnnotations

ArrayRef<Attribute> getPortAnnotations();

Get the port annotations attribute NOTE: This method must be implemented by the user.

getAnnotationsAttrForPort

ArrayAttr getAnnotationsAttrForPort(size_t portIndex);

Get a port’s annotations attribute NOTE: This method must be implemented by the user.

getAnnotationsForPort

ArrayRef<Attribute> getAnnotationsForPort(size_t portIndex);

Get a port’s annotations NOTE: This method must be implemented by the user.

getPortSymbolsAttr

ArrayAttr getPortSymbolsAttr();

Get the port symbols attribute NOTE: This method must be implemented by the user.

getPortSymbols

ArrayRef<Attribute> getPortSymbols();

Get the port symbols NOTE: This method must be implemented by the user.

hasPortSymbolAttr

bool hasPortSymbolAttr(size_t portIndex);

Check if port has symbol attribute NOTE: This method must be implemented by the user.

getPortSymbolAttr

circt::hw::InnerSymAttr getPortSymbolAttr(size_t portIndex);

Get the port symbol attribute NOTE: This method must be implemented by the user.

setPortSymbols

void setPortSymbols(ArrayRef<Attribute> symbols);

Set the symbols of all ports and their fields NOTE: This method must be implemented by the user.

setPortSymbolAttr

void setPortSymbolAttr(size_t portIndex, StringAttr symbol);

Set a port’s top-level symbol to the specified string, dropping any symbols on its fields NOTE: This method must be implemented by the user.

setPortSymbolsAttr

void setPortSymbolsAttr(size_t portIndex, circt::hw::InnerSymAttr symbol);

Set the symbols for a port including its fields NOTE: This method must be implemented by the user.

setPortSymbol

void setPortSymbol(size_t portIndex, StringRef symbol);

Set a port’s top-level symbol to the specified string, dropping any symbols on its fields NOTE: This method must be implemented by the user.

getPortLocationsAttr

ArrayAttr getPortLocationsAttr();

Get the port locations attribute NOTE: This method must be implemented by the user.

getPortLocations

ArrayRef<Attribute> getPortLocations();

Get the port locations attribute NOTE: This method must be implemented by the user.

getPortLocationAttr

LocationAttr getPortLocationAttr(size_t portIndex);

Get a port’s location attribute NOTE: This method must be implemented by the user.

getPortLocation

Location getPortLocation(size_t portIndex);

Get a port’s location NOTE: This method must be implemented by the user.

getPorts

SmallVector<PortInfo> getPorts();

Get information about all ports NOTE: This method must be implemented by the user.

insertPorts

void insertPorts(ArrayRef<std::pair<unsigned, PortInfo>> ports);

Inserts the given ports at the corresponding indices NOTE: This method must be implemented by the user.

erasePorts

void erasePorts(const llvm::BitVector&portIndices);

Erases the ports that have their corresponding bit set in portIndices NOTE: This method must be implemented by the user.

FNamableOp (FNamableOp)

The interface provides common methods for namable operations related to name preservation semantics.

Methods:

hasDroppableName

bool hasDroppableName();

Return true if the name is droppable. NOTE: This method must be implemented by the user.

dropName

void dropName();

Completely drop a name. NOTE: This method must be implemented by the user.

setNameKindAttr

void setNameKindAttr(firrtl::NameKindEnumAttr nameKind);

Set a namekind. NOTE: This method must be implemented by the user.

getNameAttr

mlir::StringAttr getNameAttr();

Return the name. NOTE: This method must be implemented by the user.

getName

llvm::StringRef getName();

Return the name. NOTE: This method must be implemented by the user.

Forceable (Forceable)

Interaction with declarations of forceable hardware components, and managing references to them.

Methods:

isForceable

bool isForceable();

Return true if the operation is forceable. NOTE: This method must be implemented by the user.

getData

mlir::TypedValue<FIRRTLBaseType> getData();

Return data value that will be targeted. NOTE: This method must be implemented by the user.

getDataRaw

Value getDataRaw();

Return raw data value that will be targeted. NOTE: This method must be implemented by the user.

getDataType

FIRRTLBaseType getDataType();

Return data type that will be referenced. NOTE: This method must be implemented by the user.

getDataRef

mlir::TypedValue<RefType> getDataRef();

Return reference result, or null if not active. NOTE: This method must be implemented by the user.

'firrtl' Dialect Docs