CIRCT

Circuit IR Compilers and Tools

'firrtl' Dialect

Types and operations for firrtl dialect This dialect defines the firrtl dialect, which is used to lower from Chisel code to Verilog. For more information, see the FIRRTL GitHub page.

Operation definition

firrtl.add (::circt::firrtl::AddPrimOp)

Syntax:

operation ::= `firrtl.add` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Traits: Commutative, SameOperandsIntTypeKind

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhssint or uint type

Results:

ResultDescription
resultsint or uint type

firrtl.and (::circt::firrtl::AndPrimOp)

Syntax:

operation ::= `firrtl.and` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Traits: Commutative, SameOperandsIntTypeKind

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhssint or uint type

Results:

ResultDescription
resultuint type

firrtl.andr (::circt::firrtl::AndRPrimOp)

Syntax:

operation ::= `firrtl.andr` $input attr-dict `:` functional-type($input, $result)

Horizontally reduce a value to one bit, using the ‘and’ operation to merge bits. andr(x) is equivalent to concat(x, 1b1) == ~0. As such, it returns 1 for zero-bit-wide operands.

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
inputsint or uint type

Results:

ResultDescription
resultUInt<1> or UInt

firrtl.asAsyncReset (::circt::firrtl::AsAsyncResetPrimOp)

Syntax:

operation ::= `firrtl.asAsyncReset` $input attr-dict `:` functional-type($input, $result)

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
input1-bit uint/sint/analog, reset, asyncreset, or clock

Results:

ResultDescription
resultAsyncReset

firrtl.asClock (::circt::firrtl::AsClockPrimOp)

Syntax:

operation ::= `firrtl.asClock` $input attr-dict `:` functional-type($input, $result)

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
input1-bit uint/sint/analog, reset, asyncreset, or clock

Results:

ResultDescription
resultclock

firrtl.asSInt (::circt::firrtl::AsSIntPrimOp)

Syntax:

operation ::= `firrtl.asSInt` $input attr-dict `:` functional-type($input, $result)

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
inputa base type

Results:

ResultDescription
resultsint type

firrtl.asUInt (::circt::firrtl::AsUIntPrimOp)

Syntax:

operation ::= `firrtl.asUInt` $input attr-dict `:` functional-type($input, $result)

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
inputa base type

Results:

ResultDescription
resultuint type

firrtl.assert (::circt::firrtl::AssertOp)

Assert Verification Statement

Syntax:

operation ::= `firrtl.assert` $clock `,` $predicate `,` $enable `,`
              $message (`(` $substitutions^ `)` `:` qualified(type($substitutions)))?
              custom<VerifAttrs>(attr-dict)

Attributes:

AttributeMLIR TypeDescription
message::mlir::StringAttrstring attribute
name::mlir::StringAttrstring attribute
isConcurrent::mlir::BoolAttrbool attribute
eventControl::EventControlAttredge control trigger

Operands:

OperandDescription
clockclock
predicateUInt<1> or UInt
enableUInt<1> or UInt
substitutionsany type

firrtl.assume (::circt::firrtl::AssumeOp)

Assume Verification Statement

Syntax:

operation ::= `firrtl.assume` $clock `,` $predicate `,` $enable `,`
              $message (`(` $substitutions^ `)` `:` qualified(type($substitutions)))?
              custom<VerifAttrs>(attr-dict)

Attributes:

AttributeMLIR TypeDescription
message::mlir::StringAttrstring attribute
name::mlir::StringAttrstring attribute
isConcurrent::mlir::BoolAttrbool attribute
eventControl::EventControlAttredge control trigger

Operands:

OperandDescription
clockclock
predicateUInt<1> or UInt
enableUInt<1> or UInt
substitutionsany type

firrtl.attach (::circt::firrtl::AttachOp)

Analog Attach Statement

Syntax:

operation ::= `firrtl.attach` $attached attr-dict `:` qualified(type($attached))

Operands:

OperandDescription
attachedanalog type

firrtl.bitcast (::circt::firrtl::BitCastOp)

Reinterpret one value to another value of the same size and
potentially different type. This op is lowered to hw::BitCastOp.

Syntax:

operation ::= `firrtl.bitcast` $input attr-dict `:` functional-type($input, $result)

Interfaces: NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
inputa base type

Results:

ResultDescription
resulta base type

firrtl.bits (::circt::firrtl::BitsPrimOp)

Syntax:

operation ::= `firrtl.bits` $input $hi `to` $lo attr-dict `:` functional-type($input, $result)

The bits operation extracts the bits between hi (inclusive) and lo (inclusive) from input. hi must be greater than or equal to lo. Both hi and lo must be non-negative and less than the bit width of input. The result is hi - lo + 1 bits wide.

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
hi::mlir::IntegerAttr32-bit signless integer attribute
lo::mlir::IntegerAttr32-bit signless integer attribute

Operands:

OperandDescription
inputsint or uint type

Results:

ResultDescription
resultuint type

firrtl.cat (::circt::firrtl::CatPrimOp)

Syntax:

operation ::= `firrtl.cat` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Traits: SameOperandsIntTypeKind

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhssint or uint type

Results:

ResultDescription
resultuint type

firrtl.circuit (::circt::firrtl::CircuitOp)

FIRRTL Circuit

Syntax:

operation ::= `firrtl.circuit` $name custom<CircuitOpAttrs>(attr-dict) $body

The “firrtl.circuit” operation represents an overall Verilog circuit, containing a list of modules.

Traits: InnerRefNamespace, IsolatedFromAbove, NoRegionArguments, NoTerminator, SingleBlock, SymbolTable

Attributes:

AttributeMLIR TypeDescription
name::mlir::StringAttrstring attribute
annotations::mlir::ArrayAttrAnnotation array attribute

firrtl.connect (::circt::firrtl::ConnectOp)

Connect two signals

Syntax:

operation ::= `firrtl.connect` $dest `,` $src  attr-dict `:` qualified(type($dest)) `,` qualified(type($src))

Connect Operation:

  firrtl.connect %dest, %src : t1, t2

Interfaces: FConnectLike

Operands:

OperandDescription
desta connectable type (base type)
srca connectable type (base type)

firrtl.constant (::circt::firrtl::ConstantOp)

Produce a constant value

The constant operation produces a constant value of SInt or UInt type, it never produces a zero bit wide result.

  %result = firrtl.constant 42 : t1

Traits: ConstantLike, FirstAttrDerivedResultType

Interfaces: HasCustomSSAName, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
value::mlir::IntegerAttrarbitrary integer attribute with sign

Results:

ResultDescription
resultsint or uint type

firrtl.cover (::circt::firrtl::CoverOp)

Cover Verification Statement

Syntax:

operation ::= `firrtl.cover` $clock `,` $predicate `,` $enable `,`
              $message (`(` $substitutions^ `)` `:` qualified(type($substitutions)))?
              custom<VerifAttrs>(attr-dict)

Attributes:

AttributeMLIR TypeDescription
message::mlir::StringAttrstring attribute
name::mlir::StringAttrstring attribute
isConcurrent::mlir::BoolAttrbool attribute
eventControl::EventControlAttredge control trigger

Operands:

OperandDescription
clockclock
predicateUInt<1> or UInt
enableUInt<1> or UInt
substitutionsany type

firrtl.cvt (::circt::firrtl::CvtPrimOp)

Syntax:

operation ::= `firrtl.cvt` $input attr-dict `:` functional-type($input, $result)

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
inputsint or uint type

Results:

ResultDescription
resultsint type

firrtl.dshl (::circt::firrtl::DShlPrimOp)

Syntax:

operation ::= `firrtl.dshl` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

A dynamic shift left operation. The width of $result is expanded to width($lhs) + 1 << width($rhs) - 1.

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhsuint type

Results:

ResultDescription
resultsint or uint type

firrtl.dshlw (::circt::firrtl::DShlwPrimOp)

Syntax:

operation ::= `firrtl.dshlw` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

A dynamic shift left operation same as ‘dshl’ but with different width rule. The width of $result is equal to $lhs.

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhsuint type

Results:

ResultDescription
resultsint or uint type

firrtl.dshr (::circt::firrtl::DShrPrimOp)

Syntax:

operation ::= `firrtl.dshr` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhsuint type

Results:

ResultDescription
resultsint or uint type

firrtl.div (::circt::firrtl::DivPrimOp)

Syntax:

operation ::= `firrtl.div` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Divides the first argument (the numerator) by the second argument (the denominator) truncating the result (rounding towards zero).

If the denominator is zero, the result is undefined.

The compiler may optimize this undefined behavior in any way it wants. Notably div(a, a) will be optimized to 1. This may cause erroneous formal equivalence mismatches between unoptimized and optimized FIRRTL dialects that are separately converted to Verilog.

Traits: SameOperandsIntTypeKind

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhssint or uint type

Results:

ResultDescription
resultsint or uint type

firrtl.eq (::circt::firrtl::EQPrimOp)

Syntax:

operation ::= `firrtl.eq` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Traits: Commutative, SameOperandsIntTypeKind

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhssint or uint type

Results:

ResultDescription
resultUInt<1> or UInt

firrtl.extmodule (::circt::firrtl::FExtModuleOp)

FIRRTL extmodule

The “firrtl.extmodule” operation represents an external reference to a Verilog module, including a given name and a list of ports.

Traits: HasParent, InnerSymbolTable, IsolatedFromAbove

Interfaces: FModuleLike, HWModuleLike, OpAsmOpInterface, Symbol

Attributes:

AttributeMLIR TypeDescription
defname::mlir::StringAttrstring attribute
parameters::mlir::ArrayAttrparameter array attribute
annotations::mlir::ArrayAttrAnnotation array attribute

firrtl.memmodule (::circt::firrtl::FMemModuleOp)

FIRRTL Generated Module

The “firrtl.memmodule” operation represents an external reference to a memory module. See the “firrtl.mem” op for a deeper explantation of the parameters.

A “firrtl.mem” operation is typically lowered to this operation when they are not directly lowered to registers by the compiler.

Traits: HasParent, InnerSymbolTable, IsolatedFromAbove

Interfaces: FModuleLike, HWModuleLike, OpAsmOpInterface, Symbol

Attributes:

AttributeMLIR TypeDescription
numReadPorts::mlir::IntegerAttr32-bit unsigned integer attribute
numWritePorts::mlir::IntegerAttr32-bit unsigned integer attribute
numReadWritePorts::mlir::IntegerAttr32-bit unsigned integer attribute
dataWidth::mlir::IntegerAttr32-bit unsigned integer attribute
maskBits::mlir::IntegerAttr32-bit unsigned integer attribute
readLatency::mlir::IntegerAttr32-bit unsigned integer attribute
writeLatency::mlir::IntegerAttr32-bit unsigned integer attribute
depth::mlir::IntegerAttr64-bit unsigned integer attribute
extraPorts::mlir::ArrayAttrarray attribute
annotations::mlir::ArrayAttrAnnotation array attribute

firrtl.module (::circt::firrtl::FModuleOp)

FIRRTL Module

The “firrtl.module” operation represents a Verilog module, including a given name, a list of ports, and a body that represents the connections within the module.

Traits: HasParent, InnerSymbolTable, IsolatedFromAbove, NoTerminator, SingleBlock

Interfaces: FModuleLike, HWModuleLike, OpAsmOpInterface, Symbol

Attributes:

AttributeMLIR TypeDescription
annotations::mlir::ArrayAttrAnnotation array attribute

firrtl.force (::circt::firrtl::ForceOp)

Force procedural statement

Syntax:

operation ::= `firrtl.force` $dest `,` $src attr-dict `:` qualified(type($dest)) `,` qualified(type($src))

Maps to the corresponding sv.force operation. Traits: SameTypeOperands

Operands:

OperandDescription
desta base type
srca base type

firrtl.geq (::circt::firrtl::GEQPrimOp)

Syntax:

operation ::= `firrtl.geq` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Traits: SameOperandsIntTypeKind

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhssint or uint type

Results:

ResultDescription
resultUInt<1> or UInt

firrtl.gt (::circt::firrtl::GTPrimOp)

Syntax:

operation ::= `firrtl.gt` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Traits: SameOperandsIntTypeKind

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhssint or uint type

Results:

ResultDescription
resultUInt<1> or UInt

firrtl.hwStructCast (::circt::firrtl::HWStructCastOp)

Syntax:

operation ::= `firrtl.hwStructCast` $input attr-dict `:` functional-type($input, $result)

Interfaces: NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
inputany type

Results:

ResultDescription
resultany type

firrtl.head (::circt::firrtl::HeadPrimOp)

Syntax:

operation ::= `firrtl.head` $input `,` $amount attr-dict `:` functional-type($input, $result)

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
amount::mlir::IntegerAttr32-bit signless integer attribute

Operands:

OperandDescription
inputsint or uint type

Results:

ResultDescription
resultuint type

firrtl.hierpath (::circt::firrtl::HierPathOp)

Hierarchical path specification

The “firrtl.hierpath” operation represents a path through the hierarchy. This is used to specify namable things for use in other operations, for example in verbatim substitution. Non-local annotations also use these.

Traits: HasParent, IsolatedFromAbove

Interfaces: InnerRefUserOpInterface, Symbol

Attributes:

AttributeMLIR TypeDescription
sym_name::mlir::StringAttrstring attribute
namepath::mlir::ArrayAttrname reference array attribute

firrtl.instance (::circt::firrtl::InstanceOp)

Instantiate an instance of a module

This represents an instance of a module. The results are the modules inputs and outputs. The inputs have flip type, the outputs do not.

Examples:

%0 = firrtl.instance foo @Foo(in io: !firrtl.uint)

Traits: HasParent<firrtl::FModuleOp, firrtl::WhenOp>

Interfaces: FNamableOp, HWInstanceLike, HasCustomSSAName, InnerSymbol, SymbolUserOpInterface

Attributes:

AttributeMLIR TypeDescription
moduleName::mlir::FlatSymbolRefAttrflat symbol reference attribute
name::mlir::StringAttrstring attribute
nameKind::circt::firrtl::NameKindEnumAttrname kind
portDirections::mlir::IntegerAttrarbitrary integer attribute
portNames::mlir::ArrayAttrstring array attribute
annotations::mlir::ArrayAttrAnnotation array attribute
portAnnotations::mlir::ArrayAttrPort annotations attribute
lowerToBind::mlir::UnitAttrunit attribute
inner_sym::circt::firrtl::InnerSymAttrInner symbol definition

Results:

ResultDescription
resultsFIRRTLType

firrtl.invalidvalue (::circt::firrtl::InvalidValueOp)

InvalidValue primitive

Syntax:

operation ::= `firrtl.invalidvalue` attr-dict `:` qualified(type($result))

The InvalidValue operation returns an invalid value of a specified type:

  %result = firrtl.invalid : !firrtl.uint<1>

This corresponds to the FIRRTL invalidate operation without the implicit connect semantics.

Traits: ConstantLike

Interfaces: HasCustomSSAName, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Results:

ResultDescription
resulta base type

firrtl.verif_isX (::circt::firrtl::IsXVerifOp)

Test for ‘x

Syntax:

operation ::= `firrtl.verif_isX` $arg attr-dict `:` qualified(type($arg))

The verif.isX expression checks that the operand is not a verilog literal ‘x. Firrtl doesn’t have a notion of ‘x per-se, but x can come in to the system from external modules and from SV constructs. Verification constructs need to explicitly test for ‘x.

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
arga base type

Results:

ResultDescription
resultUInt<1> or UInt

firrtl.leq (::circt::firrtl::LEQPrimOp)

Syntax:

operation ::= `firrtl.leq` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Traits: SameOperandsIntTypeKind

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhssint or uint type

Results:

ResultDescription
resultUInt<1> or UInt

firrtl.lt (::circt::firrtl::LTPrimOp)

Syntax:

operation ::= `firrtl.lt` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Traits: SameOperandsIntTypeKind

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhssint or uint type

Results:

ResultDescription
resultUInt<1> or UInt

firrtl.mem (::circt::firrtl::MemOp)

Define a new mem

Syntax:

operation ::= `firrtl.mem` (`sym` $inner_sym^)? custom<NameKind>($nameKind)
              $ruw custom<MemOp>(attr-dict) `:` qualified(type($results))

Interfaces: FNamableOp, HasCustomSSAName, InnerSymbol

Attributes:

AttributeMLIR TypeDescription
readLatency::mlir::IntegerAttr32-bit signless integer attribute whose minimum value is 0
writeLatency::mlir::IntegerAttr32-bit signless integer attribute whose minimum value is 1
depth::mlir::IntegerAttr64-bit signless integer attribute whose minimum value is 1
ruw::RUWAttrAttrRead Under Write Enum
portNames::mlir::ArrayAttrstring array attribute
name::mlir::StringAttrstring attribute
nameKind::circt::firrtl::NameKindEnumAttrname kind
annotations::mlir::ArrayAttrAnnotation array attribute
portAnnotations::mlir::ArrayAttrPort annotations attribute
inner_sym::circt::firrtl::InnerSymAttrInner symbol definition
groupID::mlir::IntegerAttr32-bit unsigned integer attribute

Results:

ResultDescription
resultsa base type

firrtl.mul (::circt::firrtl::MulPrimOp)

Syntax:

operation ::= `firrtl.mul` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Traits: Commutative, SameOperandsIntTypeKind

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhssint or uint type

Results:

ResultDescription
resultsint or uint type

firrtl.multibit_mux (::circt::firrtl::MultibitMuxOp)

Multibit multiplexer

The multibit mux expression dynamically selects operands. The index must be an expression with an unsigned integer type.

  %result = firrtl.multibit_mux %index,
            %v_{n-1}, ..., %v_2, %v_1, %v_0  : t1, t2

The order of operands is defined in the same way as hw dialect. For the example above, if %index is 0, then the value is %v_0.

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
indexa base type
inputsa base type

Results:

ResultDescription
resulta base type

firrtl.mux (::circt::firrtl::MuxPrimOp)

Syntax:

operation ::= `firrtl.mux` `(` operands `)` attr-dict `:` functional-type(operands, $result)

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
selUInt<1> or UInt
higha passive base type (contain no flips)
lowa passive base type (contain no flips)

Results:

ResultDescription
resulta passive base type (contain no flips)

firrtl.neq (::circt::firrtl::NEQPrimOp)

Syntax:

operation ::= `firrtl.neq` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Traits: Commutative, SameOperandsIntTypeKind

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhssint or uint type

Results:

ResultDescription
resultUInt<1> or UInt

firrtl.neg (::circt::firrtl::NegPrimOp)

Syntax:

operation ::= `firrtl.neg` $input attr-dict `:` functional-type($input, $result)

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
inputsint or uint type

Results:

ResultDescription
resultsint type

firrtl.node (::circt::firrtl::NodeOp)

No-op to name a value

Syntax:

operation ::= `firrtl.node` (`sym` $inner_sym^)? custom<NameKind>($nameKind)
              $input custom<ImplicitSSAName>(attr-dict) `:` qualified(type($input))

A node is simply a named intermediate value in a circuit. The node must be initialized to a value with a passive type and cannot be connected to. Nodes are often used to split a complicated compound expression into named subexpressions.

  %result = firrtl.node %input : t1

Traits: SameOperandsAndResultType

Interfaces: FNamableOp, HasCustomSSAName, InferTypeOpInterface, InnerSymbol

Attributes:

AttributeMLIR TypeDescription
name::mlir::StringAttrstring attribute
nameKind::circt::firrtl::NameKindEnumAttrname kind
annotations::mlir::ArrayAttrAnnotation array attribute
inner_sym::circt::firrtl::InnerSymAttrInner symbol definition

Operands:

OperandDescription
inputa passive base type (contain no flips)

Results:

ResultDescription
resulta base type

firrtl.not (::circt::firrtl::NotPrimOp)

Syntax:

operation ::= `firrtl.not` $input attr-dict `:` functional-type($input, $result)

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
inputsint or uint type

Results:

ResultDescription
resultuint type

firrtl.or (::circt::firrtl::OrPrimOp)

Syntax:

operation ::= `firrtl.or` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Traits: Commutative, SameOperandsIntTypeKind

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhssint or uint type

Results:

ResultDescription
resultuint type

firrtl.orr (::circt::firrtl::OrRPrimOp)

Syntax:

operation ::= `firrtl.orr` $input attr-dict `:` functional-type($input, $result)

Horizontally reduce a value to one bit, using the ‘or’ operation to merge bits. orr(x) is equivalent to concat(x, 1b0) != 0. As such, it returns 0 for zero-bit-wide operands.

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
inputsint or uint type

Results:

ResultDescription
resultUInt<1> or UInt

firrtl.pad (::circt::firrtl::PadPrimOp)

Syntax:

operation ::= `firrtl.pad` $input `,` $amount attr-dict `:` functional-type($input, $result)

Pad the input out to an amount wide integer, sign extending or zero extending according to inputs type. If amount is less than the existing width of input, then input is unmodified.

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
amount::mlir::IntegerAttr32-bit signless integer attribute

Operands:

OperandDescription
inputsint or uint type

Results:

ResultDescription
resultsint or uint type

firrtl.printf (::circt::firrtl::PrintFOp)

Formatted Print Statement

Syntax:

operation ::= `firrtl.printf` $clock `,` $cond `,` $formatString custom<PrintfAttrs>(attr-dict)
              (`(` $substitutions^ `)` `:` qualified(type($substitutions)))?

Attributes:

AttributeMLIR TypeDescription
formatString::mlir::StringAttrstring attribute
name::mlir::StringAttrstring attribute

Operands:

OperandDescription
clockclock
condUInt<1> or UInt
substitutionsa base type

firrtl.probe (::circt::firrtl::ProbeOp)

FIRRTL Value Probe

Syntax:

operation ::= `firrtl.probe` $inner_sym attr-dict ( `,` $captured^  `:` qualified(type($captured)))?

Captures values without binding to any accidental name.

Attributes:

AttributeMLIR TypeDescription
inner_sym::mlir::StringAttrstring attribute

Operands:

OperandDescription
captureda base type

firrtl.reg (::circt::firrtl::RegOp)

Define a new register

Syntax:

operation ::= `firrtl.reg` (`sym` $inner_sym^)? custom<NameKind>($nameKind)
              operands custom<ImplicitSSAName>(attr-dict) `:` qualified(type($result))

Declare a new register:

%name = firrtl.reg %clockVal : t1

Interfaces: FNamableOp, HasCustomSSAName, InnerSymbol

Attributes:

AttributeMLIR TypeDescription
name::mlir::StringAttrstring attribute
nameKind::circt::firrtl::NameKindEnumAttrname kind
annotations::mlir::ArrayAttrAnnotation array attribute
inner_sym::circt::firrtl::InnerSymAttrInner symbol definition

Operands:

OperandDescription
clockValclock

Results:

ResultDescription
resulta passive type that does not contain analog

firrtl.regreset (::circt::firrtl::RegResetOp)

Define a new register with a reset

Syntax:

operation ::= `firrtl.regreset` (`sym` $inner_sym^)? custom<NameKind>($nameKind)
              operands custom<ImplicitSSAName>(attr-dict)
              `:` qualified(type($resetSignal)) `,` qualified(type($resetValue)) `,` qualified(type($result))

Declare a new register:

  %name = firrtl.regreset %clockVal, %resetSignal, %resetValue : t1

Interfaces: FNamableOp, HasCustomSSAName, InnerSymbol

Attributes:

AttributeMLIR TypeDescription
name::mlir::StringAttrstring attribute
nameKind::circt::firrtl::NameKindEnumAttrname kind
annotations::mlir::ArrayAttrAnnotation array attribute
inner_sym::circt::firrtl::InnerSymAttrInner symbol definition

Operands:

OperandDescription
clockValclock
resetSignalReset
resetValuea passive type that does not contain analog

Results:

ResultDescription
resulta passive type that does not contain analog

firrtl.rem (::circt::firrtl::RemPrimOp)

Syntax:

operation ::= `firrtl.rem` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Traits: SameOperandsIntTypeKind

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhssint or uint type

Results:

ResultDescription
resultsint or uint type

firrtl.shl (::circt::firrtl::ShlPrimOp)

Syntax:

operation ::= `firrtl.shl` $input `,` $amount attr-dict `:` functional-type($input, $result)

The shl operation concatenates amount zero bits to the least significant end of input. amount must be non-negative.

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
amount::mlir::IntegerAttr32-bit signless integer attribute

Operands:

OperandDescription
inputsint or uint type

Results:

ResultDescription
resultsint or uint type

firrtl.shr (::circt::firrtl::ShrPrimOp)

Syntax:

operation ::= `firrtl.shr` $input `,` $amount attr-dict `:` functional-type($input, $result)

The shr operation truncates least significant amount bits from input. If amount is greater than of equal to width(input), the value will be zero for unsigned types and the sign bit for signed types. amount must be non-negative.

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
amount::mlir::IntegerAttr32-bit signless integer attribute

Operands:

OperandDescription
inputsint or uint type

Results:

ResultDescription
resultsint or uint type

firrtl.skip (::circt::firrtl::SkipOp)

Skip statement

Syntax:

operation ::= `firrtl.skip` attr-dict

Skip Statement:

   %firrtl.skip

This is a no-op statement.

Interfaces: NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

firrtl.specialconstant (::circt::firrtl::SpecialConstantOp)

Produce a constant Reset or Clock value

The constant operation produces a constant value of Reset, AsyncReset, or Clock type. The value can only be 0 or 1.

  %result = firrtl.specialconstant 1 : !firrtl.clock

Traits: ConstantLike

Interfaces: HasCustomSSAName, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
value::mlir::BoolAttrbool attribute

Results:

ResultDescription
resultclock or Reset or AsyncReset

firrtl.stop (::circt::firrtl::StopOp)

Stop Statement

Syntax:

operation ::= `firrtl.stop` $clock `,` $cond `,` $exitCode custom<StopAttrs>(attr-dict)

Attributes:

AttributeMLIR TypeDescription
exitCode::mlir::IntegerAttr32-bit signless integer attribute
name::mlir::StringAttrstring attribute

Operands:

OperandDescription
clockclock
condUInt<1> or UInt

firrtl.strictconnect (::circt::firrtl::StrictConnectOp)

Connect two signals

Syntax:

operation ::= `firrtl.strictconnect` $dest `,` $src  attr-dict `:` qualified(type($dest))

Connect two values with strict constraints:

  firrtl.strictconnect %dest, %src : t1

Traits: SameTypeOperands

Interfaces: FConnectLike

Operands:

OperandDescription
desta sized type (contains no unifered widths)
srca sized type (contains no unifered widths)

firrtl.sub (::circt::firrtl::SubPrimOp)

Syntax:

operation ::= `firrtl.sub` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Traits: SameOperandsIntTypeKind

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhssint or uint type

Results:

ResultDescription
resultsint or uint type

firrtl.subaccess (::circt::firrtl::SubaccessOp)

Extract a dynamic element of a vector value

Syntax:

operation ::= `firrtl.subaccess` $input `[` $index `]` attr-dict `:` qualified(type($input)) `,` qualified(type($index))

The subaccess expression dynamically refers to a subelement of a vector-typed expression using a calculated index. The index must be an expression with an unsigned integer type.

  %result = firrtl.subaccess %input[%idx] : t1, t2

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
inputa base type
indexuint type

Results:

ResultDescription
resulta base type

firrtl.subfield (::circt::firrtl::SubfieldOp)

Extract a subfield of another value

Syntax:

operation ::= `firrtl.subfield` $input `(` $fieldIndex `)` attr-dict `:` functional-type($input, $result)

The subfield expression refers to a subelement of an expression with a bundle type.

  %result = firrtl.subfield %input "fieldIndex" : t1, t2

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
fieldIndex::mlir::IntegerAttr32-bit signless integer attribute

Operands:

OperandDescription
inputBundleType

Results:

ResultDescription
resulta base type

firrtl.subindex (::circt::firrtl::SubindexOp)

Extract an element of a vector value

Syntax:

operation ::= `firrtl.subindex` $input `[` $index `]` attr-dict `:` qualified(type($input))

The subindex expression statically refers, by index, to a subelement of an expression with a vector type. The index must be a non-negative integer and cannot be equal to or exceed the length of the vector it indexes.

  %result = firrtl.subindex %input[index] : t1

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
index::mlir::IntegerAttr32-bit signless integer attribute

Operands:

OperandDescription
inputa base type

Results:

ResultDescription
resulta base type

firrtl.tail (::circt::firrtl::TailPrimOp)

Syntax:

operation ::= `firrtl.tail` $input `,` $amount attr-dict `:` functional-type($input, $result)

The tail operation truncates the amount most significant bits from input. amount must be non-negative and less than or equal to the bit width of e. The result is width(input)-amount bits wide.

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
amount::mlir::IntegerAttr32-bit signless integer attribute

Operands:

OperandDescription
inputsint or uint type

Results:

ResultDescription
resultuint type

firrtl.verbatim.expr (::circt::firrtl::VerbatimExprOp)

Expression that expands to a value given SystemVerilog text

Syntax:

operation ::= `firrtl.verbatim.expr` $text (`(` $substitutions^ `)`)?
              `:` functional-type($substitutions, $result) attr-dict

This operation produces a typed value expressed by a string of SystemVerilog. This can be used to access macros and other values that are only sensible as Verilog text.

The text string is expected to have the highest precedence, so you should include parentheses in the string if it isn’t a single token. This is also assumed to not have side effects (use sv.verbatim if you need them).

firrtl.verbatim.expr allows operand substitutions with {{0}} syntax.

Interfaces: HasCustomSSAName, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
text::mlir::StringAttrstring attribute
symbols::mlir::ArrayAttrname reference array attribute

Operands:

OperandDescription
substitutionsany type

Results:

ResultDescription
resulta base type

firrtl.verbatim.wire (::circt::firrtl::VerbatimWireOp)

Expression with wire semantics that expands to a value given SystemVerilog text

Syntax:

operation ::= `firrtl.verbatim.wire` $text (`(` $substitutions^ `)`)?
              `:` functional-type($substitutions, $result) attr-dict

This operation produces a typed value with wire semantics, expressed by a string of SystemVerilog. This can be used to access macros and other values that are only sensible as Verilog text.

The text string is expected to have the highest precedence, so you should include parentheses in the string if it isn’t a single token. This is also assumed to not have side effects (use sv.verbatim if you need them).

firrtl.verbatim.wire allows operand substitutions with {{0}} syntax.

Interfaces: HasCustomSSAName, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
text::mlir::StringAttrstring attribute
symbols::mlir::ArrayAttrname reference array attribute

Operands:

OperandDescription
substitutionsany type

Results:

ResultDescription
resulta base type

firrtl.when (::circt::firrtl::WhenOp)

When Statement

Syntax:

operation ::= `firrtl.when` $condition $thenRegion (`else` $elseRegion^)? attr-dict-with-keyword

The “firrtl.when” operation represents a conditional. Connections within a conditional statement that connect to previously declared components hold only when the given condition is high. The condition must have a 1-bit unsigned integer type.

Traits: NoRegionArguments, NoTerminator, RecursiveSideEffects, SingleBlock

Operands:

OperandDescription
conditionUInt<1> or UInt

firrtl.wire (::circt::firrtl::WireOp)

Define a new wire

Syntax:

operation ::= `firrtl.wire` (`sym` $inner_sym^)? custom<NameKind>($nameKind)
              custom<ImplicitSSAName>(attr-dict) `:` qualified(type($result))

Declare a new wire:

  %name = firrtl.wire : t1

Interfaces: FNamableOp, HasCustomSSAName, InnerSymbol

Attributes:

AttributeMLIR TypeDescription
name::mlir::StringAttrstring attribute
nameKind::circt::firrtl::NameKindEnumAttrname kind
annotations::mlir::ArrayAttrAnnotation array attribute
inner_sym::circt::firrtl::InnerSymAttrInner symbol definition

Results:

ResultDescription
resulta base type

firrtl.xor (::circt::firrtl::XorPrimOp)

Syntax:

operation ::= `firrtl.xor` $lhs `,` $rhs  attr-dict `:`
              `(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))

Traits: Commutative, SameOperandsIntTypeKind

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
lhssint or uint type
rhssint or uint type

Results:

ResultDescription
resultuint type

firrtl.xorr (::circt::firrtl::XorRPrimOp)

Syntax:

operation ::= `firrtl.xorr` $input attr-dict `:` functional-type($input, $result)

Horizontally reduce a value to one bit, using the ‘xor’ operation to merge bits. xorr(x) is equivalent to popcount(concat(x, 1b0)) & 1. As such, it returns 0 for zero-bit-wide operands.

Interfaces: HasCustomSSAName, InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands:

OperandDescription
inputsint or uint type

Results:

ResultDescription
resultUInt<1> or UInt

Attribute definition

AugmentedBooleanTypeAttr

GrandCentral AugmentedBooleanType

Used in the GrandCentralPass.

Parameters:

ParameterC++ typeDescription
underlyingDictionaryAttr

AugmentedBundleTypeAttr

GrandCentral AugmentedBundleType

Used in the GrandCentralPass.

Parameters:

ParameterC++ typeDescription
underlyingDictionaryAttr

AugmentedDeletedTypeAttr

GrandCentral AugmentedDeletedType

Used in the GrandCentralPass.

Parameters:

ParameterC++ typeDescription
underlyingDictionaryAttr

AugmentedDoubleTypeAttr

GrandCentral AugmentedDoubleType

Used in the GrandCentralPass.

Parameters:

ParameterC++ typeDescription
underlyingDictionaryAttr

AugmentedGroundTypeAttr

GrandCentral AugmentedGroundType

Used in the GrandCentralPass.

Parameters:

ParameterC++ typeDescription
underlyingDictionaryAttr

AugmentedIntegerTypeAttr

GrandCentral AugmentedIntegerType

Used in the GrandCentralPass.

Parameters:

ParameterC++ typeDescription
underlyingDictionaryAttr

AugmentedLiteralTypeAttr

GrandCentral AugmentedLiteralType

Used in the GrandCentralPass.

Parameters:

ParameterC++ typeDescription
underlyingDictionaryAttr

AugmentedStringTypeAttr

GrandCentral AugmentedStringType

Used in the GrandCentralPass.

Parameters:

ParameterC++ typeDescription
underlyingDictionaryAttr

AugmentedVectorTypeAttr

GrandCentral AugmentedVectorType

Used in the GrandCentralPass.

Parameters:

ParameterC++ typeDescription
underlyingDictionaryAttr

InnerSymAttr

Inner symbol definition

Defines the properties of an inner_sym attribute. It specifies the symbol name and symbol visibility for each field ID. For any ground types, there are no subfields and the field ID is 0. For aggregate types, a unique field ID is assigned to each field by visiting them in a depth-first pre-order. The custom assembly format ensures that for ground types, only @<sym_name> is printed.

Parameters:

ParameterC++ typeDescription
props::llvm::ArrayRef<InnerSymPropertiesAttr>

InnerSymPropertiesAttr

Parameters:

ParameterC++ typeDescription
nameStringAttr
fieldIDint64_t
sym_visibility::mlir::StringAttr

InvalidValueAttr

A constant value of firrtl.invalid type

Syntax:

!firrtl.invalidvalue<
  ::mlir::Type   # type
>

Represents an firrtl.invalidvalue value, whose type is specified by the type of the attribute.

Parameters:

ParameterC++ typeDescription
type::mlir::Type

NameKindEnumAttr

name kind

Syntax:

!firrtl.name_kind<
  ::circt::firrtl::NameKindEnum   # value
>

Parameters:

ParameterC++ typeDescription
value::circt::firrtl::NameKindEnuman enum of type NameKindEnum

ParamDeclAttr

Module or instance parameter definition

An attribute describing a module parameter, or instance parameter specification.

Parameters:

ParameterC++ typeDescription
name::mlir::StringAttr
type::mlir::Type
value::mlir::Attribute

Type constraint definition

analog type

a passive type that does not contain analog

Reset

AsyncReset

BundleType

clock

a connectable type (base type)

Any type that is valid for use in connect statements. Currently this is any base type.

a base type

A base FIRRTL type, such as a clock, integer, or wire.

Base types represent circuit elements and constructs, examples include ClockType, IntType, or BundleType. Nearly all FIRRTL types are base types.

All base types are FIRRTLType’s, and inherit from FIRRTLBaseType.

FIRRTLType

Any FIRRTL dialect type, represented by FIRRTLType.

FVectorType

sint or uint type

UInt<1>, SInt<1>, or Analog<1>

a passive base type (contain no flips)

Reset

sint type

a sized type (contains no unifered widths)

UInt<1> or UInt

uint type

'firrtl' Dialect Docs