CIRCT

Circuit IR Compilers and Tools

'firrtl' Dialect

Types and operations for firrtl dialect This dialect defines the firrtl dialect, which is used to lower from Chisel code to Verilog. For more information, see the FIRRTL GitHub page .

Attribute definition 

InvalidValueAttr 

A constant value of firrtl.invalid type

Represents an firrtl.invalidvalue value, whose type is specified by the type of the attribute.

Parameters: 

ParameterC++ typeDescription
type::mlir::Type

SubAnnotationAttr 

An Annotation that targets part of what it’s attached to

An Annotation that is only applicable to part of what it is attached to. This uses a field ID to indicate to which field it is applicable.

Parameters: 

ParameterC++ typeDescription
fieldIDint64_t
annotationsDictionaryAttr

Type constraint definition 

analog type 

AsyncReset 

BundleType 

clock 

FIRRTLType 

FVectorType 

sint or uint type 

Int 

UInt<1>, SInt<1>, or Analog<1> 

a passive type (contain no flips) 

Reset 

sint type 

UInt<1> or UInt 

uint type 

Operation definition 

firrtl.add (::circt::firrtl::AddPrimOp) 

Syntax:

operation ::= `firrtl.add` $lhs `,` $rhs  attr-dict `:`
              `(` type($lhs) `,` type($rhs) `)` `->` type($result)

Operands: 

OperandDescription
lhssint or uint type
rhssint or uint type

Results: 

ResultDescription
resultsint or uint type

firrtl.analogInOutCast (::circt::firrtl::AnalogInOutCastOp) 

Syntax:

operation ::= `firrtl.analogInOutCast` $input attr-dict `:` functional-type($input, $result)

Operands: 

OperandDescription
inputany type

Results: 

ResultDescription
resultany type

firrtl.and (::circt::firrtl::AndPrimOp) 

Syntax:

operation ::= `firrtl.and` $lhs `,` $rhs  attr-dict `:`
              `(` type($lhs) `,` type($rhs) `)` `->` type($result)

Operands: 

OperandDescription
lhssint or uint type
rhssint or uint type

Results: 

ResultDescription
resultuint type

firrtl.andr (::circt::firrtl::AndRPrimOp) 

Syntax:

operation ::= `firrtl.andr` $input attr-dict `:` functional-type($input, $result)

Horizontally reduce a value to one bit, using the ‘and’ operation to merge bits. andr(x) is equivalent to concat(x, 1b1) == ~0. As such, it returns 1 for zero-bit-wide operands.

Operands: 

OperandDescription
inputsint or uint type

Results: 

ResultDescription
resultUInt<1> or UInt

firrtl.asAsyncReset (::circt::firrtl::AsAsyncResetPrimOp) 

Syntax:

operation ::= `firrtl.asAsyncReset` $input attr-dict `:` functional-type($input, $result)

Operands: 

OperandDescription
input1-bit uint/sint/analog, reset, asyncreset, or clock

Results: 

ResultDescription
resultAsyncReset

firrtl.asClock (::circt::firrtl::AsClockPrimOp) 

Syntax:

operation ::= `firrtl.asClock` $input attr-dict `:` functional-type($input, $result)

Operands: 

OperandDescription
input1-bit uint/sint/analog, reset, asyncreset, or clock

Results: 

ResultDescription
resultclock

firrtl.asNonPassive (::circt::firrtl::AsNonPassivePrimOp) 

Syntax:

operation ::= `firrtl.asNonPassive` $input attr-dict `:` type($result)

Operands: 

OperandDescription
inputa passive type (contain no flips)

Results: 

ResultDescription
resultFIRRTLType

firrtl.asPassive (::circt::firrtl::AsPassivePrimOp) 

Syntax:

operation ::= `firrtl.asPassive` $input attr-dict `:` type($input)

Operands: 

OperandDescription
inputFIRRTLType

Results: 

ResultDescription
resulta passive type (contain no flips)

firrtl.asSInt (::circt::firrtl::AsSIntPrimOp) 

Syntax:

operation ::= `firrtl.asSInt` $input attr-dict `:` functional-type($input, $result)

Operands: 

OperandDescription
inputFIRRTLType

Results: 

ResultDescription
resultsint type

firrtl.asUInt (::circt::firrtl::AsUIntPrimOp) 

Syntax:

operation ::= `firrtl.asUInt` $input attr-dict `:` functional-type($input, $result)

Operands: 

OperandDescription
inputFIRRTLType

Results: 

ResultDescription
resultuint type

firrtl.assert (::circt::firrtl::AssertOp) 

Assert Verification Statement

Syntax:

operation ::= `firrtl.assert` $clock `,` $predicate `,` $enable `,` $message custom<VerifAttrs>(attr-dict)

Attributes: 

AttributeMLIR TypeDescription
message::mlir::StringAttrstring attribute
name::mlir::StringAttrstring attribute

Operands: 

OperandDescription
clockclock
predicateUInt<1> or UInt
enableUInt<1> or UInt

firrtl.assume (::circt::firrtl::AssumeOp) 

Assume Verification Statement

Syntax:

operation ::= `firrtl.assume` $clock `,` $predicate `,` $enable `,` $message custom<VerifAttrs>(attr-dict)

Attributes: 

AttributeMLIR TypeDescription
message::mlir::StringAttrstring attribute
name::mlir::StringAttrstring attribute

Operands: 

OperandDescription
clockclock
predicateUInt<1> or UInt
enableUInt<1> or UInt

firrtl.attach (::circt::firrtl::AttachOp) 

Analog Attach Statement

Syntax:

operation ::= `firrtl.attach` $operands attr-dict `:` type($operands)

Operands: 

OperandDescription
operandsanalog type

firrtl.bits (::circt::firrtl::BitsPrimOp) 

Syntax:

operation ::= `firrtl.bits` $input $hi `to` $lo attr-dict `:` functional-type($input, $result)

The bits operation extracts the bits between hi (inclusive) and lo (inclusive) from input. hi must be greater than or equal to lo. Both hi and lo must be non-negative and less than the bit width of input. The result is hi - lo + 1 bits wide.

Attributes: 

AttributeMLIR TypeDescription
hi::mlir::IntegerAttr32-bit signless integer attribute
lo::mlir::IntegerAttr32-bit signless integer attribute

Operands: 

OperandDescription
inputsint or uint type

Results: 

ResultDescription
resultuint type

firrtl.cmem (::circt::firrtl::CMemOp) 

Define a new cmem

Syntax:

operation ::= `firrtl.cmem` custom<ElideAnnotations>(attr-dict) `:` type($result)

Attributes: 

AttributeMLIR TypeDescription
name::mlir::StringAttrstring attribute
annotations::mlir::ArrayAttr

Results: 

ResultDescription
resultFIRRTLType

firrtl.cat (::circt::firrtl::CatPrimOp) 

Syntax:

operation ::= `firrtl.cat` $lhs `,` $rhs  attr-dict `:`
              `(` type($lhs) `,` type($rhs) `)` `->` type($result)

Operands: 

OperandDescription
lhssint or uint type
rhssint or uint type

Results: 

ResultDescription
resultuint type

firrtl.circuit (::circt::firrtl::CircuitOp) 

FIRRTL Circuit

Syntax:

operation ::= `firrtl.circuit` $name custom<CircuitOpAttrs>(attr-dict) $body

The “firrtl.circuit” operation represents an overall Verilog circuit, containing a list of modules.

Attributes: 

AttributeMLIR TypeDescription
name::mlir::StringAttrstring attribute
annotations::mlir::ArrayAttr

firrtl.connect (::circt::firrtl::ConnectOp) 

Connect two signals

Syntax:

operation ::= `firrtl.connect` $dest `,` $src  attr-dict `:` type($dest) `,` type($src)

Connect Operation:

  firrtl.connect %dest, %src : t1, t2

Operands: 

OperandDescription
destFIRRTLType
srcFIRRTLType

firrtl.constant (::circt::firrtl::ConstantOp) 

Produce a constant value

The constant operation produces a constant value of SInt or UInt type, it never produces a zero bit wide result.

  %result = firrtl.constant 42 : t1

Attributes: 

AttributeMLIR TypeDescription
value::mlir::IntegerAttrarbitrary integer attribute with sign

Results: 

ResultDescription
resultInt

firrtl.cover (::circt::firrtl::CoverOp) 

Cover Verification Statement

Syntax:

operation ::= `firrtl.cover` $clock `,` $predicate `,` $enable `,` $message custom<VerifAttrs>(attr-dict)

Attributes: 

AttributeMLIR TypeDescription
message::mlir::StringAttrstring attribute
name::mlir::StringAttrstring attribute

Operands: 

OperandDescription
clockclock
predicateUInt<1> or UInt
enableUInt<1> or UInt

firrtl.cvt (::circt::firrtl::CvtPrimOp) 

Syntax:

operation ::= `firrtl.cvt` $input attr-dict `:` functional-type($input, $result)

Operands: 

OperandDescription
inputsint or uint type

Results: 

ResultDescription
resultsint type

firrtl.dshl (::circt::firrtl::DShlPrimOp) 

Syntax:

operation ::= `firrtl.dshl` $lhs `,` $rhs  attr-dict `:`
              `(` type($lhs) `,` type($rhs) `)` `->` type($result)

A dynamic shift left operation. The width of $result is expanded to width($lhs) + 1 << width($rhs) - 1.

Operands: 

OperandDescription
lhssint or uint type
rhsuint type

Results: 

ResultDescription
resultsint or uint type

firrtl.dshlw (::circt::firrtl::DShlwPrimOp) 

Syntax:

operation ::= `firrtl.dshlw` $lhs `,` $rhs  attr-dict `:`
              `(` type($lhs) `,` type($rhs) `)` `->` type($result)

A dynamic shift left operation same as ‘dshl’ but with different width rule. The width of $result is equal to $lhs.

Operands: 

OperandDescription
lhssint or uint type
rhsuint type

Results: 

ResultDescription
resultsint or uint type

firrtl.dshr (::circt::firrtl::DShrPrimOp) 

Syntax:

operation ::= `firrtl.dshr` $lhs `,` $rhs  attr-dict `:`
              `(` type($lhs) `,` type($rhs) `)` `->` type($result)

Operands: 

OperandDescription
lhssint or uint type
rhsuint type

Results: 

ResultDescription
resultsint or uint type

firrtl.div (::circt::firrtl::DivPrimOp) 

Syntax:

operation ::= `firrtl.div` $lhs `,` $rhs  attr-dict `:`
              `(` type($lhs) `,` type($rhs) `)` `->` type($result)

Divides the first argument (the numerator) by the second argument (the denominator) truncating the result (rounding towards zero).

If the denominator is zero, the result is undefined.

The compiler may optimize this undefined behavior in any way it wants. Notably div(a, a) will be optimized to 1. This may cause erroneous formal equivalence mismatches between unoptimized and optimized FIRRTL dialects that are separately converted to Verilog.

Operands: 

OperandDescription
lhssint or uint type
rhssint or uint type

Results: 

ResultDescription
resultsint or uint type

firrtl.eq (::circt::firrtl::EQPrimOp) 

Syntax:

operation ::= `firrtl.eq` $lhs `,` $rhs  attr-dict `:`
              `(` type($lhs) `,` type($rhs) `)` `->` type($result)

Operands: 

OperandDescription
lhssint or uint type
rhssint or uint type

Results: 

ResultDescription
resultUInt<1> or UInt

firrtl.extmodule (::circt::firrtl::FExtModuleOp) 

FIRRTL extmodule

The “firrtl.extmodule” operation represents an external reference to a Verilog module, including a given name and a list of ports.

Attributes: 

AttributeMLIR TypeDescription
portNames::mlir::ArrayAttrstring array attribute
defname::mlir::StringAttrstring attribute
parameters::mlir::DictionaryAttrdictionary of named attribute values
annotations::mlir::ArrayAttr

firrtl.module (::circt::firrtl::FModuleOp) 

FIRRTL Module

The “firrtl.module” operation represents a Verilog module, including a given name, a list of ports, and a body that represents the connections within the module.

Attributes: 

AttributeMLIR TypeDescription
portNames::mlir::ArrayAttrstring array attribute
annotations::mlir::ArrayAttr

firrtl.geq (::circt::firrtl::GEQPrimOp) 

Syntax:

operation ::= `firrtl.geq` $lhs `,` $rhs  attr-dict `:`
              `(` type($lhs) `,` type($rhs) `)` `->` type($result)

Operands: 

OperandDescription
lhssint or uint type
rhssint or uint type

Results: 

ResultDescription
resultUInt<1> or UInt

firrtl.gt (::circt::firrtl::GTPrimOp) 

Syntax:

operation ::= `firrtl.gt` $lhs `,` $rhs  attr-dict `:`
              `(` type($lhs) `,` type($rhs) `)` `->` type($result)

Operands: 

OperandDescription
lhssint or uint type
rhssint or uint type

Results: 

ResultDescription
resultUInt<1> or UInt

firrtl.hwStructCast (::circt::firrtl::HWStructCastOp) 

Syntax:

operation ::= `firrtl.hwStructCast` $input attr-dict `:` functional-type($input, $result)

Operands: 

OperandDescription
inputany type

Results: 

ResultDescription
resultany type

firrtl.head (::circt::firrtl::HeadPrimOp) 

Syntax:

operation ::= `firrtl.head` $input `,` $amount attr-dict `:` functional-type($input, $result)

Attributes: 

AttributeMLIR TypeDescription
amount::mlir::IntegerAttr32-bit signless integer attribute

Operands: 

OperandDescription
inputsint or uint type

Results: 

ResultDescription
resultuint type

firrtl.instance (::circt::firrtl::InstanceOp) 

Instantiate an instance of a module

Syntax:

operation ::= `firrtl.instance` $moduleName custom<InstanceOp>(attr-dict) (`:` type($results)^ )?

This represents an instance of a module. The results are the modules inputs and outputs. The inputs have flip type, the outputs do not.

Attributes: 

AttributeMLIR TypeDescription
moduleName::mlir::FlatSymbolRefAttrflat symbol reference attribute
name::mlir::StringAttrstring attribute
annotations::mlir::ArrayAttr
portAnnotations::mlir::ArrayAttrFIRRTL port annotations
lowerToBind::mlir::BoolAttrbool attribute

Results: 

ResultDescription
resultsFIRRTLType

firrtl.invalidvalue (::circt::firrtl::InvalidValueOp) 

InvalidValue primitive

Syntax:

operation ::= `firrtl.invalidvalue` attr-dict `:` type($result)

The InvalidValue operation returns an invalid value of a specified type:

  %result = firrtl.invalid : !firrtl.uint<1>

This corresponds to the FIRRTL invalidate operation without the implicit connect semantics.

Results: 

ResultDescription
resultFIRRTLType

firrtl.leq (::circt::firrtl::LEQPrimOp) 

Syntax:

operation ::= `firrtl.leq` $lhs `,` $rhs  attr-dict `:`
              `(` type($lhs) `,` type($rhs) `)` `->` type($result)

Operands: 

OperandDescription
lhssint or uint type
rhssint or uint type

Results: 

ResultDescription
resultUInt<1> or UInt

firrtl.lt (::circt::firrtl::LTPrimOp) 

Syntax:

operation ::= `firrtl.lt` $lhs `,` $rhs  attr-dict `:`
              `(` type($lhs) `,` type($rhs) `)` `->` type($result)

Operands: 

OperandDescription
lhssint or uint type
rhssint or uint type

Results: 

ResultDescription
resultUInt<1> or UInt

firrtl.mem (::circt::firrtl::MemOp) 

Define a new mem

Syntax:

operation ::= `firrtl.mem` $ruw custom<MemOp>(attr-dict) `:` type($results)

Attributes: 

AttributeMLIR TypeDescription
readLatency::mlir::IntegerAttr32-bit signless integer attribute whose minimum value is 0
writeLatency::mlir::IntegerAttr32-bit signless integer attribute whose minimum value is 1
depth::mlir::IntegerAttr64-bit signless integer attribute whose minimum value is 1
ruw::RUWAttrAttrRead Under Write Enum
portNames::mlir::ArrayAttrstring array attribute
name::mlir::StringAttrstring attribute
annotations::mlir::ArrayAttr
portAnnotations::mlir::ArrayAttrFIRRTL port annotations

Results: 

ResultDescription
resultsFIRRTLType

firrtl.memoryport (::circt::firrtl::MemoryPortOp) 

Access a memory

Syntax:

operation ::= `firrtl.memoryport` $direction $memory `,` $index `,` $clock custom<MemoryPortOp>(attr-dict) `:`
              functional-type(operands, $result)

Attributes: 

AttributeMLIR TypeDescription
direction::MemDirAttrAttrMemory Direction Enum
name::mlir::StringAttrstring attribute
annotations::mlir::ArrayAttr

Operands: 

OperandDescription
memoryFIRRTLType
indexsint or uint type
clockclock

Results: 

ResultDescription
resultFIRRTLType

firrtl.mul (::circt::firrtl::MulPrimOp) 

Syntax:

operation ::= `firrtl.mul` $lhs `,` $rhs  attr-dict `:`
              `(` type($lhs) `,` type($rhs) `)` `->` type($result)

Operands: 

OperandDescription
lhssint or uint type
rhssint or uint type

Results: 

ResultDescription
resultsint or uint type

firrtl.mux (::circt::firrtl::MuxPrimOp) 

Syntax:

operation ::= `firrtl.mux` `(` operands `)` attr-dict `:` functional-type(operands, $result)

Operands: 

OperandDescription
selUInt<1> or UInt
higha passive type (contain no flips)
lowa passive type (contain no flips)

Results: 

ResultDescription
resulta passive type (contain no flips)

firrtl.neq (::circt::firrtl::NEQPrimOp) 

Syntax:

operation ::= `firrtl.neq` $lhs `,` $rhs  attr-dict `:`
              `(` type($lhs) `,` type($rhs) `)` `->` type($result)

Operands: 

OperandDescription
lhssint or uint type
rhssint or uint type

Results: 

ResultDescription
resultUInt<1> or UInt

firrtl.neg (::circt::firrtl::NegPrimOp) 

Syntax:

operation ::= `firrtl.neg` $input attr-dict `:` functional-type($input, $result)

Operands: 

OperandDescription
inputsint or uint type

Results: 

ResultDescription
resultsint type

firrtl.node (::circt::firrtl::NodeOp) 

No-op to name a value

Syntax:

operation ::= `firrtl.node` $input custom<ImplicitSSAName>(attr-dict) `:` type($input)

A node is simply a named intermediate value in a circuit. The node must be initialized to a value with a passive type and cannot be connected to. Nodes are often used to split a complicated compound expression into named subexpressions.

  %result = firrtl.node %input : t1

Attributes: 

AttributeMLIR TypeDescription
name::mlir::StringAttrstring attribute
annotations::mlir::ArrayAttr

Operands: 

OperandDescription
inputa passive type (contain no flips)

Results: 

ResultDescription
resultFIRRTLType

firrtl.not (::circt::firrtl::NotPrimOp) 

Syntax:

operation ::= `firrtl.not` $input attr-dict `:` functional-type($input, $result)

Operands: 

OperandDescription
inputsint or uint type

Results: 

ResultDescription
resultuint type

firrtl.or (::circt::firrtl::OrPrimOp) 

Syntax:

operation ::= `firrtl.or` $lhs `,` $rhs  attr-dict `:`
              `(` type($lhs) `,` type($rhs) `)` `->` type($result)

Operands: 

OperandDescription
lhssint or uint type
rhssint or uint type

Results: 

ResultDescription
resultuint type

firrtl.orr (::circt::firrtl::OrRPrimOp) 

Syntax:

operation ::= `firrtl.orr` $input attr-dict `:` functional-type($input, $result)

Horizontally reduce a value to one bit, using the ‘or’ operation to merge bits. orr(x) is equivalent to concat(x, 1b0) != 0. As such, it returns 0 for zero-bit-wide operands.

Operands: 

OperandDescription
inputsint or uint type

Results: 

ResultDescription
resultUInt<1> or UInt

firrtl.pad (::circt::firrtl::PadPrimOp) 

Syntax:

operation ::= `firrtl.pad` $input `,` $amount attr-dict `:` functional-type($input, $result)

Pad the input out to an amount wide integer, sign extending or zero extending according to inputs type. If amount is less than the existing width of input, then input is unmodified.

Attributes: 

AttributeMLIR TypeDescription
amount::mlir::IntegerAttr32-bit signless integer attribute

Operands: 

OperandDescription
inputsint or uint type

Results: 

ResultDescription
resultsint or uint type

firrtl.partialconnect (::circt::firrtl::PartialConnectOp) 

Connect two signals

Syntax:

operation ::= `firrtl.partialconnect` $dest `,` $src  attr-dict `:` type($dest) `,` type($src)

Connect two values with fewer constraints:

  firrtl.partialconnect %dest, %src : t1, t2

Operands: 

OperandDescription
destFIRRTLType
srcFIRRTLType

firrtl.printf (::circt::firrtl::PrintFOp) 

Formatted Print Statement

Syntax:

operation ::= `firrtl.printf` $clock `,` $cond `,` $formatString custom<PrintfAttrs>(attr-dict)
              (`(` $operands^ `)` `:` type($operands))?

Attributes: 

AttributeMLIR TypeDescription
formatString::mlir::StringAttrstring attribute
name::mlir::StringAttrstring attribute

Operands: 

OperandDescription
clockclock
condUInt<1> or UInt
operandsFIRRTLType

firrtl.reg (::circt::firrtl::RegOp) 

Define a new register

Syntax:

operation ::= `firrtl.reg` operands custom<ImplicitSSAName>(attr-dict) `:` functional-type(operands, $result)

Declare a new register:

  %name = firrtl.reg %clockVal : t1

Attributes: 

AttributeMLIR TypeDescription
name::mlir::StringAttrstring attribute
annotations::mlir::ArrayAttr

Operands: 

OperandDescription
clockValclock

Results: 

ResultDescription
resulta passive type (contain no flips)

firrtl.regreset (::circt::firrtl::RegResetOp) 

Define a new register with a reset

Syntax:

operation ::= `firrtl.regreset` operands custom<ImplicitSSAName>(attr-dict) `:` functional-type(operands, $result)

Declare a new register:

  %name = firrtl.regreset %clockVal, %resetSignal, %resetValue : t1

Attributes: 

AttributeMLIR TypeDescription
name::mlir::StringAttrstring attribute
annotations::mlir::ArrayAttr

Operands: 

OperandDescription
clockValclock
resetSignalReset
resetValuea passive type (contain no flips)

Results: 

ResultDescription
resulta passive type (contain no flips)

firrtl.rem (::circt::firrtl::RemPrimOp) 

Syntax:

operation ::= `firrtl.rem` $lhs `,` $rhs  attr-dict `:`
              `(` type($lhs) `,` type($rhs) `)` `->` type($result)

Operands: 

OperandDescription
lhssint or uint type
rhssint or uint type

Results: 

ResultDescription
resultsint or uint type

firrtl.smem (::circt::firrtl::SMemOp) 

Define a new smem

Syntax:

operation ::= `firrtl.smem` $ruw custom<SMemOp>(attr-dict) `:` type($result)

Attributes: 

AttributeMLIR TypeDescription
ruw::RUWAttrAttrRead Under Write Enum
name::mlir::StringAttrstring attribute
annotations::mlir::ArrayAttr

Results: 

ResultDescription
resultFIRRTLType

firrtl.shl (::circt::firrtl::ShlPrimOp) 

Syntax:

operation ::= `firrtl.shl` $input `,` $amount attr-dict `:` functional-type($input, $result)

The shl operation concatenates amount zero bits to the least significant end of input. amount must be non-negative.

Attributes: 

AttributeMLIR TypeDescription
amount::mlir::IntegerAttr32-bit signless integer attribute

Operands: 

OperandDescription
inputsint or uint type

Results: 

ResultDescription
resultsint or uint type

firrtl.shr (::circt::firrtl::ShrPrimOp) 

Syntax:

operation ::= `firrtl.shr` $input `,` $amount attr-dict `:` functional-type($input, $result)

The shr operation truncates least significant amount bits from input. If amount is greater than of equal to width(input), the value will be zero for unsigned types and the sign bit for signed types. amount must be non-negative.

Attributes: 

AttributeMLIR TypeDescription
amount::mlir::IntegerAttr32-bit signless integer attribute

Operands: 

OperandDescription
inputsint or uint type

Results: 

ResultDescription
resultsint or uint type

firrtl.skip (::circt::firrtl::SkipOp) 

Skip statement

Syntax:

operation ::= `firrtl.skip` attr-dict

Skip Statement:

   %firrtl.skip

This is a no-op statement.

firrtl.specialconstant (::circt::firrtl::SpecialConstantOp) 

Produce a constant Reset or Clock value

The constant operation produces a constant value of Reset, AsyncReset, or Clock type. The value can only be 0 or 1.

  %result = firrtl.specialconstant 1 : !firrtl.clock

Attributes: 

AttributeMLIR TypeDescription
value::mlir::BoolAttrbool attribute

Results: 

ResultDescription
resultclock or Reset or AsyncReset

firrtl.stdIntCast (::circt::firrtl::StdIntCastOp) 

Syntax:

operation ::= `firrtl.stdIntCast` $input attr-dict `:` functional-type($input, $result)

Operands: 

OperandDescription
inputpassive FIRRTL type or signless builtin integer

Results: 

ResultDescription
resultpassive FIRRTL type or signless builtin integer

firrtl.stop (::circt::firrtl::StopOp) 

Stop Statement

Syntax:

operation ::= `firrtl.stop` $clock `,` $cond `,` $exitCode custom<StopAttrs>(attr-dict)

Attributes: 

AttributeMLIR TypeDescription
exitCode::mlir::IntegerAttr32-bit signless integer attribute
name::mlir::StringAttrstring attribute

Operands: 

OperandDescription
clockclock
condUInt<1> or UInt

firrtl.sub (::circt::firrtl::SubPrimOp) 

Syntax:

operation ::= `firrtl.sub` $lhs `,` $rhs  attr-dict `:`
              `(` type($lhs) `,` type($rhs) `)` `->` type($result)

Operands: 

OperandDescription
lhssint or uint type
rhssint or uint type

Results: 

ResultDescription
resultsint or uint type

firrtl.subaccess (::circt::firrtl::SubaccessOp) 

Extract a dynamic element of a vector value

Syntax:

operation ::= `firrtl.subaccess` $input `[` $index `]` attr-dict `:` type($input) `,` type($index)

The subaccess expression dynamically refers to a subelement of a vector-typed expression using a calculated index. The index must be an expression with an unsigned integer type.

  %result = firrtl.subaccess %input[%idx] : t1, t2

Operands: 

OperandDescription
inputFIRRTLType
indexuint type

Results: 

ResultDescription
resultFIRRTLType

firrtl.subfield (::circt::firrtl::SubfieldOp) 

Extract a subfield of another value

Syntax:

operation ::= `firrtl.subfield` $input `(` $fieldIndex `)` attr-dict `:` functional-type($input, $result)

The subfield expression refers to a subelement of an expression with a bundle type.

  %result = firrtl.subfield %input "fieldIndex" : t1, t2

Attributes: 

AttributeMLIR TypeDescription
fieldIndex::mlir::IntegerAttr32-bit signless integer attribute

Operands: 

OperandDescription
inputBundleType

Results: 

ResultDescription
resultFIRRTLType

firrtl.subindex (::circt::firrtl::SubindexOp) 

Extract an element of a vector value

Syntax:

operation ::= `firrtl.subindex` $input `[` $index `]` attr-dict `:` type($input)

The subindex expression statically refers, by index, to a subelement of an expression with a vector type. The index must be a non-negative integer and cannot be equal to or exceed the length of the vector it indexes.

  %result = firrtl.subindex %input[index] : t1

Attributes: 

AttributeMLIR TypeDescription
index::mlir::IntegerAttr32-bit signless integer attribute

Operands: 

OperandDescription
inputFIRRTLType

Results: 

ResultDescription
resultFIRRTLType

firrtl.tail (::circt::firrtl::TailPrimOp) 

Syntax:

operation ::= `firrtl.tail` $input `,` $amount attr-dict `:` functional-type($input, $result)

The tail operation truncates the amount most significant bits from input. amount must be non-negative and less than or equal to the bit width of e. The result is width(input)-amount bits wide.

Attributes: 

AttributeMLIR TypeDescription
amount::mlir::IntegerAttr32-bit signless integer attribute

Operands: 

OperandDescription
inputsint or uint type

Results: 

ResultDescription
resultuint type

firrtl.verbatim.expr (::circt::firrtl::VerbatimExprOp) 

Expression that expands to a value given SystemVerilog text

Syntax:

operation ::= `firrtl.verbatim.expr` $text attr-dict (`(` $operands^ `)`)?
              `:` functional-type($operands, $result)

This operation produces a typed value expressed by a string of SystemVerilog. This can be used to access macros and other values that are only sensible as Verilog text.

The text string is expected to have the highest precedence, so you should include parentheses in the string if it isn’t a single token. This is also assumed to not have side effects (use sv.verbatim if you need them).

firrtl.verbatim.expr allows operand substitutions with {{0}} syntax.

Attributes: 

AttributeMLIR TypeDescription
text::mlir::StringAttrstring attribute

Operands: 

OperandDescription
operandsany type

Results: 

ResultDescription
resultFIRRTLType

firrtl.when (::circt::firrtl::WhenOp) 

When Statement

Syntax:

operation ::= `firrtl.when` $condition $thenRegion (`else` $elseRegion^)? attr-dict-with-keyword

The “firrtl.when” operation represents a conditional. Connections within a conditional statement that connect to previously declared components hold only when the given condition is high. The condition must have a 1-bit unsigned integer type.

Operands: 

OperandDescription
conditionUInt<1> or UInt

firrtl.wire (::circt::firrtl::WireOp) 

Define a new wire

Syntax:

operation ::= `firrtl.wire` custom<ImplicitSSAName>(attr-dict) `:` type($result)

Declare a new wire:

  %name = firrtl.wire : t1

Attributes: 

AttributeMLIR TypeDescription
name::mlir::StringAttrstring attribute
annotations::mlir::ArrayAttr

Results: 

ResultDescription
resultFIRRTLType

firrtl.xor (::circt::firrtl::XorPrimOp) 

Syntax:

operation ::= `firrtl.xor` $lhs `,` $rhs  attr-dict `:`
              `(` type($lhs) `,` type($rhs) `)` `->` type($result)

Operands: 

OperandDescription
lhssint or uint type
rhssint or uint type

Results: 

ResultDescription
resultuint type

firrtl.xorr (::circt::firrtl::XorRPrimOp) 

Syntax:

operation ::= `firrtl.xorr` $input attr-dict `:` functional-type($input, $result)

Horizontally reduce a value to one bit, using the ‘xor’ operation to merge bits. xorr(x) is equivalent to popcount(concat(x, 1b0)) & 1. As such, it returns 0 for zero-bit-wide operands.

Operands: 

OperandDescription
inputsint or uint type

Results: 

ResultDescription
resultUInt<1> or UInt