'firrtl' Dialect
This dialect defines the firrtl
dialect, which is used to lower from Chisel
code to Verilog. For more information, see the
FIRRTL GitHub
page.
Operation Definitions – Structure
firrtl.circuit
(::circt::firrtl::CircuitOp)
FIRRTL Circuit
Syntax:
operation ::= `firrtl.circuit` $name custom<CircuitOpAttrs>(attr-dict) $body
The “firrtl.circuit” operation represents an overall Verilog circuit, containing a list of modules.
Traits: InnerRefNamespace, IsolatedFromAbove, NoRegionArguments, NoTerminator, SingleBlock, SymbolTable
Attributes:
Attribute | MLIR Type | Description |
---|---|---|
name | ::mlir::StringAttr | string attribute |
annotations | ::mlir::ArrayAttr | Annotation array attribute |
firrtl.extmodule
(::circt::firrtl::FExtModuleOp)
FIRRTL external module
The “firrtl.extmodule” operation represents an external reference to a Verilog module, including a given name and a list of ports. LowerAnnotations can add RefType ports to it. Each RefType port must have a corresponding entry in the internalPaths attribute. The internalPaths attribute is used to represent opaque internal paths into the external module, to be used for generating XMRs. Each RefType port must be removed by LowerXMR pass.
Traits: HasParent
Interfaces: FModuleLike, HWModuleLike, OpAsmOpInterface, Symbol
Attributes:
Attribute | MLIR Type | Description |
---|---|---|
defname | ::mlir::StringAttr | string attribute |
parameters | ::mlir::ArrayAttr | parameter array attribute |
annotations | ::mlir::ArrayAttr | Annotation array attribute |
internalPaths | ::mlir::ArrayAttr | array attribute |
firrtl.memmodule
(::circt::firrtl::FMemModuleOp)
FIRRTL Generated Memory Module
The “firrtl.memmodule” operation represents an external reference to a memory module. See the “firrtl.mem” op for a deeper explantation of the parameters.
A “firrtl.mem” operation is typically lowered to this operation when they are not directly lowered to registers by the compiler.
Traits: HasParent
Interfaces: FModuleLike, HWModuleLike, OpAsmOpInterface, Symbol
Attributes:
Attribute | MLIR Type | Description |
---|---|---|
numReadPorts | ::mlir::IntegerAttr | 32-bit unsigned integer attribute |
numWritePorts | ::mlir::IntegerAttr | 32-bit unsigned integer attribute |
numReadWritePorts | ::mlir::IntegerAttr | 32-bit unsigned integer attribute |
dataWidth | ::mlir::IntegerAttr | 32-bit unsigned integer attribute |
maskBits | ::mlir::IntegerAttr | 32-bit unsigned integer attribute |
readLatency | ::mlir::IntegerAttr | 32-bit unsigned integer attribute |
writeLatency | ::mlir::IntegerAttr | 32-bit unsigned integer attribute |
depth | ::mlir::IntegerAttr | 64-bit unsigned integer attribute |
extraPorts | ::mlir::ArrayAttr | array attribute |
annotations | ::mlir::ArrayAttr | Annotation array attribute |
firrtl.module
(::circt::firrtl::FModuleOp)
FIRRTL Module
The “firrtl.module” operation represents a Verilog module, including a given name, a list of ports, and a body that represents the connections within the module.
Traits: HasParent
Interfaces: FModuleLike, HWModuleLike, OpAsmOpInterface, Symbol
Attributes:
Attribute | MLIR Type | Description |
---|---|---|
annotations | ::mlir::ArrayAttr | Annotation array attribute |
Operation Definitions – Declarations
firrtl.instance
(::circt::firrtl::InstanceOp)
Instantiate an instance of a module
This represents an instance of a module. The results are the modules inputs and outputs. The inputs have flip type, the outputs do not.
Examples:
%0 = firrtl.instance foo @Foo(in io: !firrtl.uint)
Traits: HasParent<firrtl::FModuleOp, firrtl::WhenOp>
Interfaces: FNamableOp, HWInstanceLike, HasCustomSSAName, InnerSymbol, SymbolUserOpInterface
Attributes:
Attribute | MLIR Type | Description |
---|---|---|
moduleName | ::mlir::FlatSymbolRefAttr | flat symbol reference attribute |
name | ::mlir::StringAttr | string attribute |
nameKind | ::circt::firrtl::NameKindEnumAttr | name kind |
portDirections | ::mlir::IntegerAttr | arbitrary integer attribute |
portNames | ::mlir::ArrayAttr | string array attribute |
annotations | ::mlir::ArrayAttr | Annotation array attribute |
portAnnotations | ::mlir::ArrayAttr | Port annotations attribute |
lowerToBind | ::mlir::UnitAttr | unit attribute |
inner_sym | ::circt::hw::InnerSymAttr | Inner symbol definition |
Results:
Result | Description |
---|---|
results | any type |
firrtl.mem
(::circt::firrtl::MemOp)
Define a new mem
Syntax:
operation ::= `firrtl.mem` (`sym` $inner_sym^)? custom<NameKind>($nameKind)
$ruw custom<MemOp>(attr-dict) `:` qualified(type($results))
Interfaces: FNamableOp, HasCustomSSAName, InnerSymbol
Attributes:
Attribute | MLIR Type | Description |
---|---|---|
readLatency | ::mlir::IntegerAttr | 32-bit signless integer attribute whose minimum value is 0 |
writeLatency | ::mlir::IntegerAttr | 32-bit signless integer attribute whose minimum value is 1 |
depth | ::mlir::IntegerAttr | 64-bit signless integer attribute whose minimum value is 1 |
ruw | ::RUWAttrAttr | Read Under Write Enum |
portNames | ::mlir::ArrayAttr | string array attribute |
name | ::mlir::StringAttr | string attribute |
nameKind | ::circt::firrtl::NameKindEnumAttr | name kind |
annotations | ::mlir::ArrayAttr | Annotation array attribute |
portAnnotations | ::mlir::ArrayAttr | Port annotations attribute |
inner_sym | ::circt::hw::InnerSymAttr | Inner symbol definition |
groupID | ::mlir::IntegerAttr | 32-bit unsigned integer attribute |
Results:
Result | Description |
---|---|
results | FIRRTLType |
firrtl.node
(::circt::firrtl::NodeOp)
No-op to name a value
Syntax:
operation ::= `firrtl.node` (`sym` $inner_sym^)? custom<NameKind>($nameKind)
$input custom<ImplicitSSAName>(attr-dict) `:` qualified(type($input))
A node is simply a named intermediate value in a circuit. The node must be initialized to a value with a passive type and cannot be connected to. Nodes are often used to split a complicated compound expression into named subexpressions.
%result = firrtl.node %input : t1
Traits: SameOperandsAndResultType
Interfaces: FNamableOp, HasCustomSSAName, InferTypeOpInterface, InnerSymbol
Attributes:
Attribute | MLIR Type | Description |
---|---|---|
name | ::mlir::StringAttr | string attribute |
nameKind | ::circt::firrtl::NameKindEnumAttr | name kind |
annotations | ::mlir::ArrayAttr | Annotation array attribute |
inner_sym | ::circt::hw::InnerSymAttr | Inner symbol definition |
Operands:
Operand | Description |
---|---|
input | a passive base type (contain no flips) |
Results:
Result | Description |
---|---|
result | a base type |
firrtl.reg
(::circt::firrtl::RegOp)
Define a new register
Syntax:
operation ::= `firrtl.reg` (`sym` $inner_sym^)? custom<NameKind>($nameKind)
operands custom<ImplicitSSAName>(attr-dict) `:` qualified(type($result))
Declare a new register:
%name = firrtl.reg %clockVal : t1
Interfaces: FNamableOp, HasCustomSSAName, InnerSymbol
Attributes:
Attribute | MLIR Type | Description |
---|---|---|
name | ::mlir::StringAttr | string attribute |
nameKind | ::circt::firrtl::NameKindEnumAttr | name kind |
annotations | ::mlir::ArrayAttr | Annotation array attribute |
inner_sym | ::circt::hw::InnerSymAttr | Inner symbol definition |
Operands:
Operand | Description |
---|---|
clockVal | clock |
Results:
Result | Description |
---|---|
result | a passive base type that does not contain analog |
firrtl.regreset
(::circt::firrtl::RegResetOp)
Define a new register with a reset
Syntax:
operation ::= `firrtl.regreset` (`sym` $inner_sym^)? custom<NameKind>($nameKind)
operands custom<ImplicitSSAName>(attr-dict)
`:` qualified(type($resetSignal)) `,` qualified(type($resetValue)) `,` qualified(type($result))
Declare a new register:
%name = firrtl.regreset %clockVal, %resetSignal, %resetValue : t1
Interfaces: FNamableOp, HasCustomSSAName, InnerSymbol
Attributes:
Attribute | MLIR Type | Description |
---|---|---|
name | ::mlir::StringAttr | string attribute |
nameKind | ::circt::firrtl::NameKindEnumAttr | name kind |
annotations | ::mlir::ArrayAttr | Annotation array attribute |
inner_sym | ::circt::hw::InnerSymAttr | Inner symbol definition |
Operands:
Operand | Description |
---|---|
clockVal | clock |
resetSignal | Reset |
resetValue | a passive base type that does not contain analog |
Results:
Result | Description |
---|---|
result | a passive base type that does not contain analog |
firrtl.wire
(::circt::firrtl::WireOp)
Define a new wire
Syntax:
operation ::= `firrtl.wire` (`sym` $inner_sym^)? custom<NameKind>($nameKind)
custom<ImplicitSSAName>(attr-dict) `:` qualified(type($result))
Declare a new wire:
%name = firrtl.wire : t1
Interfaces: FNamableOp, HasCustomSSAName, InnerSymbol
Attributes:
Attribute | MLIR Type | Description |
---|---|---|
name | ::mlir::StringAttr | string attribute |
nameKind | ::circt::firrtl::NameKindEnumAttr | name kind |
annotations | ::mlir::ArrayAttr | Annotation array attribute |
inner_sym | ::circt::hw::InnerSymAttr | Inner symbol definition |
Results:
Result | Description |
---|---|
result | any type |
Statement Operation – Statements
firrtl.assert
(::circt::firrtl::AssertOp)
Assert Verification Statement
Syntax:
operation ::= `firrtl.assert` $clock `,` $predicate `,` $enable `,`
$message (`(` $substitutions^ `)` `:` qualified(type($substitutions)))?
custom<VerifAttrs>(attr-dict)
Attributes:
Attribute | MLIR Type | Description |
---|---|---|
message | ::mlir::StringAttr | string attribute |
name | ::mlir::StringAttr | string attribute |
isConcurrent | ::mlir::BoolAttr | bool attribute |
eventControl | ::EventControlAttr | edge control trigger |
Operands:
Operand | Description |
---|---|
clock | clock |
predicate | UInt<1> or UInt |
enable | UInt<1> or UInt |
substitutions | any type |
firrtl.assume
(::circt::firrtl::AssumeOp)
Assume Verification Statement
Syntax:
operation ::= `firrtl.assume` $clock `,` $predicate `,` $enable `,`
$message (`(` $substitutions^ `)` `:` qualified(type($substitutions)))?
custom<VerifAttrs>(attr-dict)
Attributes:
Attribute | MLIR Type | Description |
---|---|---|
message | ::mlir::StringAttr | string attribute |
name | ::mlir::StringAttr | string attribute |
isConcurrent | ::mlir::BoolAttr | bool attribute |
eventControl | ::EventControlAttr | edge control trigger |
Operands:
Operand | Description |
---|---|
clock | clock |
predicate | UInt<1> or UInt |
enable | UInt<1> or UInt |
substitutions | any type |
firrtl.attach
(::circt::firrtl::AttachOp)
Analog Attach Statement
Syntax:
operation ::= `firrtl.attach` $attached attr-dict `:` qualified(type($attached))
Operands:
Operand | Description |
---|---|
attached | analog type |
firrtl.connect
(::circt::firrtl::ConnectOp)
Connect two signals
Syntax:
operation ::= `firrtl.connect` $dest `,` $src attr-dict `:` qualified(type($dest)) `,` qualified(type($src))
Connect Operation:
firrtl.connect %dest, %src : t1, t2
Interfaces: FConnectLike
Operands:
Operand | Description |
---|---|
dest | a connectable type (base or ref type) |
src | a connectable type (base or ref type) |
firrtl.cover
(::circt::firrtl::CoverOp)
Cover Verification Statement
Syntax:
operation ::= `firrtl.cover` $clock `,` $predicate `,` $enable `,`
$message (`(` $substitutions^ `)` `:` qualified(type($substitutions)))?
custom<VerifAttrs>(attr-dict)
Attributes:
Attribute | MLIR Type | Description |
---|---|---|
message | ::mlir::StringAttr | string attribute |
name | ::mlir::StringAttr | string attribute |
isConcurrent | ::mlir::BoolAttr | bool attribute |
eventControl | ::EventControlAttr | edge control trigger |
Operands:
Operand | Description |
---|---|
clock | clock |
predicate | UInt<1> or UInt |
enable | UInt<1> or UInt |
substitutions | any type |
firrtl.force
(::circt::firrtl::ForceOp)
Force procedural statement
Syntax:
operation ::= `firrtl.force` $dest `,` $src attr-dict `:` qualified(type($dest)) `,` qualified(type($src))
Maps to the corresponding sv.force
operation.
Traits: SameTypeOperands
Operands:
Operand | Description |
---|---|
dest | a base type |
src | a base type |
firrtl.printf
(::circt::firrtl::PrintFOp)
Formatted Print Statement
Syntax:
operation ::= `firrtl.printf` $clock `,` $cond `,` $formatString custom<PrintfAttrs>(attr-dict)
(`(` $substitutions^ `)` `:` qualified(type($substitutions)))?
Attributes:
Attribute | MLIR Type | Description |
---|---|---|
formatString | ::mlir::StringAttr | string attribute |
name | ::mlir::StringAttr | string attribute |
Operands:
Operand | Description |
---|---|
clock | clock |
cond | UInt<1> or UInt |
substitutions | a base type |
firrtl.probe
(::circt::firrtl::ProbeOp)
FIRRTL Value Probe
Syntax:
operation ::= `firrtl.probe` $inner_sym attr-dict ( `,` $captured^ `:` qualified(type($captured)))?
Captures values without binding to any accidental name.
Attributes:
Attribute | MLIR Type | Description |
---|---|---|
inner_sym | ::mlir::StringAttr | string attribute |
Operands:
Operand | Description |
---|---|
captured | a base type |
firrtl.skip
(::circt::firrtl::SkipOp)
Skip statement
Syntax:
operation ::= `firrtl.skip` attr-dict
Skip Statement:
%firrtl.skip
This is a no-op statement.
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
firrtl.stop
(::circt::firrtl::StopOp)
Stop Statement
Syntax:
operation ::= `firrtl.stop` $clock `,` $cond `,` $exitCode custom<StopAttrs>(attr-dict)
Attributes:
Attribute | MLIR Type | Description |
---|---|---|
exitCode | ::mlir::IntegerAttr | 32-bit signless integer attribute |
name | ::mlir::StringAttr | string attribute |
Operands:
Operand | Description |
---|---|
clock | clock |
cond | UInt<1> or UInt |
firrtl.strictconnect
(::circt::firrtl::StrictConnectOp)
Connect two signals
Syntax:
operation ::= `firrtl.strictconnect` $dest `,` $src attr-dict `:` qualified(type($dest))
Connect two values with strict constraints:
firrtl.strictconnect %dest, %src : t1
Traits: SameTypeOperands
Interfaces: FConnectLike
Operands:
Operand | Description |
---|---|
dest | a sized base or ref type (contains no uninferred widths) or foreign type |
src | a sized base or ref type (contains no uninferred widths) or foreign type |
firrtl.when
(::circt::firrtl::WhenOp)
When Statement
Syntax:
operation ::= `firrtl.when` $condition $thenRegion (`else` $elseRegion^)? attr-dict-with-keyword
The “firrtl.when” operation represents a conditional. Connections within a conditional statement that connect to previously declared components hold only when the given condition is high. The condition must have a 1-bit unsigned integer type.
Traits: NoRegionArguments, NoTerminator, RecursiveMemoryEffects, RecursivelySpeculatableImplTrait, SingleBlock
Interfaces: ConditionallySpeculatable
Operands:
Operand | Description |
---|---|
condition | UInt<1> or UInt |
Operation Definitions – Expressions
firrtl.add
(::circt::firrtl::AddPrimOp)
Syntax:
operation ::= `firrtl.add` $lhs `,` $rhs attr-dict `:`
`(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))
Traits: AlwaysSpeculatableImplTrait, Commutative, SameOperandsIntTypeKind
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
lhs | sint or uint type |
rhs | sint or uint type |
Results:
Result | Description |
---|---|
result | sint or uint type |
firrtl.aggregateconstant
(::circt::firrtl::AggregateConstantOp)
Produce a constant of a passive aggregate value
Syntax:
operation ::= `firrtl.aggregateconstant` $fields attr-dict `:` type($result)
The constant operation produces a constant value of an aggregate type. The type must be passive. Clock and reset values are supported. For nested aggregates, embedded arrays are used.
%result = firrtl.aggregateconstant [1, 2, 3] : !firrtl.bundle<a: uint<8>, b: uint<5>, c: uint<4>>
%result = firrtl.aggregateconstant [1, 2, 3] : !firrtl.vector<uint<8>, 3>
%result = firrtl.aggregateconstant [[1, 2], [3, 5]] : !firrtl.vector<!firrtl.bundle<a: uint<8>, b: uint<5>>, 2>
Traits: AlwaysSpeculatableImplTrait, ConstantLike
Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Attributes:
Attribute | MLIR Type | Description |
---|---|---|
fields | ::mlir::ArrayAttr | array attribute |
Results:
Result | Description |
---|---|
result | a aggregate type |
firrtl.and
(::circt::firrtl::AndPrimOp)
Syntax:
operation ::= `firrtl.and` $lhs `,` $rhs attr-dict `:`
`(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))
Traits: AlwaysSpeculatableImplTrait, Commutative, SameOperandsIntTypeKind
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
lhs | sint or uint type |
rhs | sint or uint type |
Results:
Result | Description |
---|---|
result | uint type |
firrtl.andr
(::circt::firrtl::AndRPrimOp)
Syntax:
operation ::= `firrtl.andr` $input attr-dict `:` functional-type($input, $result)
Horizontally reduce a value to one bit, using the ‘and’ operation to merge
bits. andr(x)
is equivalent to concat(x, 1b1) == ~0
. As such, it
returns 1 for zero-bit-wide operands.
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
input | sint or uint type |
Results:
Result | Description |
---|---|
result | UInt<1> or UInt |
firrtl.asAsyncReset
(::circt::firrtl::AsAsyncResetPrimOp)
Syntax:
operation ::= `firrtl.asAsyncReset` $input attr-dict `:` functional-type($input, $result)
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
input | 1-bit uint/sint/analog, reset, asyncreset, or clock |
Results:
Result | Description |
---|---|
result | AsyncReset |
firrtl.asClock
(::circt::firrtl::AsClockPrimOp)
Syntax:
operation ::= `firrtl.asClock` $input attr-dict `:` functional-type($input, $result)
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
input | 1-bit uint/sint/analog, reset, asyncreset, or clock |
Results:
Result | Description |
---|---|
result | clock |
firrtl.asSInt
(::circt::firrtl::AsSIntPrimOp)
Syntax:
operation ::= `firrtl.asSInt` $input attr-dict `:` functional-type($input, $result)
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
input | a base type |
Results:
Result | Description |
---|---|
result | sint type |
firrtl.asUInt
(::circt::firrtl::AsUIntPrimOp)
Syntax:
operation ::= `firrtl.asUInt` $input attr-dict `:` functional-type($input, $result)
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
input | a base type |
Results:
Result | Description |
---|---|
result | uint type |
firrtl.bitcast
(::circt::firrtl::BitCastOp)
Reinterpret one value to another value of the same size and
potentially different type. This op is lowered to hw::BitCastOp.
Syntax:
operation ::= `firrtl.bitcast` $input attr-dict `:` functional-type($input, $result)
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
input | a base type |
Results:
Result | Description |
---|---|
result | a base type |
firrtl.bits
(::circt::firrtl::BitsPrimOp)
Syntax:
operation ::= `firrtl.bits` $input $hi `to` $lo attr-dict `:` functional-type($input, $result)
The bits
operation extracts the bits between hi
(inclusive) and lo
(inclusive) from input
. hi
must be greater than or equal to lo
. Both
hi
and lo
must be non-negative and less than the bit width of input
.
The result is hi - lo + 1
bits wide.
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Attributes:
Attribute | MLIR Type | Description |
---|---|---|
hi | ::mlir::IntegerAttr | 32-bit signless integer attribute |
lo | ::mlir::IntegerAttr | 32-bit signless integer attribute |
Operands:
Operand | Description |
---|---|
input | sint or uint type |
Results:
Result | Description |
---|---|
result | uint type |
firrtl.bundlecreate
(::circt::firrtl::BundleCreateOp)
Produce a bundle value
Syntax:
operation ::= `firrtl.bundlecreate` $fields attr-dict `:` functional-type($fields, $result)
Create an bundle from component values. This is equivalent in terms of flow to creating a node.
%result = firrtl.bundlecreate %1, %2, %3 : !firrtl.bundle<a: uint<8>, b: uint<5>, c: uint<4>>
Operands:
Operand | Description |
---|---|
fields | a base type |
Results:
Result | Description |
---|---|
result | BundleType |
firrtl.cat
(::circt::firrtl::CatPrimOp)
Syntax:
operation ::= `firrtl.cat` $lhs `,` $rhs attr-dict `:`
`(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))
Traits: AlwaysSpeculatableImplTrait, SameOperandsIntTypeKind
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
lhs | sint or uint type |
rhs | sint or uint type |
Results:
Result | Description |
---|---|
result | uint type |
firrtl.constant
(::circt::firrtl::ConstantOp)
Produce a constant value
The constant operation produces a constant value of SInt or UInt type, it never produces a zero bit wide result.
%result = firrtl.constant 42 : t1
Traits: AlwaysSpeculatableImplTrait, ConstantLike, FirstAttrDerivedResultType
Interfaces: ConditionallySpeculatable, HasCustomSSAName, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Attributes:
Attribute | MLIR Type | Description |
---|---|---|
value | ::mlir::IntegerAttr | arbitrary integer attribute with sign |
Results:
Result | Description |
---|---|
result | sint or uint type |
firrtl.cvt
(::circt::firrtl::CvtPrimOp)
Syntax:
operation ::= `firrtl.cvt` $input attr-dict `:` functional-type($input, $result)
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
input | sint or uint type |
Results:
Result | Description |
---|---|
result | sint type |
firrtl.dshl
(::circt::firrtl::DShlPrimOp)
Syntax:
operation ::= `firrtl.dshl` $lhs `,` $rhs attr-dict `:`
`(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))
A dynamic shift left operation. The width of $result
is expanded to
width($lhs) + 1 << width($rhs) - 1
.
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
lhs | sint or uint type |
rhs | uint type |
Results:
Result | Description |
---|---|
result | sint or uint type |
firrtl.dshlw
(::circt::firrtl::DShlwPrimOp)
Syntax:
operation ::= `firrtl.dshlw` $lhs `,` $rhs attr-dict `:`
`(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))
A dynamic shift left operation same as ‘dshl’ but with different width rule.
The width of $result
is equal to $lhs
.
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
lhs | sint or uint type |
rhs | uint type |
Results:
Result | Description |
---|---|
result | sint or uint type |
firrtl.dshr
(::circt::firrtl::DShrPrimOp)
Syntax:
operation ::= `firrtl.dshr` $lhs `,` $rhs attr-dict `:`
`(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
lhs | sint or uint type |
rhs | uint type |
Results:
Result | Description |
---|---|
result | sint or uint type |
firrtl.div
(::circt::firrtl::DivPrimOp)
Syntax:
operation ::= `firrtl.div` $lhs `,` $rhs attr-dict `:`
`(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))
Divides the first argument (the numerator) by the second argument (the denominator) truncating the result (rounding towards zero).
If the denominator is zero, the result is undefined.
The compiler may optimize this undefined behavior in any way it
wants. Notably div(a, a)
will be optimized to 1
. This may cause
erroneous formal equivalence mismatches between unoptimized and
optimized FIRRTL dialects that are separately converted to Verilog.
Traits: AlwaysSpeculatableImplTrait, SameOperandsIntTypeKind
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
lhs | sint or uint type |
rhs | sint or uint type |
Results:
Result | Description |
---|---|
result | sint or uint type |
firrtl.eq
(::circt::firrtl::EQPrimOp)
Syntax:
operation ::= `firrtl.eq` $lhs `,` $rhs attr-dict `:`
`(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))
Traits: AlwaysSpeculatableImplTrait, Commutative, SameOperandsIntTypeKind
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
lhs | sint or uint type |
rhs | sint or uint type |
Results:
Result | Description |
---|---|
result | UInt<1> or UInt |
firrtl.geq
(::circt::firrtl::GEQPrimOp)
Syntax:
operation ::= `firrtl.geq` $lhs `,` $rhs attr-dict `:`
`(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))
Traits: AlwaysSpeculatableImplTrait, SameOperandsIntTypeKind
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
lhs | sint or uint type |
rhs | sint or uint type |
Results:
Result | Description |
---|---|
result | UInt<1> or UInt |
firrtl.gt
(::circt::firrtl::GTPrimOp)
Syntax:
operation ::= `firrtl.gt` $lhs `,` $rhs attr-dict `:`
`(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))
Traits: AlwaysSpeculatableImplTrait, SameOperandsIntTypeKind
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
lhs | sint or uint type |
rhs | sint or uint type |
Results:
Result | Description |
---|---|
result | UInt<1> or UInt |
firrtl.hwStructCast
(::circt::firrtl::HWStructCastOp)
Syntax:
operation ::= `firrtl.hwStructCast` $input attr-dict `:` functional-type($input, $result)
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
input | any type |
Results:
Result | Description |
---|---|
result | any type |
firrtl.head
(::circt::firrtl::HeadPrimOp)
Syntax:
operation ::= `firrtl.head` $input `,` $amount attr-dict `:` functional-type($input, $result)
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Attributes:
Attribute | MLIR Type | Description |
---|---|---|
amount | ::mlir::IntegerAttr | 32-bit signless integer attribute |
Operands:
Operand | Description |
---|---|
input | sint or uint type |
Results:
Result | Description |
---|---|
result | uint type |
firrtl.invalidvalue
(::circt::firrtl::InvalidValueOp)
InvalidValue primitive
Syntax:
operation ::= `firrtl.invalidvalue` attr-dict `:` qualified(type($result))
The InvalidValue operation returns an invalid value of a specified type:
%result = firrtl.invalid : !firrtl.uint<1>
This corresponds to the FIRRTL invalidate operation without the implicit connect semantics. Each invalid op produces a unique invalid value. InvalidOp is not constant-like
Interfaces: HasCustomSSAName, MemoryEffectOpInterface (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{MemoryEffects::Allocate on ::mlir::SideEffects::DefaultResource}
Results:
Result | Description |
---|---|
result | a base type |
firrtl.int.isX
(::circt::firrtl::IsXIntrinsicOp)
Test for ‘x
Syntax:
operation ::= `firrtl.int.isX` $arg attr-dict `:` type($arg)
The int.isX
expression checks that the operand is not a verilog literal
‘x. FIRRTL doesn’t have a notion of ‘x per-se, but x can come in to the
system from external modules and from SV constructs. Verification
constructs need to explicitly test for ‘x.
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
arg | a base type |
Results:
Result | Description |
---|---|
result | UInt<1> or UInt |
firrtl.leq
(::circt::firrtl::LEQPrimOp)
Syntax:
operation ::= `firrtl.leq` $lhs `,` $rhs attr-dict `:`
`(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))
Traits: AlwaysSpeculatableImplTrait, SameOperandsIntTypeKind
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
lhs | sint or uint type |
rhs | sint or uint type |
Results:
Result | Description |
---|---|
result | UInt<1> or UInt |
firrtl.lt
(::circt::firrtl::LTPrimOp)
Syntax:
operation ::= `firrtl.lt` $lhs `,` $rhs attr-dict `:`
`(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))
Traits: AlwaysSpeculatableImplTrait, SameOperandsIntTypeKind
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
lhs | sint or uint type |
rhs | sint or uint type |
Results:
Result | Description |
---|---|
result | UInt<1> or UInt |
firrtl.mul
(::circt::firrtl::MulPrimOp)
Syntax:
operation ::= `firrtl.mul` $lhs `,` $rhs attr-dict `:`
`(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))
Traits: AlwaysSpeculatableImplTrait, Commutative, SameOperandsIntTypeKind
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
lhs | sint or uint type |
rhs | sint or uint type |
Results:
Result | Description |
---|---|
result | sint or uint type |
firrtl.multibit_mux
(::circt::firrtl::MultibitMuxOp)
Multibit multiplexer
The multibit mux expression dynamically selects operands. The index must be an expression with an unsigned integer type.
%result = firrtl.multibit_mux %index,
%v_{n-1}, ..., %v_2, %v_1, %v_0 : t1, t2
The order of operands is defined in the same way as hw dialect.
For the example above, if %index
is 0, then the value is %v_0
.
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
index | uint type |
inputs | a base type |
Results:
Result | Description |
---|---|
result | a base type |
firrtl.mux
(::circt::firrtl::MuxPrimOp)
Syntax:
operation ::= `firrtl.mux` `(` operands `)` attr-dict `:` functional-type(operands, $result)
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
sel | UInt<1> or UInt |
high | a passive base type (contain no flips) |
low | a passive base type (contain no flips) |
Results:
Result | Description |
---|---|
result | a passive base type (contain no flips) |
firrtl.neq
(::circt::firrtl::NEQPrimOp)
Syntax:
operation ::= `firrtl.neq` $lhs `,` $rhs attr-dict `:`
`(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))
Traits: AlwaysSpeculatableImplTrait, Commutative, SameOperandsIntTypeKind
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
lhs | sint or uint type |
rhs | sint or uint type |
Results:
Result | Description |
---|---|
result | UInt<1> or UInt |
firrtl.neg
(::circt::firrtl::NegPrimOp)
Syntax:
operation ::= `firrtl.neg` $input attr-dict `:` functional-type($input, $result)
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
input | sint or uint type |
Results:
Result | Description |
---|---|
result | sint type |
firrtl.not
(::circt::firrtl::NotPrimOp)
Syntax:
operation ::= `firrtl.not` $input attr-dict `:` functional-type($input, $result)
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
input | sint or uint type |
Results:
Result | Description |
---|---|
result | uint type |
firrtl.or
(::circt::firrtl::OrPrimOp)
Syntax:
operation ::= `firrtl.or` $lhs `,` $rhs attr-dict `:`
`(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))
Traits: AlwaysSpeculatableImplTrait, Commutative, SameOperandsIntTypeKind
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
lhs | sint or uint type |
rhs | sint or uint type |
Results:
Result | Description |
---|---|
result | uint type |
firrtl.orr
(::circt::firrtl::OrRPrimOp)
Syntax:
operation ::= `firrtl.orr` $input attr-dict `:` functional-type($input, $result)
Horizontally reduce a value to one bit, using the ‘or’ operation to merge
bits. orr(x)
is equivalent to concat(x, 1b0) != 0
. As such, it
returns 0 for zero-bit-wide operands.
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
input | sint or uint type |
Results:
Result | Description |
---|---|
result | UInt<1> or UInt |
firrtl.pad
(::circt::firrtl::PadPrimOp)
Syntax:
operation ::= `firrtl.pad` $input `,` $amount attr-dict `:` functional-type($input, $result)
Pad the input out to an amount
wide integer, sign extending or zero
extending according to input
s type. If amount
is less than the existing
width of input
, then input is unmodified.
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Attributes:
Attribute | MLIR Type | Description |
---|---|---|
amount | ::mlir::IntegerAttr | 32-bit signless integer attribute |
Operands:
Operand | Description |
---|---|
input | sint or uint type |
Results:
Result | Description |
---|---|
result | sint or uint type |
firrtl.int.plusargs.test
(::circt::firrtl::PlusArgsTestIntrinsicOp)
SystemVerilog $test$plusargs
call
Syntax:
operation ::= `firrtl.int.plusargs.test` $formatString attr-dict
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Attributes:
Attribute | MLIR Type | Description |
---|---|---|
formatString | ::mlir::StringAttr | string attribute |
Results:
Result | Description |
---|---|
found | UInt<1> or UInt |
firrtl.int.plusargs.value
(::circt::firrtl::PlusArgsValueIntrinsicOp)
SystemVerilog $value$plusargs
call
Syntax:
operation ::= `firrtl.int.plusargs.value` $formatString attr-dict `:` type($result)
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, HasCustomSSAName, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Attributes:
Attribute | MLIR Type | Description |
---|---|---|
formatString | ::mlir::StringAttr | string attribute |
Results:
Result | Description |
---|---|
found | UInt<1> or UInt |
result | any type |
firrtl.ref.resolve
(::circt::firrtl::RefResolveOp)
FIRRTL Resolve a Reference
Syntax:
operation ::= `firrtl.ref.resolve` $ref attr-dict `:` qualified(type($ref))
Resolve a remote reference for reading a remote value. It takes a RefType input and returns the corresponding BaseType value. If an XMR is emitted for this reference, it will be at the location of this operation.
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
ref | reference type |
Results:
Result | Description |
---|---|
result | a base type |
firrtl.ref.send
(::circt::firrtl::RefSendOp)
FIRRTL Send through Reference
Syntax:
operation ::= `firrtl.ref.send` $base attr-dict `:` qualified(type($base))
Endpoint of a remote reference. Send a value through a reference to be read from the firrtl.ref.resolve op. It takes a BaseType input and returns the corresponding RefType value.
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
base | a base type |
Results:
Result | Description |
---|---|
result | reference type |
firrtl.ref.sub
(::circt::firrtl::RefSubOp)
Extract an element of an aggregate RefType value
Syntax:
operation ::= `firrtl.ref.sub` $input `[` $index `]` attr-dict `:` qualified(type($input))
The refsub expression statically refers, by index, to a sub-element of an expression with a RefType. The index must be a non-negative integer and cannot be equal to or exceed the underlying vector size or number of elements in bundle.
%result = firrtl.ref.sub %input[index] : t1
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Attributes:
Attribute | MLIR Type | Description |
---|---|---|
index | ::mlir::IntegerAttr | 32-bit signless integer attribute |
Operands:
Operand | Description |
---|---|
input | reference type |
Results:
Result | Description |
---|---|
result | reference type |
firrtl.rem
(::circt::firrtl::RemPrimOp)
Syntax:
operation ::= `firrtl.rem` $lhs `,` $rhs attr-dict `:`
`(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))
Traits: AlwaysSpeculatableImplTrait, SameOperandsIntTypeKind
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
lhs | sint or uint type |
rhs | sint or uint type |
Results:
Result | Description |
---|---|
result | sint or uint type |
firrtl.shl
(::circt::firrtl::ShlPrimOp)
Syntax:
operation ::= `firrtl.shl` $input `,` $amount attr-dict `:` functional-type($input, $result)
The shl
operation concatenates amount
zero bits to the least significant
end of input
. amount
must be non-negative.
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Attributes:
Attribute | MLIR Type | Description |
---|---|---|
amount | ::mlir::IntegerAttr | 32-bit signless integer attribute |
Operands:
Operand | Description |
---|---|
input | sint or uint type |
Results:
Result | Description |
---|---|
result | sint or uint type |
firrtl.shr
(::circt::firrtl::ShrPrimOp)
Syntax:
operation ::= `firrtl.shr` $input `,` $amount attr-dict `:` functional-type($input, $result)
The shr
operation truncates least significant amount
bits from input
.
If amount
is greater than of equal to width(input)
, the value will be
zero for unsigned types and the sign bit for signed types. amount
must be
non-negative.
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Attributes:
Attribute | MLIR Type | Description |
---|---|---|
amount | ::mlir::IntegerAttr | 32-bit signless integer attribute |
Operands:
Operand | Description |
---|---|
input | sint or uint type |
Results:
Result | Description |
---|---|
result | sint or uint type |
firrtl.int.sizeof
(::circt::firrtl::SizeOfIntrinsicOp)
Syntax:
operation ::= `firrtl.int.sizeof` $input attr-dict `:` functional-type($input, $result)
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
input | a base type |
Results:
Result | Description |
---|---|
result | UInt<32> |
firrtl.specialconstant
(::circt::firrtl::SpecialConstantOp)
Produce a constant Reset or Clock value
The constant operation produces a constant value of Reset, AsyncReset, or Clock type. The value can only be 0 or 1.
%result = firrtl.specialconstant 1 : !firrtl.clock
Traits: AlwaysSpeculatableImplTrait, ConstantLike
Interfaces: ConditionallySpeculatable, HasCustomSSAName, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Attributes:
Attribute | MLIR Type | Description |
---|---|---|
value | ::mlir::BoolAttr | bool attribute |
Results:
Result | Description |
---|---|
result | clock or Reset or AsyncReset |
firrtl.sub
(::circt::firrtl::SubPrimOp)
Syntax:
operation ::= `firrtl.sub` $lhs `,` $rhs attr-dict `:`
`(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))
Traits: AlwaysSpeculatableImplTrait, SameOperandsIntTypeKind
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
lhs | sint or uint type |
rhs | sint or uint type |
Results:
Result | Description |
---|---|
result | sint or uint type |
firrtl.subaccess
(::circt::firrtl::SubaccessOp)
Extract a dynamic element of a vector value
Syntax:
operation ::= `firrtl.subaccess` $input `[` $index `]` attr-dict `:` qualified(type($input)) `,` qualified(type($index))
The subaccess expression dynamically refers to a subelement of a vector-typed expression using a calculated index. The index must be an expression with an unsigned integer type.
%result = firrtl.subaccess %input[%idx] : t1, t2
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
input | a base type |
index | uint type |
Results:
Result | Description |
---|---|
result | a base type |
firrtl.subfield
(::circt::firrtl::SubfieldOp)
Extract a subfield of another value
The subfield expression refers to a subelement of an expression with a bundle type.
%result = firrtl.subfield %input[field-name] : !input-type
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Attributes:
Attribute | MLIR Type | Description |
---|---|---|
fieldIndex | ::mlir::IntegerAttr | 32-bit signless integer attribute |
Operands:
Operand | Description |
---|---|
input | BundleType |
Results:
Result | Description |
---|---|
result | a base type |
firrtl.subindex
(::circt::firrtl::SubindexOp)
Extract an element of a vector value
Syntax:
operation ::= `firrtl.subindex` $input `[` $index `]` attr-dict `:` qualified(type($input))
The subindex expression statically refers, by index, to a subelement of an expression with a vector type. The index must be a non-negative integer and cannot be equal to or exceed the length of the vector it indexes.
%result = firrtl.subindex %input[index] : t1
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Attributes:
Attribute | MLIR Type | Description |
---|---|---|
index | ::mlir::IntegerAttr | 32-bit signless integer attribute |
Operands:
Operand | Description |
---|---|
input | a base type |
Results:
Result | Description |
---|---|
result | a base type |
firrtl.tail
(::circt::firrtl::TailPrimOp)
Syntax:
operation ::= `firrtl.tail` $input `,` $amount attr-dict `:` functional-type($input, $result)
The tail
operation truncates the amount
most significant bits from
input
. amount
must be non-negative and less than or equal to the bit
width of e. The result is width(input)-amount
bits wide.
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Attributes:
Attribute | MLIR Type | Description |
---|---|---|
amount | ::mlir::IntegerAttr | 32-bit signless integer attribute |
Operands:
Operand | Description |
---|---|
input | sint or uint type |
Results:
Result | Description |
---|---|
result | uint type |
firrtl.vectorcreate
(::circt::firrtl::VectorCreateOp)
Produce a vector value
Syntax:
operation ::= `firrtl.vectorcreate` $fields attr-dict `:` functional-type($fields, $result)
Create a vector from component values. This is equivalent in terms of flow to creating a node. The first operand indicates 0-th element of the result.
%result = firrtl.vectorcreate %1, %2, %3 : !firrtl.vector<uint<8>, 3>
Operands:
Operand | Description |
---|---|
fields | a base type |
Results:
Result | Description |
---|---|
result | FVectorType |
firrtl.verbatim.expr
(::circt::firrtl::VerbatimExprOp)
Expression that expands to a value given SystemVerilog text
Syntax:
operation ::= `firrtl.verbatim.expr` $text (`(` $substitutions^ `)`)?
`:` functional-type($substitutions, $result) attr-dict
This operation produces a typed value expressed by a string of SystemVerilog. This can be used to access macros and other values that are only sensible as Verilog text.
The text string is expected to have the highest precedence, so you should
include parentheses in the string if it isn’t a single token. This is also
assumed to not have side effects (use sv.verbatim
if you need them).
firrtl.verbatim.expr
allows operand substitutions with {{0}}
syntax.
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, HasCustomSSAName, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Attributes:
Attribute | MLIR Type | Description |
---|---|---|
text | ::mlir::StringAttr | string attribute |
symbols | ::mlir::ArrayAttr | name reference array attribute |
Operands:
Operand | Description |
---|---|
substitutions | any type |
Results:
Result | Description |
---|---|
result | a base type |
firrtl.verbatim.wire
(::circt::firrtl::VerbatimWireOp)
Expression with wire semantics that expands to a value given SystemVerilog text
Syntax:
operation ::= `firrtl.verbatim.wire` $text (`(` $substitutions^ `)`)?
`:` functional-type($substitutions, $result) attr-dict
This operation produces a typed value with wire semantics, expressed by a string of SystemVerilog. This can be used to access macros and other values that are only sensible as Verilog text.
The text string is expected to have the highest precedence, so you should
include parentheses in the string if it isn’t a single token. This is also
assumed to not have side effects (use sv.verbatim
if you need them).
firrtl.verbatim.wire
allows operand substitutions with {{0}}
syntax.
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, HasCustomSSAName, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Attributes:
Attribute | MLIR Type | Description |
---|---|---|
text | ::mlir::StringAttr | string attribute |
symbols | ::mlir::ArrayAttr | name reference array attribute |
Operands:
Operand | Description |
---|---|
substitutions | any type |
Results:
Result | Description |
---|---|
result | a base type |
firrtl.xor
(::circt::firrtl::XorPrimOp)
Syntax:
operation ::= `firrtl.xor` $lhs `,` $rhs attr-dict `:`
`(` qualified(type($lhs)) `,` qualified(type($rhs)) `)` `->` qualified(type($result))
Traits: AlwaysSpeculatableImplTrait, Commutative, SameOperandsIntTypeKind
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
lhs | sint or uint type |
rhs | sint or uint type |
Results:
Result | Description |
---|---|
result | uint type |
firrtl.xorr
(::circt::firrtl::XorRPrimOp)
Syntax:
operation ::= `firrtl.xorr` $input attr-dict `:` functional-type($input, $result)
Horizontally reduce a value to one bit, using the ‘xor’ operation to merge
bits. xorr(x)
is equivalent to popcount(concat(x, 1b0)) & 1
. As
such, it returns 0 for zero-bit-wide operands.
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable, HasCustomSSAName, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands:
Operand | Description |
---|---|
input | sint or uint type |
Results:
Result | Description |
---|---|
result | UInt<1> or UInt |
Type Definitions
AnalogType
Analog signal
Parameters:
Parameter | C++ type | Description |
---|---|---|
widthOrSentinel | int32_t |
AsyncResetType
AsyncReset signal
BundleType
an aggregate of named elements. This is effectively a struct.
Parameters:
Parameter | C++ type | Description |
---|---|---|
elements | ArrayRef<BundleElement> |
ClockType
Clock signal
FVectorType
a fixed size collection of elements, like an array.
Parameters:
Parameter | C++ type | Description |
---|---|---|
elementType | FIRRTLBaseType | |
numElements | size_t |
ResetType
Reset Signal
SIntType
A signed integer type, whose width may not be known.
Parameters:
Parameter | C++ type | Description |
---|---|---|
widthOrSentinel | int32_t |
UIntType
An unsigned integer type, whose width may not be known.
Parameters:
Parameter | C++ type | Description |
---|---|---|
widthOrSentinel | int32_t |
Attribute Definitions
AugmentedBooleanTypeAttr
GrandCentral AugmentedBooleanType
Used in the GrandCentralPass.
Parameters:
Parameter | C++ type | Description |
---|---|---|
underlying | DictionaryAttr |
AugmentedBundleTypeAttr
GrandCentral AugmentedBundleType
Used in the GrandCentralPass.
Parameters:
Parameter | C++ type | Description |
---|---|---|
underlying | DictionaryAttr |
AugmentedDeletedTypeAttr
GrandCentral AugmentedDeletedType
Used in the GrandCentralPass.
Parameters:
Parameter | C++ type | Description |
---|---|---|
underlying | DictionaryAttr |
AugmentedDoubleTypeAttr
GrandCentral AugmentedDoubleType
Used in the GrandCentralPass.
Parameters:
Parameter | C++ type | Description |
---|---|---|
underlying | DictionaryAttr |
AugmentedGroundTypeAttr
GrandCentral AugmentedGroundType
Used in the GrandCentralPass.
Parameters:
Parameter | C++ type | Description |
---|---|---|
underlying | DictionaryAttr |
AugmentedIntegerTypeAttr
GrandCentral AugmentedIntegerType
Used in the GrandCentralPass.
Parameters:
Parameter | C++ type | Description |
---|---|---|
underlying | DictionaryAttr |
AugmentedLiteralTypeAttr
GrandCentral AugmentedLiteralType
Used in the GrandCentralPass.
Parameters:
Parameter | C++ type | Description |
---|---|---|
underlying | DictionaryAttr |
AugmentedStringTypeAttr
GrandCentral AugmentedStringType
Used in the GrandCentralPass.
Parameters:
Parameter | C++ type | Description |
---|---|---|
underlying | DictionaryAttr |
AugmentedVectorTypeAttr
GrandCentral AugmentedVectorType
Used in the GrandCentralPass.
Parameters:
Parameter | C++ type | Description |
---|---|---|
underlying | DictionaryAttr |
ParamDeclAttr
Module or instance parameter definition
An attribute describing a module parameter, or instance parameter specification.
Parameters:
Parameter | C++ type | Description |
---|---|---|
name | ::mlir::StringAttr | |
type | ::mlir::Type | |
value | ::mlir::Attribute |
FConnectLike (FConnectLike
)
Provide common connection information.
Methods:
getDest
Value getDest();
Return a destination of connection. NOTE: This method must be implemented by the user.
getSrc
Value getSrc();
Return a source of connection. NOTE: This method must be implemented by the user.
FModuleLike (FModuleLike
)
Provide common module information.
Methods:
moduleName
StringRef moduleName();
Get the module name
moduleNameAttr
StringAttr moduleNameAttr();
Get the module name
getPortDirectionsAttr
IntegerAttr getPortDirectionsAttr();
Get the port directions attribute NOTE: This method must be implemented by the user.
getPortDirections
APInt getPortDirections();
Get the port directions NOTE: This method must be implemented by the user.
getPortDirection
Direction getPortDirection(size_t portIndex);
Get a port direction NOTE: This method must be implemented by the user.
getPortNamesAttr
ArrayAttr getPortNamesAttr();
Get the port names attribute NOTE: This method must be implemented by the user.
getPortNames
ArrayRef<Attribute> getPortNames();
Get the port names NOTE: This method must be implemented by the user.
getPortNameAttr
StringAttr getPortNameAttr(size_t portIndex);
Get a port name NOTE: This method must be implemented by the user.
getPortName
StringRef getPortName(size_t portIndex);
Get a port name NOTE: This method must be implemented by the user.
getPortTypesAttr
ArrayAttr getPortTypesAttr();
Get the port types attribute NOTE: This method must be implemented by the user.
getPortTypes
ArrayRef<Attribute> getPortTypes();
Get the port types NOTE: This method must be implemented by the user.
getPortTypeAttr
TypeAttr getPortTypeAttr(size_t portIndex);
Get a port type NOTE: This method must be implemented by the user.
getPortType
Type getPortType(size_t portIndex);
Get a port type NOTE: This method must be implemented by the user.
getPortAnnotationsAttr
ArrayAttr getPortAnnotationsAttr();
Get the port annotations attribute NOTE: This method must be implemented by the user.
getPortAnnotations
ArrayRef<Attribute> getPortAnnotations();
Get the port annotations attribute NOTE: This method must be implemented by the user.
getAnnotationsAttrForPort
ArrayAttr getAnnotationsAttrForPort(size_t portIndex);
Get a port’s annotations attribute NOTE: This method must be implemented by the user.
getAnnotationsForPort
ArrayRef<Attribute> getAnnotationsForPort(size_t portIndex);
Get a port’s annotations NOTE: This method must be implemented by the user.
getPortSymbolsAttr
ArrayAttr getPortSymbolsAttr();
Get the port symbols attribute NOTE: This method must be implemented by the user.
getPortSymbols
ArrayRef<Attribute> getPortSymbols();
Get the port symbols NOTE: This method must be implemented by the user.
hasPortSymbolAttr
bool hasPortSymbolAttr(size_t portIndex);
Check if port has symbol attribute NOTE: This method must be implemented by the user.
setPortSymbols
void setPortSymbols(ArrayRef<Attribute> symbols);
Set the port symbols NOTE: This method must be implemented by the user.
setPortSymbolAttr
void setPortSymbolAttr(size_t portIndex, StringAttr symbol);
Set a port symbol attribute NOTE: This method must be implemented by the user.
setPortSymbol
void setPortSymbol(size_t portIndex, StringRef symbol);
Set a port symbol NOTE: This method must be implemented by the user.
getPorts
SmallVector<PortInfo> getPorts();
Get information about all ports NOTE: This method must be implemented by the user.
insertPorts
void insertPorts(ArrayRef<std::pair<unsigned, PortInfo>> ports);
Inserts the given ports at the corresponding indices NOTE: This method must be implemented by the user.
erasePorts
void erasePorts(const llvm::BitVector&portIndices);
Erases the ports that have their corresponding bit set in portIndices
NOTE: This method must be implemented by the user.
FNamableOp (FNamableOp
)
The interface provides common methods for namable operations related to name preservation semantics.
Methods:
hasDroppableName
bool hasDroppableName();
Return true if the name is droppable. NOTE: This method must be implemented by the user.
dropName
void dropName();
Make the name droppable. NOTE: This method must be implemented by the user.
setNameKindAttr
void setNameKindAttr(firrtl::NameKindEnumAttr nameKind);
Set a namekind. NOTE: This method must be implemented by the user.
getNameAttr
mlir::StringAttr getNameAttr();
Return the name. NOTE: This method must be implemented by the user.
getName
llvm::StringRef getName();
Return the name. NOTE: This method must be implemented by the user.