Intrinsics

Intrinsics provide an implementation-specific way to extend the FIRRTL language with new operations.

Intrinsics are currently implemented as intmodule’s.

Motivation ¶

Intrinsics provide a way to add functionality to FIRRTL without having to extend the FIRRTL language. This allows a fast path for prototyping new operations to rapidly respond to output requirements. Intrinsics maintain strict definitions and type checking.

Supported Intrinsics ¶

circt_sizeof ¶

Returns the size of a type. The input port is not read from and may be any type, including uninferred types.

circt_isX ¶

Tests if the value is a literal x. FIRRTL doesn’t have a notion of ‘x per-se, but x can come in to the system from external modules and from SV constructs.
Verification constructs need to explicitly test for ‘x.

circt_plusargs_value ¶

Tests and extracts a value from simulator command line options with SystemVerilog $value$plusargs. This is described in SystemVerilog 2012 section 21.6.

We do not currently check that the format string substitution flag matches the type of the result.

circt_plusargs_test ¶

Tests simulator command line options with SystemVerilog $test$plusargs. This is described in SystemVerilog 2012 section 21.6.

circt_clock_gate ¶

Enables and disables a clock safely, without glitches, based on a boolean enable value. If the enable input is 1, the output clock produced by the clock gate is identical to the input clock. If the enable input is 0, the output clock is a constant zero.

The enable input is sampled at the rising edge of the input clock; any changes on the enable before or after that edge are ignored and do not affect the output clock.

circt_chisel_assert ¶

Generate a clocked SV assert statement, with optional formatted error message.

Example output:

wire _GEN = ~enable | cond;
assert__label: assert property (@(posedge clock) _GEN) else $error("message");

circt_chisel_ifelsefatal ¶

Generate a particular Verilog sequence that’s similar to an assertion.

Has legacy special behavior and should not be used by new code.

This intrinsic also accepts the label and guard parameters which are recorded but not used in the normal emission.

Example SV output:

`ifndef SYNTHESIS
  always @(posedge clock) begin
    if (enable & ~cond) begin
      if (`ASSERT_VERBOSE_COND_)
        $error("message");
      if (`STOP_COND_)
        $fatal;
    end
  end // always @(posedge)
`endif // not def SYNTHESIS

circt_chisel_assume ¶

Generate a clocked SV assume statement, with optional formatted error message.

Example SV output:

assume__label: assume property (@(posedge clock) ~enable | cond) else $error("message");	

circt_chisel_cover ¶

Generate a clocked SV cover statement.

Example SV output:

cover__label: cover property (@(posedge clock) enable & cond);

circt_unclocked_assume ¶

Generate a SV assume statement whose predicate is used in a sensitivity list of the enclosing always block.

Example SV output:

ifdef USE_FORMAL_ONLY_CONSTRAINTS
 `ifdef USE_UNR_ONLY_CONSTRAINTS
   wire _GEN = ~enable | pred;
   always @(edge _GEN)
     assume_label: assume(_GEN) else $error("Conditional compilation example for UNR-only and formal-only assert");
 `endif // USE_UNR_ONLY_CONSTRAINTS
endif // USE_FORMAL_ONLY_CONSTRAINTS