'moore' Dialect
This dialect provides operations and types to capture a SystemVerilog design after parsing, type checking, and elaboration.
Rationale ¶
The main goal of the moore
dialect is to provide a set of operations and types for the ImportVerilog
conversion to translate a fully parsed, type-checked, and elaborated Slang AST into MLIR operations. See IEEE 1800-2017 for more details about SystemVerilog. The dialect aims to faithfully capture the full SystemVerilog types and semantics, and provide a platform for transformation passes to resolve language quirks, analyze the design at a high level, and lower it to the core dialects.
In contrast, the sv
dialect is geared towards emission of SystemVerilog text, and is focused on providing a good lowering target to allow for emission. The moore
and sv
dialect may eventually converge into a single dialect. As we are building out the Verilog frontend capabilities of CIRCT it is valuable to have a separate ingestion dialect, such that we do not have to make disruptive changes to the load-bearing sv
dialect used in production.
Types ¶
Operations ¶
moore.ashr
(::circt::moore::AShrOp) ¶
Arithmetic right shift
Syntax:
operation ::= `moore.ashr` $value `,` $amount attr-dict `:` type($value) `,` type($amount)
Shifts the value
to the left or right by amount
number of bits. The
result has the same type as the input value. The amount is always treated as
an unsigned number and has no effect on the signedness of the result. X or
Z bits in the input value are simply shifted left or right the same way 0 or
1 bits are. If the amount contains X or Z bits, all result bits are X.
shl
shifts bits to the left, filling in 0 for the vacated least
significant bits. shr
and ashr
shift bits to the right; shr
fills in
0 for the vacated most significant bits, and ashr
copies the input’s sign
bit into the vacated most significant bits. Note that in contrast to the SV
spec, the ashr
always fills in the sign bit regardless of the signedness
of the input.
shl
corresponds to the <<
and <<<
operators. shr
corresponds to the
>>
operator, and the >>>
operator applied to an unsigned value. ashr
corresponds to the >>>
operator applied to a signed value.
See IEEE 1800-2017 § 11.4.10 “Shift operators”.
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable
, InferTypeOpInterface
, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
value | simple bit vector type |
amount | simple bit vector type |
Results: ¶
Result | Description |
---|---|
result | simple bit vector type |
moore.add
(::circt::moore::AddOp) ¶
Addition
Syntax:
operation ::= `moore.add` $lhs `,` $rhs attr-dict `:` type($result)
Add the operands. If any bit in the two operands is Z or X, all bits in the result are X.
See IEEE 1800-2017 § 11.4.3 “Arithmetic operators”.
Traits: AlwaysSpeculatableImplTrait
, Commutative
, SameOperandsAndResultType
Interfaces: ConditionallySpeculatable
, InferTypeOpInterface
, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
lhs | simple bit vector type |
rhs | simple bit vector type |
Results: ¶
Result | Description |
---|---|
result | simple bit vector type |
moore.and
(::circt::moore::AndOp) ¶
Bitwise AND operation
Syntax:
operation ::= `moore.and` $lhs `,` $rhs attr-dict `:` type($result)
Applies the boolean AND operation to each pair of corresponding bits in the
left- and right-hand side operand. Corresponds to the &
operator.
See IEEE 1800-2017 § 11.4.8 “Bitwise operators”.
0 | 1 | X | Z | |
---|---|---|---|---|
0 | 0 | 0 | 0 | 0 |
1 | 0 | 1 | X | X |
X | 0 | X | X | X |
Z | 0 | X | X | X |
Traits: AlwaysSpeculatableImplTrait
, Commutative
, SameOperandsAndResultType
Interfaces: ConditionallySpeculatable
, InferTypeOpInterface
, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
lhs | simple bit vector type |
rhs | simple bit vector type |
Results: ¶
Result | Description |
---|---|
result | simple bit vector type |
moore.blocking_assign
(::circt::moore::BlockingAssignOp) ¶
Blocking procedural assignment
Syntax:
operation ::= `moore.blocking_assign` $dst `,` $src attr-dict `:` type($src)
A blocking procedural assignment in a sequential block, such as x = y
. The
effects of the assignment are visible to any subsequent operations in the
block.
See IEEE 1800-2017 § 10.4.1 “Blocking procedural assignments”.
Traits: SameTypeOperands
Operands: ¶
Operand | Description |
---|---|
dst | any type |
src | any type |
moore.bool_cast
(::circt::moore::BoolCastOp) ¶
Cast a value to a single bit boolean
Syntax:
operation ::= `moore.bool_cast` $input attr-dict `:` type($input) `->` type($result)
Convert a nonzero or true value into 1, a zero or false value into 0, and any value containing Z or X bits into a X. This conversion is useful in combination with the logical and, or, implication, equivalence, and negation operators.
See IEEE 1800-2017 § 11.4.7 “Logical operators”.
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable
, InferTypeOpInterface
, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
input | unpacked type |
Results: ¶
Result | Description |
---|---|
result | single bit type |
moore.case_eq
(::circt::moore::CaseEqOp) ¶
Case equality
Syntax:
operation ::= `moore.case_eq` $lhs `,` $rhs attr-dict `:` type($lhs)
Compares the bits in the left- and right-hand side operand and returns a
single bit 0 or 1 result. If all corresponding bits in the left- and
right-hand side are equal (both 0, 1, X, or Z), the two operands are
considered equal (case_eq
returns 1, case_ne
returns 0). If any bits are
not equal, the two operands are considered not equal (case_eq
returns 0,
case_ne
returns 1). case_eq
corresponds to the ===
operator and
case_ne
to the !==
operator.
See IEEE 1800-2017 § 11.4.5 “Equality operators”.
Traits: AlwaysSpeculatableImplTrait
, Commutative
, SameTypeOperands
Interfaces: ConditionallySpeculatable
, InferTypeOpInterface
, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
lhs | simple bit vector type |
rhs | simple bit vector type |
Results: ¶
Result | Description |
---|---|
result | bit type |
moore.case_ne
(::circt::moore::CaseNeOp) ¶
Case inequality
Syntax:
operation ::= `moore.case_ne` $lhs `,` $rhs attr-dict `:` type($lhs)
Compares the bits in the left- and right-hand side operand and returns a
single bit 0 or 1 result. If all corresponding bits in the left- and
right-hand side are equal (both 0, 1, X, or Z), the two operands are
considered equal (case_eq
returns 1, case_ne
returns 0). If any bits are
not equal, the two operands are considered not equal (case_eq
returns 0,
case_ne
returns 1). case_eq
corresponds to the ===
operator and
case_ne
to the !==
operator.
See IEEE 1800-2017 § 11.4.5 “Equality operators”.
Traits: AlwaysSpeculatableImplTrait
, Commutative
, SameTypeOperands
Interfaces: ConditionallySpeculatable
, InferTypeOpInterface
, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
lhs | simple bit vector type |
rhs | simple bit vector type |
Results: ¶
Result | Description |
---|---|
result | bit type |
moore.concat
(::circt::moore::ConcatOp) ¶
A concatenation of expressions
Syntax:
operation ::= `moore.concat` $values attr-dict `:` functional-type($values, $result)
This operation represents the SystemVerilog concatenation expression
{x, y, z}
. See IEEE 1800-2017 §11.4.12 “Concatenation operators”.
All operands must be simple bit vector types.
The concatenation result is a simple bit vector type. The result is unsigned regardless of the sign of the operands (see concatenation-specific rules in IEEE 1800-2017 §11.8.1 “Rules for expression types”). The size of the result is the sum of the sizes of all operands. If any of the operands is four-valued, the result is four-valued; otherwise it is two-valued.
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable
, InferTypeOpInterface
, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
values | variadic of simple bit vector type |
Results: ¶
Result | Description |
---|---|
result | simple bit vector type |
moore.constant
(::circt::moore::ConstantOp) ¶
A constant integer value
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable
, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
value | ::mlir::IntegerAttr | arbitrary integer attribute |
Results: ¶
Result | Description |
---|---|
result | simple bit vector type |
moore.assign
(::circt::moore::ContinuousAssignOp) ¶
Continuous assignment within a module
Syntax:
operation ::= `moore.assign` $dst `,` $src attr-dict `:` type($src)
A continuous assignment in module scope, such as assign x = y;
, which
continuously drives the value on the right-hand side onto the left-hand
side.
See IEEE 1800-2017 § 10.3 “Continuous assignments”.
Traits: HasParent<SVModuleOp>
, SameTypeOperands
Operands: ¶
Operand | Description |
---|---|
dst | any type |
src | any type |
moore.conversion
(::circt::moore::ConversionOp) ¶
A type conversion
Syntax:
operation ::= `moore.conversion` $input attr-dict `:` type($input) `->` type($result)
An explicit or implicit type conversion. These are either generated automatically in order to make assignments compatible:
int a;
shortint b;
a = b; // generates an implicit cast from shortint to int
Or explicitly by the user through a type, sign, or const cast expression:
byte'(a)
unsigned'(a)
signed'(a)
42'(a)
See IEEE 1800-2017 § 6.24 “Casting”.
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable
, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
input | any type |
Results: ¶
Result | Description |
---|---|
result | any type |
moore.div
(::circt::moore::DivOp) ¶
Division
Syntax:
operation ::= `moore.div` $lhs `,` $rhs attr-dict `:` type($result)
Divide the left-hand side by the right-hand side operand. Any fractional part is truncated toward zero. If the right-hand side is zero, all bits of the result are X. If any bit in the two operands is Z or X, all bits in the result are X.
See IEEE 1800-2017 § 11.4.3 “Arithmetic operators”.
Traits: AlwaysSpeculatableImplTrait
, SameOperandsAndResultType
Interfaces: ConditionallySpeculatable
, InferTypeOpInterface
, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
lhs | simple bit vector type |
rhs | simple bit vector type |
Results: ¶
Result | Description |
---|---|
result | simple bit vector type |
moore.eq
(::circt::moore::EqOp) ¶
Logical equality
Syntax:
operation ::= `moore.eq` $lhs `,` $rhs attr-dict `:` type($lhs) `->` type($result)
Compares the bits in the left- and right-hand side operand and returns a
single bit 0, 1, or X result. If all corresponding bits in the left- and
right-hand side are equal, and all are 0 or 1 (not X or Z), the two operands
are considered equal (eq
returns 1, ne
returns 0). If any bits are not
equal, but all are 0 or 1, the two operands are considered not equal (eq
returns 0, ne
returns 1). If any bit in the two operands is Z or X,
returns X. eq
corresponds to the ==
operator and ne
to the !=
operator.
See IEEE 1800-2017 § 11.4.5 “Equality operators”.
Traits: AlwaysSpeculatableImplTrait
, Commutative
, SameTypeOperands
Interfaces: ConditionallySpeculatable
, InferTypeOpInterface
, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
lhs | simple bit vector type |
rhs | simple bit vector type |
Results: ¶
Result | Description |
---|---|
result | single bit type |
moore.ge
(::circt::moore::GeOp) ¶
Greater than or equal
Syntax:
operation ::= `moore.ge` $lhs `,` $rhs attr-dict `:` type($lhs) `->` type($result)
Compares the left- and right-hand side operand and returns a single bit 0,
1, or X result. If any bit in the two operands is Z or X, returns X.
Otherwise, if all bits are 0 or 1, lt
, le
, gt
, and ge
return whether
the left-hand side is less than, less than or equal to, greater than, or
greater than or equal to the right-hand side, respectively. lt
corresponds
to the <
operator, le
to <=
, gt
to >
, and ge
to >=
.
See IEEE 1800-2017 § 11.4.4 “Relational operators”.
Traits: AlwaysSpeculatableImplTrait
, SameTypeOperands
Interfaces: ConditionallySpeculatable
, InferTypeOpInterface
, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
lhs | simple bit vector type |
rhs | simple bit vector type |
Results: ¶
Result | Description |
---|---|
result | single bit type |
moore.gt
(::circt::moore::GtOp) ¶
Greater than
Syntax:
operation ::= `moore.gt` $lhs `,` $rhs attr-dict `:` type($lhs) `->` type($result)
Compares the left- and right-hand side operand and returns a single bit 0,
1, or X result. If any bit in the two operands is Z or X, returns X.
Otherwise, if all bits are 0 or 1, lt
, le
, gt
, and ge
return whether
the left-hand side is less than, less than or equal to, greater than, or
greater than or equal to the right-hand side, respectively. lt
corresponds
to the <
operator, le
to <=
, gt
to >
, and ge
to >=
.
See IEEE 1800-2017 § 11.4.4 “Relational operators”.
Traits: AlwaysSpeculatableImplTrait
, SameTypeOperands
Interfaces: ConditionallySpeculatable
, InferTypeOpInterface
, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
lhs | simple bit vector type |
rhs | simple bit vector type |
Results: ¶
Result | Description |
---|---|
result | single bit type |
moore.instance
(::circt::moore::InstanceOp) ¶
Create an instance of a module
Syntax:
operation ::= `moore.instance` $instanceName $moduleName attr-dict
The moore.instance
operation instantiates a moore.module
operation.
See IEEE 1800-2017 § 23.3 “Module instances”.
Interfaces: SymbolUserOpInterface
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
instanceName | ::mlir::StringAttr | string attribute |
moduleName | ::mlir::FlatSymbolRefAttr | flat symbol reference attribute |
moore.le
(::circt::moore::LeOp) ¶
Less than or equal
Syntax:
operation ::= `moore.le` $lhs `,` $rhs attr-dict `:` type($lhs) `->` type($result)
Compares the left- and right-hand side operand and returns a single bit 0,
1, or X result. If any bit in the two operands is Z or X, returns X.
Otherwise, if all bits are 0 or 1, lt
, le
, gt
, and ge
return whether
the left-hand side is less than, less than or equal to, greater than, or
greater than or equal to the right-hand side, respectively. lt
corresponds
to the <
operator, le
to <=
, gt
to >
, and ge
to >=
.
See IEEE 1800-2017 § 11.4.4 “Relational operators”.
Traits: AlwaysSpeculatableImplTrait
, SameTypeOperands
Interfaces: ConditionallySpeculatable
, InferTypeOpInterface
, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
lhs | simple bit vector type |
rhs | simple bit vector type |
Results: ¶
Result | Description |
---|---|
result | single bit type |
moore.lt
(::circt::moore::LtOp) ¶
Less than
Syntax:
operation ::= `moore.lt` $lhs `,` $rhs attr-dict `:` type($lhs) `->` type($result)
Compares the left- and right-hand side operand and returns a single bit 0,
1, or X result. If any bit in the two operands is Z or X, returns X.
Otherwise, if all bits are 0 or 1, lt
, le
, gt
, and ge
return whether
the left-hand side is less than, less than or equal to, greater than, or
greater than or equal to the right-hand side, respectively. lt
corresponds
to the <
operator, le
to <=
, gt
to >
, and ge
to >=
.
See IEEE 1800-2017 § 11.4.4 “Relational operators”.
Traits: AlwaysSpeculatableImplTrait
, SameTypeOperands
Interfaces: ConditionallySpeculatable
, InferTypeOpInterface
, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
lhs | simple bit vector type |
rhs | simple bit vector type |
Results: ¶
Result | Description |
---|---|
result | single bit type |
moore.mod
(::circt::moore::ModOp) ¶
Remainder
Syntax:
operation ::= `moore.mod` $lhs `,` $rhs attr-dict `:` type($result)
Compute the remainder of the left-hand side divided by the right-hand side operand. If the right-hand side is zero, all bits of the result are X. The sign of the result is the sign of the left-hand side. If any bit in the two operands is Z or X, all bits in the result are X.
See IEEE 1800-2017 § 11.4.3 “Arithmetic operators”.
Consider the following examples:
LHS | RHS | Result |
---|---|---|
11 | 3 | 2 |
-11 | 3 | -2 |
11 | -3 | 2 |
-11 | -3 | -2 |
Traits: AlwaysSpeculatableImplTrait
, SameOperandsAndResultType
Interfaces: ConditionallySpeculatable
, InferTypeOpInterface
, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
lhs | simple bit vector type |
rhs | simple bit vector type |
Results: ¶
Result | Description |
---|---|
result | simple bit vector type |
moore.mul
(::circt::moore::MulOp) ¶
Multiplication
Syntax:
operation ::= `moore.mul` $lhs `,` $rhs attr-dict `:` type($result)
Multiply the operands. If any bit in the two operands is Z or X, all bits in the result are X.
See IEEE 1800-2017 § 11.4.3 “Arithmetic operators”.
Traits: AlwaysSpeculatableImplTrait
, Commutative
, SameOperandsAndResultType
Interfaces: ConditionallySpeculatable
, InferTypeOpInterface
, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
lhs | simple bit vector type |
rhs | simple bit vector type |
Results: ¶
Result | Description |
---|---|
result | simple bit vector type |
moore.ne
(::circt::moore::NeOp) ¶
Logical inequality
Syntax:
operation ::= `moore.ne` $lhs `,` $rhs attr-dict `:` type($lhs) `->` type($result)
Compares the bits in the left- and right-hand side operand and returns a
single bit 0, 1, or X result. If all corresponding bits in the left- and
right-hand side are equal, and all are 0 or 1 (not X or Z), the two operands
are considered equal (eq
returns 1, ne
returns 0). If any bits are not
equal, but all are 0 or 1, the two operands are considered not equal (eq
returns 0, ne
returns 1). If any bit in the two operands is Z or X,
returns X. eq
corresponds to the ==
operator and ne
to the !=
operator.
See IEEE 1800-2017 § 11.4.5 “Equality operators”.
Traits: AlwaysSpeculatableImplTrait
, Commutative
, SameTypeOperands
Interfaces: ConditionallySpeculatable
, InferTypeOpInterface
, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
lhs | simple bit vector type |
rhs | simple bit vector type |
Results: ¶
Result | Description |
---|---|
result | single bit type |
moore.neg
(::circt::moore::NegOp) ¶
Arithmetic negation
Syntax:
operation ::= `moore.neg` $input attr-dict `:` type($input)
Negate a value to its two’s complement form. If any bit in the input is Z or X, all bits in the result are X.
See IEEE 1800-2017 § 11.4.3 “Arithmetic operators”.
Traits: AlwaysSpeculatableImplTrait
, SameOperandsAndResultType
Interfaces: ConditionallySpeculatable
, InferTypeOpInterface
, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
input | simple bit vector type |
Results: ¶
Result | Description |
---|---|
result | simple bit vector type |
moore.nonblocking_assign
(::circt::moore::NonBlockingAssignOp) ¶
Nonblocking procedural assignment
Syntax:
operation ::= `moore.nonblocking_assign` $dst `,` $src attr-dict `:` type($src)
A nonblocking procedural assignment in a sequential block, such as x <= y;
or x <= @(posedge y) z
or x <= #1ns y
. The assignment does not take
effect immediately. Subsequent operations in the block do not see the
effects of this assignment. Instead, the assignment is scheduled to happen
in a subsequent time step as dictated by the delay or event control.
See IEEE 1800-2017 § 10.4.2 “Nonblocking procedural assignments”.
Traits: SameTypeOperands
Operands: ¶
Operand | Description |
---|---|
dst | any type |
src | any type |
moore.not
(::circt::moore::NotOp) ¶
Bitwise unary negation
Syntax:
operation ::= `moore.not` $input attr-dict `:` type($input)
Applies the boolean NOT operation to each bit in the input. Corresponds to
the ~
operator, as well as the negation in the ~&
, ~|
, ^~
, and ~^
reduction operators.
See IEEE 1800-2017 § 11.4.8 “Bitwise operators”.
Input | Result |
---|---|
0 | 1 |
1 | 0 |
X | X |
Z | X |
Traits: AlwaysSpeculatableImplTrait
, SameOperandsAndResultType
Interfaces: ConditionallySpeculatable
, InferTypeOpInterface
, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
input | simple bit vector type |
Results: ¶
Result | Description |
---|---|
result | simple bit vector type |
moore.or
(::circt::moore::OrOp) ¶
Bitwise OR operation
Syntax:
operation ::= `moore.or` $lhs `,` $rhs attr-dict `:` type($result)
Applies the boolean OR operation to each pair of corresponding bits in the
left- and right-hand side operand. Corresponds to the |
operator.
See IEEE 1800-2017 § 11.4.8 “Bitwise operators”.
0 | 1 | X | Z | |
---|---|---|---|---|
0 | 0 | 1 | X | X |
1 | 1 | 1 | 1 | 1 |
X | X | 1 | X | X |
Z | X | 1 | X | X |
Traits: AlwaysSpeculatableImplTrait
, Commutative
, SameOperandsAndResultType
Interfaces: ConditionallySpeculatable
, InferTypeOpInterface
, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
lhs | simple bit vector type |
rhs | simple bit vector type |
Results: ¶
Result | Description |
---|---|
result | simple bit vector type |
moore.procedure
(::circt::moore::ProcedureOp) ¶
A procedure executed at different points in time
Syntax:
operation ::= `moore.procedure` $kind attr-dict-with-keyword $bodyRegion
The moore.procedure
operation represents the SystemVerilog initial
,
final
, always
, always_comb
, always_latch
, and always_ff
procedures.
Execution times of the various procedures:
An
initial
procedure is executed once at the start of a design’s lifetime, before any other procedures are executed.A
final
procedure is executed once at the end of a design’s lifetime, after all other procedures have stopped execution.An
always
oralways_ff
procedure is repeatedly executed during a design’s lifetime. Timing and event control inside the procedure can suspend its execution, for example to wait for a signal to change. If no such timing or event control is present, the procedure repeats infinitely at the current timestep, effectively deadlocking the design.An
always_comb
oralways_latch
procedure is executed once at the start of a design’s lifetime, after anyinitial
procedures, and throughout the lifetime of the design whenever any of the variables read by the body of the procedure changes. Since the procedure is only executed when its change, and not repeatedly, the body generally does not contain any timing or event control. This behavior mitigates a shortcoming ofalways
procedures, which commonly have an event control like@*
that blocks and waits for a change of any input signals. This prevents the body from executing when the design is initialized and properly reacting to the initial values of signals. In contrast,always_comb
andalways_latch
procedures have an implicit unconditional execution at design start-up.
See IEEE 1800-2017 § 9.2 “Structured procedures”.
Traits: NoRegionArguments
, NoTerminator
, RecursiveMemoryEffects
, RecursivelySpeculatableImplTrait
, SingleBlock
Interfaces: ConditionallySpeculatable
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
kind | circt::moore::ProcedureKindAttr | Procedure kind |
moore.read_lvalue
(::circt::moore::ReadLValueOp) ¶
Read the current value of a declaration
Syntax:
operation ::= `moore.read_lvalue` $input attr-dict `:` type($result)
Samples the current value of a declaration. This is a helper to capture the exact point at which declarations that can be targeted by assignments are read.
Traits: SameOperandsAndResultType
Interfaces: InferTypeOpInterface
Operands: ¶
Operand | Description |
---|---|
input | unpacked type |
Results: ¶
Result | Description |
---|---|
result | unpacked type |
moore.reduce_and
(::circt::moore::ReduceAndOp) ¶
Reduction AND operator
Syntax:
operation ::= `moore.reduce_and` $input attr-dict `:` type($input) `->` type($result)
Reduces all bits in the input to a single result bit by iteratively applying the boolean AND operator. If the input has only a single bit, that bit is returned.
See IEEE 1800-2017 § 11.4.9 “Reduction operators”. See the corresponding
and
, or
, and xor
operations for the truth table.
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable
, InferTypeOpInterface
, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
input | simple bit vector type |
Results: ¶
Result | Description |
---|---|
result | single bit type |
moore.reduce_or
(::circt::moore::ReduceOrOp) ¶
Reduction OR operator
Syntax:
operation ::= `moore.reduce_or` $input attr-dict `:` type($input) `->` type($result)
Reduces all bits in the input to a single result bit by iteratively applying the boolean OR operator. If the input has only a single bit, that bit is returned.
See IEEE 1800-2017 § 11.4.9 “Reduction operators”. See the corresponding
and
, or
, and xor
operations for the truth table.
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable
, InferTypeOpInterface
, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
input | simple bit vector type |
Results: ¶
Result | Description |
---|---|
result | single bit type |
moore.reduce_xor
(::circt::moore::ReduceXorOp) ¶
Reduction XOR operator
Syntax:
operation ::= `moore.reduce_xor` $input attr-dict `:` type($input) `->` type($result)
Reduces all bits in the input to a single result bit by iteratively applying the boolean XOR operator. If the input has only a single bit, that bit is returned.
See IEEE 1800-2017 § 11.4.9 “Reduction operators”. See the corresponding
and
, or
, and xor
operations for the truth table.
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable
, InferTypeOpInterface
, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
input | simple bit vector type |
Results: ¶
Result | Description |
---|---|
result | single bit type |
moore.module
(::circt::moore::SVModuleOp) ¶
A module definition
Syntax:
operation ::= `moore.module` $sym_name attr-dict-with-keyword $bodyRegion
The moore.module
operation represents a SystemVerilog module, including
its name, port list, and the constituent parts that make up its body. The
module’s body is an SSACFG region, since declarations within SystemVerilog
modules generally have to appear before their uses, and dedicated assignment
operators are used to make connections after declarations.
See IEEE 1800-2017 § 3.3 “Modules” and § 23.2 “Module definitions”.
Traits: IsolatedFromAbove
, NoTerminator
, SingleBlock
Interfaces: Symbol
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
sym_name | ::mlir::StringAttr | string attribute |
moore.shl
(::circt::moore::ShlOp) ¶
Logical left shift
Syntax:
operation ::= `moore.shl` $value `,` $amount attr-dict `:` type($value) `,` type($amount)
Shifts the value
to the left or right by amount
number of bits. The
result has the same type as the input value. The amount is always treated as
an unsigned number and has no effect on the signedness of the result. X or
Z bits in the input value are simply shifted left or right the same way 0 or
1 bits are. If the amount contains X or Z bits, all result bits are X.
shl
shifts bits to the left, filling in 0 for the vacated least
significant bits. shr
and ashr
shift bits to the right; shr
fills in
0 for the vacated most significant bits, and ashr
copies the input’s sign
bit into the vacated most significant bits. Note that in contrast to the SV
spec, the ashr
always fills in the sign bit regardless of the signedness
of the input.
shl
corresponds to the <<
and <<<
operators. shr
corresponds to the
>>
operator, and the >>>
operator applied to an unsigned value. ashr
corresponds to the >>>
operator applied to a signed value.
See IEEE 1800-2017 § 11.4.10 “Shift operators”.
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable
, InferTypeOpInterface
, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
value | simple bit vector type |
amount | simple bit vector type |
Results: ¶
Result | Description |
---|---|
result | simple bit vector type |
moore.shr
(::circt::moore::ShrOp) ¶
Logical right shift
Syntax:
operation ::= `moore.shr` $value `,` $amount attr-dict `:` type($value) `,` type($amount)
Shifts the value
to the left or right by amount
number of bits. The
result has the same type as the input value. The amount is always treated as
an unsigned number and has no effect on the signedness of the result. X or
Z bits in the input value are simply shifted left or right the same way 0 or
1 bits are. If the amount contains X or Z bits, all result bits are X.
shl
shifts bits to the left, filling in 0 for the vacated least
significant bits. shr
and ashr
shift bits to the right; shr
fills in
0 for the vacated most significant bits, and ashr
copies the input’s sign
bit into the vacated most significant bits. Note that in contrast to the SV
spec, the ashr
always fills in the sign bit regardless of the signedness
of the input.
shl
corresponds to the <<
and <<<
operators. shr
corresponds to the
>>
operator, and the >>>
operator applied to an unsigned value. ashr
corresponds to the >>>
operator applied to a signed value.
See IEEE 1800-2017 § 11.4.10 “Shift operators”.
Traits: AlwaysSpeculatableImplTrait
Interfaces: ConditionallySpeculatable
, InferTypeOpInterface
, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
value | simple bit vector type |
amount | simple bit vector type |
Results: ¶
Result | Description |
---|---|
result | simple bit vector type |
moore.sub
(::circt::moore::SubOp) ¶
Subtraction
Syntax:
operation ::= `moore.sub` $lhs `,` $rhs attr-dict `:` type($result)
Subtract the right-hand side from the left-hand side operand. If any bit in the two operands is Z or X, all bits in the result are X.
See IEEE 1800-2017 § 11.4.3 “Arithmetic operators”.
Traits: AlwaysSpeculatableImplTrait
, SameOperandsAndResultType
Interfaces: ConditionallySpeculatable
, InferTypeOpInterface
, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
lhs | simple bit vector type |
rhs | simple bit vector type |
Results: ¶
Result | Description |
---|---|
result | simple bit vector type |
moore.variable
(::circt::moore::VariableOp) ¶
A variable declaration
Syntax:
operation ::= `moore.variable` `` custom<ImplicitSSAName>($name) ($initial^)? attr-dict
`:` type($result)
See IEEE 1800-2017 § 6.8 “Variable declarations”.
Interfaces: OpAsmOpInterface
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
name | ::mlir::StringAttr | string attribute |
Operands: ¶
Operand | Description |
---|---|
initial | unpacked type |
Results: ¶
Result | Description |
---|---|
result | unpacked type |
moore.wildcard_eq
(::circt::moore::WildcardEqOp) ¶
Wildcard equality
Syntax:
operation ::= `moore.wildcard_eq` $lhs `,` $rhs attr-dict `:` type($lhs) `->` type($result)
Compares the bits in the left- and right-hand side operand and returns a
single bit 0, 1, or X result. If any bit in the left-hand side is Z or X,
returns X. Performs the same comparison as the eq
and ne
operations, but
all right-hand side bits that are X or Z are skipped. Therefore, X and Z in
the right-hand side act as wildcards or “don’t care” values. wildcard_eq
corresponds to the ==?
operator and wildcard_ne
to the !=?
operator.
See IEEE 1800-2017 § 11.4.6 “Wildcard equality operators”.
Traits: AlwaysSpeculatableImplTrait
, SameTypeOperands
Interfaces: ConditionallySpeculatable
, InferTypeOpInterface
, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
lhs | simple bit vector type |
rhs | simple bit vector type |
Results: ¶
Result | Description |
---|---|
result | single bit type |
moore.wildcard_ne
(::circt::moore::WildcardNeOp) ¶
Wildcard inequality
Syntax:
operation ::= `moore.wildcard_ne` $lhs `,` $rhs attr-dict `:` type($lhs) `->` type($result)
Compares the bits in the left- and right-hand side operand and returns a
single bit 0, 1, or X result. If any bit in the left-hand side is Z or X,
returns X. Performs the same comparison as the eq
and ne
operations, but
all right-hand side bits that are X or Z are skipped. Therefore, X and Z in
the right-hand side act as wildcards or “don’t care” values. wildcard_eq
corresponds to the ==?
operator and wildcard_ne
to the !=?
operator.
See IEEE 1800-2017 § 11.4.6 “Wildcard equality operators”.
Traits: AlwaysSpeculatableImplTrait
, SameTypeOperands
Interfaces: ConditionallySpeculatable
, InferTypeOpInterface
, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
lhs | simple bit vector type |
rhs | simple bit vector type |
Results: ¶
Result | Description |
---|---|
result | single bit type |
moore.xor
(::circt::moore::XorOp) ¶
Bitwise XOR operation
Syntax:
operation ::= `moore.xor` $lhs `,` $rhs attr-dict `:` type($result)
Applies the boolean XOR operation to each pair of corresponding bits in the
left- and right-hand side operand. Corresponds to the ^
operator.
See IEEE 1800-2017 § 11.4.8 “Bitwise operators”.
0 | 1 | X | Z | |
---|---|---|---|---|
0 | 0 | 1 | X | X |
1 | 1 | 0 | X | X |
X | X | X | X | X |
Z | X | X | X | X |
Traits: AlwaysSpeculatableImplTrait
, Commutative
, SameOperandsAndResultType
Interfaces: ConditionallySpeculatable
, InferTypeOpInterface
, NoMemoryEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
lhs | simple bit vector type |
rhs | simple bit vector type |
Results: ¶
Result | Description |
---|---|
result | simple bit vector type |