'moore' Dialect

This dialect provides operations and types to capture a SystemVerilog design after parsing, type checking, and elaboration.

Rationale ¶

The main goal of the moore dialect is to provide a set of operations and types for the ImportVerilog conversion to translate a fully parsed, type-checked, and elaborated Slang AST into MLIR operations. See IEEE 1800-2017 for more details about SystemVerilog. The dialect aims to faithfully capture the full SystemVerilog types and semantics, and provide a platform for transformation passes to resolve language quirks, analyze the design at a high level, and lower it to the core dialects.

In contrast, the sv dialect is geared towards emission of SystemVerilog text, and is focused on providing a good lowering target to allow for emission. The moore and sv dialect may eventually converge into a single dialect. As we are building out the Verilog frontend capabilities of CIRCT it is valuable to have a separate ingestion dialect, such that we do not have to make disruptive changes to the load-bearing sv dialect used in production.

LRM Rules ¶

Unconnection rules ¶

The SystemVerilog LRM defines unconnected behavior while leaving ports unconnected.

For variables that do not have a specified initializer. It has a default rule to initialize data value according to its type:

Types ¶

Simple Bit Vector Type ¶

The moore.iN and moore.lN types represent a two-valued or four-valued simple bit vector of width N.

ArrayType ¶

a packed array type

Syntax:

!moore.array<
  unsigned,   # size
  PackedType   # elementType
>

A packed array with a fixed number of elements. This type represents packed range dimensions ([a:b]) in SystemVerilog.

Parameters: ¶

AssocArrayType ¶

an associative array type

Syntax:

!moore.assoc_array<
  UnpackedType,   # elementType
  UnpackedType   # indexType
>

An associative array. This type represents associative arrays ([T]) in SystemVerilog.

Parameters: ¶

ChandleType ¶

the SystemVerilog chandle type

Syntax: !moore.chandle

EventType ¶

the SystemVerilog event type

Syntax: !moore.event

IntType ¶

a simple bit vector type

The !moore.iN and !moore.lN types represent a two-valued or four-valued simple bit vector of width N. The predefined SystemVerilog integer types map to this as follows:

Parameters: ¶

OpenArrayType ¶

an open packed array type

Syntax:

!moore.open_array<
  PackedType   # elementType
>

A packed array with an unspecified number of elements. This type represents unsized/open packed arrays ([]) in SystemVerilog.

Parameters: ¶

OpenUnpackedArrayType ¶

an open unpacked array type

Syntax:

!moore.open_uarray<
  UnpackedType   # elementType
>

An unpacked array with an unspecified number of elements. This type represents unsized/open unpacked arrays ([]) in SystemVerilog.

Parameters: ¶

QueueType ¶

a queue type

Syntax:

!moore.queue<
  UnpackedType,   # elementType
  unsigned   # bound
>

A queue with an optional upper bound on the number of elements that it can hold. This type represents queues ([$] and [$:a]) in SystemVerilog. A bound of 0 indicates an unbounded queue.

Parameters: ¶

RealType ¶

a SystemVerilog real type

Syntax: !moore.real

This type represents the SystemVerilog real type. Since the Moore dialect does not fully handle real-valued expressions properly yet, we coalesce the shortreal, real, and realtime types in the SystemVerilgo standard to this common !moore.real type. The standard specifies these types to be of at least 32, 64, and 64 bits, respectively. The !moore.real type is 64 bits wide.

RefType ¶

Syntax:

!moore.ref<
  UnpackedType   # nestedType
>

A wrapper is used to wrap any SystemVerilog type. It’s aimed to work for ‘moore.variable’, ‘moore.blocking_assign’, and ‘moore.read’, which are related to memory, like alloca/write/read.

Parameters: ¶

StringType ¶

the SystemVerilog string type

Syntax: !moore.string

StructType ¶

a packed struct type

Syntax:

!moore.struct<
  ::llvm::ArrayRef<StructLikeMember>   # members
>

A packed struct. All members are guaranteed to be packed as well.

Parameters: ¶

UnionType ¶

a packed union type

Syntax:

!moore.union<
  ::llvm::ArrayRef<StructLikeMember>   # members
>

A packed union. All members are guaranteed to be packed as well.

Parameters: ¶

UnpackedArrayType ¶

an unpacked array type

Syntax:

!moore.uarray<
  unsigned,   # size
  UnpackedType   # elementType
>

An unpacked array with a fixed number of elements. This type represents unpacked range dimensions ([a:b]) and unpacked array dimensions ([a]) in SystemVerilog.

Parameters: ¶

UnpackedStructType ¶

an unpacked struct type

Syntax:

!moore.ustruct<
  ::llvm::ArrayRef<StructLikeMember>   # members
>

An unpacked struct.

Parameters: ¶

UnpackedUnionType ¶

an unpacked union type

Syntax:

!moore.uunion<
  ::llvm::ArrayRef<StructLikeMember>   # members
>

An unpacked union.

Parameters: ¶

VoidType ¶

the SystemVerilog void type

Syntax: !moore.void

Operations ¶

moore.ashr (::circt::moore::AShrOp) ¶

Arithmetic right shift

Syntax:

operation ::= `moore.ashr` $value `,` $amount attr-dict `:` type($value) `,` type($amount)

Shifts the value to the left or right by amount number of bits. The result has the same type as the input value. The amount is always treated as an unsigned number and has no effect on the signedness of the result. X or Z bits in the input value are simply shifted left or right the same way 0 or 1 bits are. If the amount contains X or Z bits, all result bits are X.

shl shifts bits to the left, filling in 0 for the vacated least significant bits. shr and ashr shift bits to the right; shr fills in 0 for the vacated most significant bits, and ashr copies the input’s sign bit into the vacated most significant bits. Note that in contrast to the SV spec, the ashr always fills in the sign bit regardless of the signedness of the input.

shl corresponds to the << and <<< operators. shr corresponds to the >> operator, and the >>> operator applied to an unsigned value. ashr corresponds to the >>> operator applied to a signed value.

See IEEE 1800-2017 § 11.4.10 “Shift operators”.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.add (::circt::moore::AddOp) ¶

Addition

Syntax:

operation ::= `moore.add` $lhs `,` $rhs attr-dict `:` type($result)

Add the operands. If any bit in the two operands is Z or X, all bits in the result are X.

See IEEE 1800-2017 § 11.4.3 “Arithmetic operators”.

Traits: AlwaysSpeculatableImplTrait, Commutative, SameOperandsAndResultType

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.and (::circt::moore::AndOp) ¶

Bitwise AND operation

Syntax:

operation ::= `moore.and` $lhs `,` $rhs attr-dict `:` type($result)

Applies the boolean AND operation to each pair of corresponding bits in the left- and right-hand side operand. Corresponds to the & operator.

See IEEE 1800-2017 § 11.4.8 “Bitwise operators”.

Traits: AlwaysSpeculatableImplTrait, Commutative, SameOperandsAndResultType

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.assigned_variable (::circt::moore::AssignedVarOp) ¶

The copy of variable must have the initial value

Syntax:

operation ::= `moore.assigned_variable` `` custom<ImplicitSSAName>($name) $initial attr-dict `:` type($result)

Interfaces: OpAsmOpInterface

Attributes: ¶

Operands: ¶

Results: ¶

moore.blocking_assign (::circt::moore::BlockingAssignOp) ¶

Blocking procedural assignment

Syntax:

operation ::= `moore.blocking_assign` $dst `,` $src attr-dict `:` type($src)

A blocking procedural assignment in a sequential block, such as x = y. The effects of the assignment are visible to any subsequent operations in the block.

See IEEE 1800-2017 § 10.4.1 “Blocking procedural assignments”.

Interfaces: PromotableMemOpInterface

Operands: ¶

moore.bool_cast (::circt::moore::BoolCastOp) ¶

Cast a value to a single bit boolean

Syntax:

operation ::= `moore.bool_cast` $input attr-dict `:` type($input) `->` type($result)

Convert a nonzero or true value into 1, a zero or false value into 0, and any value containing Z or X bits into a X. This conversion is useful in combination with the logical and, or, implication, equivalence, and negation operators.

See IEEE 1800-2017 § 11.4.7 “Logical operators”.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.case_eq (::circt::moore::CaseEqOp) ¶

Case equality

Syntax:

operation ::= `moore.case_eq` $lhs `,` $rhs attr-dict `:` type($lhs)

Compares the bits in the left- and right-hand side operand and returns a single bit 0 or 1 result. If all corresponding bits in the left- and right-hand side are equal (both 0, 1, X, or Z), the two operands are considered equal (case_eq returns 1, case_ne returns 0). If any bits are not equal, the two operands are considered not equal (case_eq returns 0, case_ne returns 1). case_eq corresponds to the === operator and case_ne to the !== operator.

See IEEE 1800-2017 § 11.4.5 “Equality operators”.

Traits: AlwaysSpeculatableImplTrait, Commutative, SameTypeOperands

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.case_ne (::circt::moore::CaseNeOp) ¶

Case inequality

Syntax:

operation ::= `moore.case_ne` $lhs `,` $rhs attr-dict `:` type($lhs)

Compares the bits in the left- and right-hand side operand and returns a single bit 0 or 1 result. If all corresponding bits in the left- and right-hand side are equal (both 0, 1, X, or Z), the two operands are considered equal (case_eq returns 1, case_ne returns 0). If any bits are not equal, the two operands are considered not equal (case_eq returns 0, case_ne returns 1). case_eq corresponds to the === operator and case_ne to the !== operator.

See IEEE 1800-2017 § 11.4.5 “Equality operators”.

Traits: AlwaysSpeculatableImplTrait, Commutative, SameTypeOperands

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.concat (::circt::moore::ConcatOp) ¶

A concatenation of expressions

Syntax:

operation ::= `moore.concat` $values attr-dict `:` `(` type($values) `)` `->` type($result)

This operation represents the SystemVerilog concatenation expression {x, y, z}. See IEEE 1800-2017 §11.4.12 “Concatenation operators”.

All operands must be simple bit vector types.

The concatenation result is a simple bit vector type. The result is unsigned regardless of the sign of the operands (see concatenation-specific rules in IEEE 1800-2017 §11.8.1 “Rules for expression types”). The size of the result is the sum of the sizes of all operands. If any of the operands is four-valued, the result is four-valued; otherwise it is two-valued.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.concat_ref (::circt::moore::ConcatRefOp) ¶

The copy of concat that explicitly works on the ref type.

Syntax:

operation ::= `moore.concat_ref` $values attr-dict `:` `(` type($values) `)` `->` type($result)

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.conditional (::circt::moore::ConditionalOp) ¶

Conditional operation

Syntax:

operation ::= `moore.conditional` $condition attr-dict `:` type($condition) `->` type($result)
              $trueRegion $falseRegion

If cond_predicate is true, the operator returns the value of the first expression without evaluating the second expression; if false, it returns the value of the second expression without evaluating the first expression. If cond_predicate evaluates to an ambiguous value (x or z), then both the first expression and the second expression shall be evaluated, and compared for logical equivalence. If that comparison is true (1), the operator shall return either the first or second expression. Otherwise the operator returns a result based on the data types of the expressions.

When both the first and second expressions are of integral types, if the cond_predicate evaluates to an ambiguous value and the expressions are not logically equivalent, their results shall be combined bit by bit using the table below to calculate the final result. The first and second expressions are extended to the same width.

See IEEE 1800-2017 § 11.4.11 “Conditional operator”.

Traits: NoRegionArguments, RecursiveMemoryEffects, SingleBlockImplicitTerminator<moore::YieldOp>, SingleBlock

Operands: ¶

Results: ¶

moore.constant (::circt::moore::ConstantOp) ¶

A constant integer value

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes: ¶

Results: ¶

moore.assign (::circt::moore::ContinuousAssignOp) ¶

Continuous assignment within a module

Syntax:

operation ::= `moore.assign` $dst `,` $src attr-dict `:` type($src)

A continuous assignment in module scope, such as assign x = y;, which continuously drives the value on the right-hand side onto the left-hand side.

See IEEE 1800-2017 § 10.3 “Continuous assignments”.

Traits: HasParent<SVModuleOp>

Operands: ¶

moore.conversion (::circt::moore::ConversionOp) ¶

A type conversion

Syntax:

operation ::= `moore.conversion` $input attr-dict `:` type($input) `->` type($result)

An explicit or implicit type conversion. These are either generated automatically in order to make assignments compatible:

int a;
shortint b;
a = b;  // generates an implicit cast from shortint to int

Or explicitly by the user through a type, sign, or const cast expression:

byte'(a)
unsigned'(a)
signed'(a)
42'(a)

See IEEE 1800-2017 § 6.24 “Casting”.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.divs (::circt::moore::DivSOp) ¶

Division

Syntax:

operation ::= `moore.divs` $lhs `,` $rhs attr-dict `:` type($result)

Divide the left-hand side by the right-hand side operand. Any fractional part is truncated toward zero. If the right-hand side is zero, all bits of the result are X. If any bit in the two operands is Z or X, all bits in the result are X.

See IEEE 1800-2017 § 11.4.3 “Arithmetic operators”.

Traits: AlwaysSpeculatableImplTrait, SameOperandsAndResultType

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.divu (::circt::moore::DivUOp) ¶

Division

Syntax:

operation ::= `moore.divu` $lhs `,` $rhs attr-dict `:` type($result)

Divide the left-hand side by the right-hand side operand. Any fractional part is truncated toward zero. If the right-hand side is zero, all bits of the result are X. If any bit in the two operands is Z or X, all bits in the result are X.

See IEEE 1800-2017 § 11.4.3 “Arithmetic operators”.

Traits: AlwaysSpeculatableImplTrait, SameOperandsAndResultType

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.dyn_extract (::circt::moore::DynExtractOp) ¶

Syntax:

operation ::= `moore.dyn_extract` $input `from` $lowBit attr-dict `:`
              type($input) `,` type($lowBit) `->` type($result)

It’s similar with extract, but it’s used to select from a value with a dynamic low bit.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.dyn_extract_ref (::circt::moore::DynExtractRefOp) ¶

Syntax:

operation ::= `moore.dyn_extract_ref` $input `from` $lowBit attr-dict `:`
              type($input) `,` type($lowBit) `->` type($result)

The copy of dyn_extract that explicitly works on the ref type.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.eq (::circt::moore::EqOp) ¶

Logical equality

Syntax:

operation ::= `moore.eq` $lhs `,` $rhs attr-dict `:` type($lhs) `->` type($result)

Compares the bits in the left- and right-hand side operand and returns a single bit 0, 1, or X result. If all corresponding bits in the left- and right-hand side are equal, and all are 0 or 1 (not X or Z), the two operands are considered equal (eq returns 1, ne returns 0). If any bits are not equal, but all are 0 or 1, the two operands are considered not equal (eq returns 0, ne returns 1). If any bit in the two operands is Z or X, returns X. eq corresponds to the == operator and ne to the != operator.

See IEEE 1800-2017 § 11.4.5 “Equality operators”.

Traits: AlwaysSpeculatableImplTrait, Commutative, SameTypeOperands

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.wait_event (::circt::moore::EventOp) ¶

Detecting posedge and negedge

Syntax:

operation ::= `moore.wait_event` $edge $input attr-dict `:` type($input)

It is introduced by the symbol @, and it allows statement execution to be delayed until the occurrence of some simulation event occurring in a procedure executing concurrently with this procedure.

For the implicit event control(@(*)), there are two situations that are not automatically added to event expression:

1. Identifiers that only appear in wait or event expressions.

    always @(*) begin    // equivalent to @(b)
      @(n) kid = b;      // n is not added to @(*)
    end
   

2. Identifiers that only appear as a hierarchical_variable_identifier in the variable_lvalue of the left-hand side of assignments.

    always @(*) begin
      a = b + c;         // a is not added to @(*)
    end
   

Example:

  @(a, b, c)        // none
  @(posedge clk)    // positive edge
  @(negedge clk)    // negative edge
  @(edge clk)       // both edge
  @(*)              // implicit event control

See IEEE 1800-2017 § 9.4.2 “Event control”.

Traits: HasParent<ProcedureOp>

Attributes: ¶

Operands: ¶

moore.extract (::circt::moore::ExtractOp) ¶

Extract a range or single bits from a value

Syntax:

operation ::= `moore.extract` $input `from` $lowBit attr-dict `:` type($input) `->` type($result)

It’s used to select from a value with a constant low bit. This operation includes the vector bit/part-select, array, and memory addressing.If the address is invalid–out of bounds or has x or z bit– then it will produce x for 4-state or 0 for 2-state. Bit-select results are unsigned, regardless of the operands. Part-select results are unsigned, regardless of the operands even if the part-select specifies the entire vector. See IEEE 1800-2017 § 11.8.1 “Rules for expression types”

Example:

logic v [7:0];
v[1];                      // the bit-select addressing
v[3:0];                    // the part-select addressing
v[3-:4];  v[0+:4];         // They are equivalent to v[3:0]

See IEEE 1800-2017 § 11.5.1 “Vector bit-select and part-select addressing”.

Example:

// an array of 256-by-256 8-bit elements
logic [7:0] twod_array [0:255][0:255];
logic [7:0] mem_name [0:1023];      // a memory of 1024 8-bit words

See IEEE 1800-2017 § 11.5.2 “Array and memory addressing”.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes: ¶

Operands: ¶

Results: ¶

moore.extract_ref (::circt::moore::ExtractRefOp) ¶

Syntax:

operation ::= `moore.extract_ref` $input `from` $lowBit attr-dict `:` type($input) `->` type($result)

The copy of extract that explicitly works on the ref type.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes: ¶

Operands: ¶

Results: ¶

moore.instance (::circt::moore::InstanceOp) ¶

Create an instance of a module

The moore.instance operation instantiates a moore.module operation.

See IEEE 1800-2017 § 23.3 “Module instances”.

Interfaces: OpAsmOpInterface, SymbolUserOpInterface

Attributes: ¶

Operands: ¶

Results: ¶

moore.mods (::circt::moore::ModSOp) ¶

Remainder

Syntax:

operation ::= `moore.mods` $lhs `,` $rhs attr-dict `:` type($result)

Compute the remainder of the left-hand side divided by the right-hand side operand. If the right-hand side is zero, all bits of the result are X. The sign of the result is the sign of the left-hand side. If any bit in the two operands is Z or X, all bits in the result are X.

See IEEE 1800-2017 § 11.4.3 “Arithmetic operators”.

Consider the following examples:

Traits: AlwaysSpeculatableImplTrait, SameOperandsAndResultType

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.modu (::circt::moore::ModUOp) ¶

Remainder

Syntax:

operation ::= `moore.modu` $lhs `,` $rhs attr-dict `:` type($result)

Compute the remainder of the left-hand side divided by the right-hand side operand. If the right-hand side is zero, all bits of the result are X. The sign of the result is the sign of the left-hand side. If any bit in the two operands is Z or X, all bits in the result are X.

See IEEE 1800-2017 § 11.4.3 “Arithmetic operators”.

Consider the following examples:

Traits: AlwaysSpeculatableImplTrait, SameOperandsAndResultType

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.mul (::circt::moore::MulOp) ¶

Multiplication

Syntax:

operation ::= `moore.mul` $lhs `,` $rhs attr-dict `:` type($result)

Multiply the operands. If any bit in the two operands is Z or X, all bits in the result are X.

See IEEE 1800-2017 § 11.4.3 “Arithmetic operators”.

Traits: AlwaysSpeculatableImplTrait, Commutative, SameOperandsAndResultType

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.named_constant (::circt::moore::NamedConstantOp) ¶

An elaboration time constant expression

Syntax:

operation ::= `moore.named_constant` $kind
              ``custom<ImplicitSSAName>($name)
              $value `:` type($result) attr-dict

Constants are named data objects that never change. SystemVerilog provides three elaboration-time constants: parameter, localparam, and specparam.

See IEEE 1800-2017 § 6.20 “Constants”.

Traits: SameOperandsAndResultType

Interfaces: InferTypeOpInterface, OpAsmOpInterface

Attributes: ¶

Operands: ¶

Results: ¶

moore.ne (::circt::moore::NeOp) ¶

Logical inequality

Syntax:

operation ::= `moore.ne` $lhs `,` $rhs attr-dict `:` type($lhs) `->` type($result)

Compares the bits in the left- and right-hand side operand and returns a single bit 0, 1, or X result. If all corresponding bits in the left- and right-hand side are equal, and all are 0 or 1 (not X or Z), the two operands are considered equal (eq returns 1, ne returns 0). If any bits are not equal, but all are 0 or 1, the two operands are considered not equal (eq returns 0, ne returns 1). If any bit in the two operands is Z or X, returns X. eq corresponds to the == operator and ne to the != operator.

See IEEE 1800-2017 § 11.4.5 “Equality operators”.

Traits: AlwaysSpeculatableImplTrait, Commutative, SameTypeOperands

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.neg (::circt::moore::NegOp) ¶

Arithmetic negation

Syntax:

operation ::= `moore.neg` $input attr-dict `:` type($input)

Negate a value to its two’s complement form. If any bit in the input is Z or X, all bits in the result are X.

See IEEE 1800-2017 § 11.4.3 “Arithmetic operators”.

Traits: AlwaysSpeculatableImplTrait, SameOperandsAndResultType

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.net (::circt::moore::NetOp) ¶

A net declaration

Syntax:

operation ::= `moore.net` `` custom<ImplicitSSAName>($name) $kind ($assignment^)? attr-dict
              `:` type($result)

The moore.net operation is a net declaration. Net types defines different types of net connection in SV. There are twelve built-in net types defined in the official standard construct of the operation: supply0, supply1, tri, triand, trior, trireg, tri0, tri1, uwire, wire, wand, wor. Optional assignment argument allows net operation to be initialized with specific values as soon as it is created. Only one net declaration assignment can be made for a particular net. See IEEE 1800-2017 § 10.3.1 “The net declaration assignment” for the differences between net declaration assignments and continuous assign statements. It has some features that are not supported: declaring an interconnect net and using user-defined types in the net operation.

See IEEE 1800-2017 § 6.7 “Net declarations”.

Interfaces: OpAsmOpInterface

Attributes: ¶

Operands: ¶

Results: ¶

moore.nonblocking_assign (::circt::moore::NonBlockingAssignOp) ¶

Nonblocking procedural assignment

Syntax:

operation ::= `moore.nonblocking_assign` $dst `,` $src attr-dict `:` type($src)

A nonblocking procedural assignment in a sequential block, such as x <= y; or x <= @(posedge y) z or x <= #1ns y. The assignment does not take effect immediately. Subsequent operations in the block do not see the effects of this assignment. Instead, the assignment is scheduled to happen in a subsequent time step as dictated by the delay or event control.

See IEEE 1800-2017 § 10.4.2 “Nonblocking procedural assignments”.

Operands: ¶

moore.not (::circt::moore::NotOp) ¶

Bitwise unary negation

Syntax:

operation ::= `moore.not` $input attr-dict `:` type($input)

Applies the boolean NOT operation to each bit in the input. Corresponds to the ~ operator, as well as the negation in the ~&, ~|, ^~, and ~^ reduction operators.

See IEEE 1800-2017 § 11.4.8 “Bitwise operators”.

Traits: AlwaysSpeculatableImplTrait, SameOperandsAndResultType

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.or (::circt::moore::OrOp) ¶

Bitwise OR operation

Syntax:

operation ::= `moore.or` $lhs `,` $rhs attr-dict `:` type($result)

Applies the boolean OR operation to each pair of corresponding bits in the left- and right-hand side operand. Corresponds to the | operator.

See IEEE 1800-2017 § 11.4.8 “Bitwise operators”.

Traits: AlwaysSpeculatableImplTrait, Commutative, SameOperandsAndResultType

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.output (::circt::moore::OutputOp) ¶

Assign module outputs

Syntax:

operation ::= `moore.output` attr-dict ($outputs^ `:` type($outputs))?

The moore.output operation marks the end of a moore.module body region and specifies the values to present for the module’s output ports.

Traits: AlwaysSpeculatableImplTrait, HasParent<SVModuleOp>, ReturnLike, Terminator

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface), RegionBranchTerminatorOpInterface

Effects: MemoryEffects::Effect{}

Operands: ¶

moore.procedure (::circt::moore::ProcedureOp) ¶

A procedure executed at different points in time

Syntax:

operation ::= `moore.procedure` $kind attr-dict-with-keyword $bodyRegion

The moore.procedure operation represents the SystemVerilog initial, final, always, always_comb, always_latch, and always_ff procedures.

Execution times of the various procedures:

• An initial procedure is executed once at the start of a design’s lifetime, before any other procedures are executed.

• A final procedure is executed once at the end of a design’s lifetime, after all other procedures have stopped execution.

• An always or always_ff procedure is repeatedly executed during a design’s lifetime. Timing and event control inside the procedure can suspend its execution, for example to wait for a signal to change. If no such timing or event control is present, the procedure repeats infinitely at the current timestep, effectively deadlocking the design.

• An always_comb or always_latch procedure is executed once at the start of a design’s lifetime, after any initial procedures, and throughout the lifetime of the design whenever any of the variables read by the body of the procedure changes. Since the procedure is only executed when its change, and not repeatedly, the body generally does not contain any timing or event control. This behavior mitigates a shortcoming of always procedures, which commonly have an event control like @* that blocks and waits for a change of any input signals. This prevents the body from executing when the design is initialized and properly reacting to the initial values of signals. In contrast, always_comb and always_latch procedures have an implicit unconditional execution at design start-up.

See IEEE 1800-2017 § 9.2 “Structured procedures”.

Traits: NoRegionArguments, NoTerminator, RecursiveMemoryEffects, RecursivelySpeculatableImplTrait, SingleBlock

Interfaces: ConditionallySpeculatable

Attributes: ¶

moore.read (::circt::moore::ReadOp) ¶

Read the current value of a declaration

Syntax:

operation ::= `moore.read` $input attr-dict `:` type($input)

Samples the current value of a declaration. This is a helper to capture the exact point at which declarations that can be targeted by all possible expressions are read. It’s similar to llvm.load.

Interfaces: InferTypeOpInterface, PromotableMemOpInterface

Operands: ¶

Results: ¶

moore.reduce_and (::circt::moore::ReduceAndOp) ¶

Reduction AND operator

Syntax:

operation ::= `moore.reduce_and` $input attr-dict `:` type($input) `->` type($result)

Reduces all bits in the input to a single result bit by iteratively applying the boolean AND operator. If the input has only a single bit, that bit is returned.

See IEEE 1800-2017 § 11.4.9 “Reduction operators”. See the corresponding and, or, and xor operations for the truth table.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.reduce_or (::circt::moore::ReduceOrOp) ¶

Reduction OR operator

Syntax:

operation ::= `moore.reduce_or` $input attr-dict `:` type($input) `->` type($result)

Reduces all bits in the input to a single result bit by iteratively applying the boolean OR operator. If the input has only a single bit, that bit is returned.

See IEEE 1800-2017 § 11.4.9 “Reduction operators”. See the corresponding and, or, and xor operations for the truth table.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.reduce_xor (::circt::moore::ReduceXorOp) ¶

Reduction XOR operator

Syntax:

operation ::= `moore.reduce_xor` $input attr-dict `:` type($input) `->` type($result)

Reduces all bits in the input to a single result bit by iteratively applying the boolean XOR operator. If the input has only a single bit, that bit is returned.

See IEEE 1800-2017 § 11.4.9 “Reduction operators”. See the corresponding and, or, and xor operations for the truth table.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.replicate (::circt::moore::ReplicateOp) ¶

Multiple concatenation of expressions

Syntax:

operation ::= `moore.replicate` $value attr-dict `:` type($value) `->` type($result)

This operation indicates a joining together of that many copies of the concatenation {constant{w}}. Which enclosed together within brace. The ‘constant’ must a non-negative, non-x, and non-z constant expression. The ‘constant’ may be a value of zero, but it only exists in parameterized code, and it will be ignored(type is changed to the void).

Example:

  {0{w}}   // empty! ignore it.
  {4{w}}   // the same as {w, w, w, w}

See IEEE 1800-2017 §11.4.12 “Concatenation operators”.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.module (::circt::moore::SVModuleOp) ¶

A module definition

The moore.module operation represents a SystemVerilog module, including its name, port list, and the constituent parts that make up its body. The module’s body is a graph region.

See IEEE 1800-2017 § 3.3 “Modules” and § 23.2 “Module definitions”.

Traits: IsolatedFromAbove, SingleBlockImplicitTerminator<OutputOp>, SingleBlock

Interfaces: OpAsmOpInterface, RegionKindInterface, Symbol

Attributes: ¶

moore.sge (::circt::moore::SgeOp) ¶

Signed greater than or equal comparison

Syntax:

operation ::= `moore.sge` $lhs `,` $rhs attr-dict `:` type($lhs) `->` type($result)

Compares the left- and right-hand side operand and returns a single bit 0, 1, or X result. If any bit in the two operands is Z or X, returns X. Otherwise, if all bits are 0 or 1, ult/slt, ule/sle, ugt/sgt, and uge/sge return whether the left-hand side is less than, less than or equal to, greater than, or greater than or equal to the right-hand side, respectively. ult/slt corresponds to the < operator, ule/sle to <=, ugt/sgt to >, and uge/sge to >=.

See IEEE 1800-2017 § 11.4.4 “Relational operators”.

Traits: AlwaysSpeculatableImplTrait, SameTypeOperands

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.sgt (::circt::moore::SgtOp) ¶

Signed greater than comparison

Syntax:

operation ::= `moore.sgt` $lhs `,` $rhs attr-dict `:` type($lhs) `->` type($result)

Compares the left- and right-hand side operand and returns a single bit 0, 1, or X result. If any bit in the two operands is Z or X, returns X. Otherwise, if all bits are 0 or 1, ult/slt, ule/sle, ugt/sgt, and uge/sge return whether the left-hand side is less than, less than or equal to, greater than, or greater than or equal to the right-hand side, respectively. ult/slt corresponds to the < operator, ule/sle to <=, ugt/sgt to >, and uge/sge to >=.

See IEEE 1800-2017 § 11.4.4 “Relational operators”.

Traits: AlwaysSpeculatableImplTrait, SameTypeOperands

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.shl (::circt::moore::ShlOp) ¶

Logical left shift

Syntax:

operation ::= `moore.shl` $value `,` $amount attr-dict `:` type($value) `,` type($amount)

Shifts the value to the left or right by amount number of bits. The result has the same type as the input value. The amount is always treated as an unsigned number and has no effect on the signedness of the result. X or Z bits in the input value are simply shifted left or right the same way 0 or 1 bits are. If the amount contains X or Z bits, all result bits are X.

shl shifts bits to the left, filling in 0 for the vacated least significant bits. shr and ashr shift bits to the right; shr fills in 0 for the vacated most significant bits, and ashr copies the input’s sign bit into the vacated most significant bits. Note that in contrast to the SV spec, the ashr always fills in the sign bit regardless of the signedness of the input.

shl corresponds to the << and <<< operators. shr corresponds to the >> operator, and the >>> operator applied to an unsigned value. ashr corresponds to the >>> operator applied to a signed value.

See IEEE 1800-2017 § 11.4.10 “Shift operators”.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.shr (::circt::moore::ShrOp) ¶

Logical right shift

Syntax:

operation ::= `moore.shr` $value `,` $amount attr-dict `:` type($value) `,` type($amount)

Shifts the value to the left or right by amount number of bits. The result has the same type as the input value. The amount is always treated as an unsigned number and has no effect on the signedness of the result. X or Z bits in the input value are simply shifted left or right the same way 0 or 1 bits are. If the amount contains X or Z bits, all result bits are X.

shl shifts bits to the left, filling in 0 for the vacated least significant bits. shr and ashr shift bits to the right; shr fills in 0 for the vacated most significant bits, and ashr copies the input’s sign bit into the vacated most significant bits. Note that in contrast to the SV spec, the ashr always fills in the sign bit regardless of the signedness of the input.

shl corresponds to the << and <<< operators. shr corresponds to the >> operator, and the >>> operator applied to an unsigned value. ashr corresponds to the >>> operator applied to a signed value.

See IEEE 1800-2017 § 11.4.10 “Shift operators”.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.sle (::circt::moore::SleOp) ¶

Signed less than or equal comparison

Syntax:

operation ::= `moore.sle` $lhs `,` $rhs attr-dict `:` type($lhs) `->` type($result)

Compares the left- and right-hand side operand and returns a single bit 0, 1, or X result. If any bit in the two operands is Z or X, returns X. Otherwise, if all bits are 0 or 1, ult/slt, ule/sle, ugt/sgt, and uge/sge return whether the left-hand side is less than, less than or equal to, greater than, or greater than or equal to the right-hand side, respectively. ult/slt corresponds to the < operator, ule/sle to <=, ugt/sgt to >, and uge/sge to >=.

See IEEE 1800-2017 § 11.4.4 “Relational operators”.

Traits: AlwaysSpeculatableImplTrait, SameTypeOperands

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.slt (::circt::moore::SltOp) ¶

Signed less than comparison

Syntax:

operation ::= `moore.slt` $lhs `,` $rhs attr-dict `:` type($lhs) `->` type($result)

Compares the left- and right-hand side operand and returns a single bit 0, 1, or X result. If any bit in the two operands is Z or X, returns X. Otherwise, if all bits are 0 or 1, ult/slt, ule/sle, ugt/sgt, and uge/sge return whether the left-hand side is less than, less than or equal to, greater than, or greater than or equal to the right-hand side, respectively. ult/slt corresponds to the < operator, ule/sle to <=, ugt/sgt to >, and uge/sge to >=.

See IEEE 1800-2017 § 11.4.4 “Relational operators”.

Traits: AlwaysSpeculatableImplTrait, SameTypeOperands

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.struct_create (::circt::moore::StructCreateOp) ¶

Struct Create operation

Syntax:

operation ::= `moore.struct_create` $input attr-dict `:` type($input) `->` type($result)

A structure represents a collection of data types that can be referenced as a whole, or the individual data types that make up the structure can be referenced by name. By default, structures are unpacked, meaning that there is an implementation-dependent packing of the data types. Unpacked structures can contain any data type. See IEEE 1800-2017 § 7.2 “Structures”

Example:

struct { bit [7:0] opcode; bit [23:0] addr; }IR;
IR.opcode = 1;   // set field in IR.
// anonymous structure
// defines variable IR
typedef struct {
bit [7:0] opcode;
bit [23:0] addr;
} instruction; // named structure type
instruction IR; // define variable

See IEEE 1800-2017 § 7.2. “Structures”.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.struct_extract (::circt::moore::StructExtractOp) ¶

Struct Extract operation

Syntax:

operation ::= `moore.struct_extract` $input `,` $fieldName attr-dict `:` type($input) `->` type($result)

Structures can be converted to bits preserving the bit pattern. In other words, they can be converted back to the same value without any loss of information. When unpacked data are converted to the packed representation, the order of the data in the packed representation is such that the first field in the structure occupies the MSBs. The effect is the same as a concatenation of the data items (struct fields or array elements) in order. The type of the elements in an unpacked structure or array shall be valid for a packed representation in order to be cast to any other type, whether packed or unpacked. See IEEE 1800-2017 § 6.24.1 “Cast operator”

Example:

typedef struct {
int addr = 1 + constant;
int crc;
byte data [4] = '{4{1}};
} packet1;

packet1 p1; // initialization defined by the typedef.
            // p1.crc will use the default value for an int

See IEEE 1800-2017 § 7.2.1 “Assigning to structures”.

Interfaces: DestructurableAccessorOpInterface

Attributes: ¶

Operands: ¶

Results: ¶

moore.struct_extract_ref (::circt::moore::StructExtractRefOp) ¶

Struct Extract operation

Syntax:

operation ::= `moore.struct_extract_ref` $input `,` $fieldName attr-dict `:`
              type($input) `->` type($result)

Interfaces: DestructurableAccessorOpInterface

Attributes: ¶

Operands: ¶

Results: ¶

moore.struct_inject (::circt::moore::StructInjectOp) ¶

Struct Field operation

A structure can be assigned as a whole and passed to or from a subroutine as a whole. Members of a structure data type can be assigned individual default member values by using an initial assignment with the declaration of each member. The assigned expression shall be a constant expression. See IEEE 1800-2017 § 7.2.2 “Assigning to structures”

Example:

typedef struct {
int addr = 1 + constant;
int crc;
byte data [4] = '{4{1}};
} packet1;

packet1 p1; // initialization defined by the typedef.
            // p1.crc will use the default value for an int

See IEEE 1800-2017 § 7.2. “Assigning to structures”.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes: ¶

Operands: ¶

Results: ¶

moore.sub (::circt::moore::SubOp) ¶

Subtraction

Syntax:

operation ::= `moore.sub` $lhs `,` $rhs attr-dict `:` type($result)

Subtract the right-hand side from the left-hand side operand. If any bit in the two operands is Z or X, all bits in the result are X.

See IEEE 1800-2017 § 11.4.3 “Arithmetic operators”.

Traits: AlwaysSpeculatableImplTrait, SameOperandsAndResultType

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.uge (::circt::moore::UgeOp) ¶

Unsigned greater than or equal comparison

Syntax:

operation ::= `moore.uge` $lhs `,` $rhs attr-dict `:` type($lhs) `->` type($result)

Compares the left- and right-hand side operand and returns a single bit 0, 1, or X result. If any bit in the two operands is Z or X, returns X. Otherwise, if all bits are 0 or 1, ult/slt, ule/sle, ugt/sgt, and uge/sge return whether the left-hand side is less than, less than or equal to, greater than, or greater than or equal to the right-hand side, respectively. ult/slt corresponds to the < operator, ule/sle to <=, ugt/sgt to >, and uge/sge to >=.

See IEEE 1800-2017 § 11.4.4 “Relational operators”.

Traits: AlwaysSpeculatableImplTrait, SameTypeOperands

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.ugt (::circt::moore::UgtOp) ¶

Unsigned greater than comparison

Syntax:

operation ::= `moore.ugt` $lhs `,` $rhs attr-dict `:` type($lhs) `->` type($result)

Compares the left- and right-hand side operand and returns a single bit 0, 1, or X result. If any bit in the two operands is Z or X, returns X. Otherwise, if all bits are 0 or 1, ult/slt, ule/sle, ugt/sgt, and uge/sge return whether the left-hand side is less than, less than or equal to, greater than, or greater than or equal to the right-hand side, respectively. ult/slt corresponds to the < operator, ule/sle to <=, ugt/sgt to >, and uge/sge to >=.

See IEEE 1800-2017 § 11.4.4 “Relational operators”.

Traits: AlwaysSpeculatableImplTrait, SameTypeOperands

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.ule (::circt::moore::UleOp) ¶

Unsigned less than or equal comparison

Syntax:

operation ::= `moore.ule` $lhs `,` $rhs attr-dict `:` type($lhs) `->` type($result)

Compares the left- and right-hand side operand and returns a single bit 0, 1, or X result. If any bit in the two operands is Z or X, returns X. Otherwise, if all bits are 0 or 1, ult/slt, ule/sle, ugt/sgt, and uge/sge return whether the left-hand side is less than, less than or equal to, greater than, or greater than or equal to the right-hand side, respectively. ult/slt corresponds to the < operator, ule/sle to <=, ugt/sgt to >, and uge/sge to >=.

See IEEE 1800-2017 § 11.4.4 “Relational operators”.

Traits: AlwaysSpeculatableImplTrait, SameTypeOperands

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.ult (::circt::moore::UltOp) ¶

Unsigned less than comparison

Syntax:

operation ::= `moore.ult` $lhs `,` $rhs attr-dict `:` type($lhs) `->` type($result)

Compares the left- and right-hand side operand and returns a single bit 0, 1, or X result. If any bit in the two operands is Z or X, returns X. Otherwise, if all bits are 0 or 1, ult/slt, ule/sle, ugt/sgt, and uge/sge return whether the left-hand side is less than, less than or equal to, greater than, or greater than or equal to the right-hand side, respectively. ult/slt corresponds to the < operator, ule/sle to <=, ugt/sgt to >, and uge/sge to >=.

See IEEE 1800-2017 § 11.4.4 “Relational operators”.

Traits: AlwaysSpeculatableImplTrait, SameTypeOperands

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.union_create (::circt::moore::UnionCreateOp) ¶

Union Create operation

Syntax:

operation ::= `moore.union_create` $input attr-dict `:` type($input) `->` type($result)

A union is a data type that represents a single piece of storage that can be accessed using one of the named member data types. Only one of the data types in the union can be used at a time. By default, a union is unpacked, meaning there is no required representation for how members of the union are stored. Dynamic types and chandle types can only be used in tagged unions. See IEEE 1800-2017 § 7.3 “Unions”

Example:

typedef union { int i; shortreal f; } num; // named union type
num n;
n.f = 0.0; // set n in floating point format
typedef struct {
bit isfloat;
union { int i; shortreal f; } n;           // anonymous union type
} tagged_st;                               // named structure

See IEEE 1800-2017 § 7.3 “Unions”

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes: ¶

Operands: ¶

Results: ¶

moore.union_extract (::circt::moore::UnionExtractOp) ¶

Union Extract operation

Syntax:

operation ::= `moore.union_extract` $input `,`   $fieldName  attr-dict `:`
              type($input) `->` type($result)

With packed unions, writing one member and reading another is independent of the byte ordering of the machine, unlike an unpacked union of unpacked structures, which are C-compatible and have members in ascending address order. See IEEE 1800-2017 § 7.3.1 “Packed unions”

Example:

typedef union packed { // default unsigned
s_atmcell acell;
bit [423:0] bit_slice;
bit [52:0][7:0] byte_slice;
} u_atmcell;
u_atmcell u1;
byte b; bit [3:0] nib;
b = u1.bit_slice[415:408]; // same as b = u1.byte_slice[51];
nib = u1.bit_slice [423:420];

See IEEE 1800-2017 § 7.3.1 “Packed unions”

Attributes: ¶

Operands: ¶

Results: ¶

moore.union_extract_ref (::circt::moore::UnionExtractRefOp) ¶

Union Extract operation

Syntax:

operation ::= `moore.union_extract_ref` $input `,`   $fieldName  attr-dict `:`
              type($input) `->` type($result)

Attributes: ¶

Operands: ¶

Results: ¶

moore.variable (::circt::moore::VariableOp) ¶

A variable declaration

Syntax:

operation ::= `moore.variable` `` custom<ImplicitSSAName>($name) ($initial^)? attr-dict
              `:` type($result)

See IEEE 1800-2017 § 6.8 “Variable declarations”.

Interfaces: DestructurableAllocationOpInterface, OpAsmOpInterface, PromotableAllocationOpInterface

Attributes: ¶

Operands: ¶

Results: ¶

moore.wildcard_eq (::circt::moore::WildcardEqOp) ¶

Wildcard equality

Syntax:

operation ::= `moore.wildcard_eq` $lhs `,` $rhs attr-dict `:` type($lhs) `->` type($result)

Compares the bits in the left- and right-hand side operand and returns a single bit 0, 1, or X result. If any bit in the left-hand side is Z or X, returns X. Performs the same comparison as the eq and ne operations, but all right-hand side bits that are X or Z are skipped. Therefore, X and Z in the right-hand side act as wildcards or “don’t care” values. wildcard_eq corresponds to the ==? operator and wildcard_ne to the !=? operator.

See IEEE 1800-2017 § 11.4.6 “Wildcard equality operators”.

Traits: AlwaysSpeculatableImplTrait, SameTypeOperands

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.wildcard_ne (::circt::moore::WildcardNeOp) ¶

Wildcard inequality

Syntax:

operation ::= `moore.wildcard_ne` $lhs `,` $rhs attr-dict `:` type($lhs) `->` type($result)

Compares the bits in the left- and right-hand side operand and returns a single bit 0, 1, or X result. If any bit in the left-hand side is Z or X, returns X. Performs the same comparison as the eq and ne operations, but all right-hand side bits that are X or Z are skipped. Therefore, X and Z in the right-hand side act as wildcards or “don’t care” values. wildcard_eq corresponds to the ==? operator and wildcard_ne to the !=? operator.

See IEEE 1800-2017 § 11.4.6 “Wildcard equality operators”.

Traits: AlwaysSpeculatableImplTrait, SameTypeOperands

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.xor (::circt::moore::XorOp) ¶

Bitwise XOR operation

Syntax:

operation ::= `moore.xor` $lhs `,` $rhs attr-dict `:` type($result)

Applies the boolean XOR operation to each pair of corresponding bits in the left- and right-hand side operand. Corresponds to the ^ operator.

See IEEE 1800-2017 § 11.4.8 “Bitwise operators”.

Traits: AlwaysSpeculatableImplTrait, Commutative, SameOperandsAndResultType

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.yield (::circt::moore::YieldOp) ¶

Conditional yield and termination operation

Syntax:

operation ::= `moore.yield` attr-dict $result `:` type($result)

“moore.yield” yields an SSA value from the Moore dialect op region and terminates the regions. The semantics of how the values are yielded is defined by the parent operation. If “moore.yield” has any operands, the operands must match the parent operation’s results. If the parent operation defines no values, then the “moore.yield” may be left out in the custom syntax and the builders will insert one implicitly. Otherwise, it has to be present in the syntax to indicate which values are yielded.

Traits: AlwaysSpeculatableImplTrait, HasParent<ConditionalOp>, Terminator

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶