'moore' Dialect

Types and operations for Moore dialect This dialect defines the moore dialect, which represents various SystemVerilog-specific constructs without ambiguities and all types resolved.

Operation definition ¶

moore.mir.assign (::circt::moore::AssignOp) ¶

Continuous assignment

Syntax:

operation ::= `moore.mir.assign` $dest `,` $src  attr-dict `:` qualified(type($src))

A SystemVerilog assignment statement ‘x = y;’. These occur in module scope. See SV Spec 10.3.2.

Operands: ¶

moore.mir.concat (::circt::moore::ConcatOp) ¶

A concatenation of expressions

Syntax:

operation ::= `moore.mir.concat` $values attr-dict `:` functional-type($values, $result)

This operation represents the SystemVerilog concatenation expression {x, y, z}. See IEEE 1800-2017 §11.4.12 “Concatenation operators”.

All operands must be simple bit vector types.

The concatenation result is a simple bit vector type. The result is unsigned regardless of the sign of the operands (see concatenation-specific rules in IEEE 1800-2017 §11.8.1 “Rules for expression types”). The size of the result is the sum of the sizes of all operands. If any of the operands is four-valued, the result is four-valued; otherwise it is two-valued.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Operands: ¶

Results: ¶

moore.mir.constant (::circt::moore::ConstantOp) ¶

A constant value

Syntax:

operation ::= `moore.mir.constant` $value attr-dict `:` qualified(type($result))

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes: ¶

Results: ¶

moore.mir.shl (::circt::moore::ShlOp) ¶

A logical or arithmetic left-shift expression

Syntax:

operation ::= `moore.mir.shl` ( `arithmetic` $arithmetic^ )? $value `,` $amount attr-dict
              `:` type($value) `,` type($amount)

This operation represents the SystemVerilog logical and arithmetic left-shift expressions << and <<<. See IEEE 1800-2017 §11.4.10 “Shift operators”.

The value to be shifted and the amount must be simple bit vector types. The shift result is of the same type as the input value.

The logical and arithmetic shift both insert zeros in place of the shifted bits.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes: ¶

Operands: ¶

Results: ¶

moore.mir.shr (::circt::moore::ShrOp) ¶

A logical or arithmetic right-shift expression

Syntax:

operation ::= `moore.mir.shr` ( `arithmetic` $arithmetic^ )? $value `,` $amount attr-dict
              `:` type($value) `,` type($amount)

This operation represents the SystemVerilog logical and arithmetic right-shift expressions >> and >>>. See IEEE 1800-2017 §11.4.10 “Shift operators”.

The value to be shifted and the amount must be simple bit vector types. The shift result is of the same type as the input value.

The logical shift always inserts zeros in place of the shifted bits. The arithmetic shift inserts zeros if the result type is unsigned or the MSB (sign bit) if the result type is signed.

Traits: AlwaysSpeculatableImplTrait

Interfaces: ConditionallySpeculatable, InferTypeOpInterface, NoMemoryEffect (MemoryEffectOpInterface)

Effects: MemoryEffects::Effect{}

Attributes: ¶

Operands: ¶

Results: ¶

moore.mir.vardecl (::circt::moore::VariableDeclOp) ¶

A variable declaration

Syntax:

operation ::= `moore.mir.vardecl` $name `=` $init attr-dict `:` custom<LValueType>(type($result))

Attributes: ¶

Results: ¶

Type constraint definition ¶

an SystemVerilog int ¶

packed type ¶

simple bit vector type ¶

unpacked type ¶

Type definition ¶

LValueType ¶

Syntax:

!moore.lvalue<
  ::mlir::Type   # nestedType
>

Parameters: ¶