'sv' Dialect
Types and operations for SV dialect
This dialect defines the sv
dialect, which represents various
SystemVerilog-specific constructs in an AST-like representation.
Attribute constraint definition ¶
Represents a reference to a macro identifier ¶
Defines direction in a modport ¶
validation qualifier type ¶
Attribute definition ¶
MacroIdentAttr ¶
Represents a reference to a macro identifier
Syntax:
!sv.macro.ident<
::mlir::StringAttr # ident
>
Parameters: ¶
Parameter | C++ type | Description |
---|---|---|
ident | ::mlir::StringAttr |
ModportDirectionAttr ¶
Defines direction in a modport
Syntax:
!sv.modport_direction<
::ModportDirection # value
>
Parameters: ¶
Parameter | C++ type | Description |
---|---|---|
value | ::ModportDirection | an enum of type ModportDirection |
ValidationQualifierTypeEnumAttr ¶
validation qualifier type
Syntax:
!sv.validation_qualifier<
::circt::sv::ValidationQualifierTypeEnum # value
>
Parameters: ¶
Parameter | C++ type | Description |
---|---|---|
value | ::circt::sv::ValidationQualifierTypeEnum | an enum of type ValidationQualifierTypeEnum |
Type constraint definition ¶
SystemVerilog interface type pointing to an InterfaceOp ¶
A MLIR type for the SV dialect’s InterfaceOp
to allow instances in any
dialect with an open type system. Points at the InterfaceOp which defines
the SystemVerilog interface.
SystemVerilog type pointing to an InterfaceModportOp ¶
A MLIR type for the SV dialect’s InterfaceModportOp
to allow
interactions with any open type system dialect. Points at the
InterfaceModportOp which defines the SystemVerilog interface’s modport.
Operation definition ¶
sv.alias
(::circt::sv::AliasOp) ¶
SystemVerilog ‘alias’ statement
Syntax:
operation ::= `sv.alias` $operands attr-dict `:` qualified(type($operands))
An alias statement declares multiple names for the same physical net, or bits within a net. Aliases always have at least two operands.
Operands: ¶
Operand | Description |
---|---|
operands | InOutType |
sv.alwayscomb
(::circt::sv::AlwaysCombOp) ¶
‘alwayscomb block
Syntax:
operation ::= `sv.alwayscomb` $body attr-dict
See SV Spec 9.2, and 9.2.2.2. Traits: NoRegionArguments, NoTerminator, NonProceduralOp, ProceduralRegion, RecursiveSideEffects, SingleBlock
sv.alwaysff
(::circt::sv::AlwaysFFOp) ¶
‘alwaysff @’ block with optional reset
Syntax:
operation ::= `sv.alwaysff` `(` $clockEdge $clock `)` $bodyBlk
( `(` $resetStyle `:` $resetEdge^ $reset `)` $resetBlk )? attr-dict
alwaysff blocks represent always_ff verilog nodes, which enforce inference of registers. This block takes a clock signal and edge sensitivity and reset type. If the reset type is anything but ‘noreset’, the block takes a reset signal, reset sensitivity, and reset block. Appropriate if conditions are generated in the output code based on the reset type. A negative-edge, asynchronous reset will check the inverse of the reset condition (if (!reset) begin resetblock end) to match the sensitivity.
Traits: NoRegionArguments, NoTerminator, NonProceduralOp, ProceduralRegion, RecursiveSideEffects, SingleBlock
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
clockEdge | circt::sv::EventControlAttr | edge control trigger |
resetStyle | ::ResetTypeAttr | reset type |
resetEdge | circt::sv::EventControlAttr | edge control trigger |
Operands: ¶
Operand | Description |
---|---|
clock | 1-bit signless integer |
reset | 1-bit signless integer |
sv.always
(::circt::sv::AlwaysOp) ¶
‘always @’ block
Syntax:
operation ::= `sv.always` custom<EventList>($events, $clocks) $body attr-dict
See SV Spec 9.2, and 9.4.2.2. Traits: NoRegionArguments, NoTerminator, NonProceduralOp, ProceduralRegion, RecursiveSideEffects, SingleBlock
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
events | ::mlir::ArrayAttr | events |
Operands: ¶
Operand | Description |
---|---|
clocks | 1-bit signless integer |
sv.array_index_inout
(::circt::sv::ArrayIndexInOutOp) ¶
Index an inout memory to produce an inout element
Syntax:
operation ::= `sv.array_index_inout` $input`[`$index`]` attr-dict `:` qualified(type($input)) `,` qualified(type($index))
See SV Spec 11.5.2. Interfaces: NoSideEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
input | an inout type with array element |
index | an integer bitvector of one or more bits |
Results: ¶
Result | Description |
---|---|
result | InOutType |
sv.assert.concurrent
(::circt::sv::AssertConcurrentOp) ¶
concurrent assertion statement, i.e., assert property
Syntax:
operation ::= `sv.assert.concurrent` $event $clock `,` $property
(`label` $label^)?
(`message` $message^ (`(` $operands^ `)` `:` qualified(type($operands)))?)?
attr-dict
Specify that a property of the hardware design is true whenever the property is evaluated. This can be used to both document the behavior of the design and to test that the design behaves as expected. See section 16.5 of the SystemVerilog 2017 specification.
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
event | circt::sv::EventControlAttr | edge control trigger |
label | ::mlir::StringAttr | string attribute |
message | ::mlir::StringAttr | string attribute |
Operands: ¶
Operand | Description |
---|---|
clock | 1-bit signless integer |
property | 1-bit signless integer |
operands | any type |
sv.assert
(::circt::sv::AssertOp) ¶
immediate assertion statement
Syntax:
operation ::= `sv.assert` $expression `,` $defer
(`label` $label^)?
(`message` $message^ (`(` $operands^ `)` `:` qualified(type($operands)))?)?
attr-dict
Specify that a Boolean expression is always true. This can be used to both document the behavior of the design and to test that the design behaves as expected. See Section 16.3 of the SystemVerilog 2017 specification.
Traits: ProceduralOp
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
defer | circt::sv::DeferAssertAttr | assertion deferring mode |
label | ::mlir::StringAttr | string attribute |
message | ::mlir::StringAttr | string attribute |
Operands: ¶
Operand | Description |
---|---|
expression | 1-bit signless integer |
operands | any type |
sv.interface.signal.assign
(::circt::sv::AssignInterfaceSignalOp) ¶
Assign an interfaces signal to some other signal.
Syntax:
operation ::= `sv.interface.signal.assign` $iface `(` custom<IfaceTypeAndSignal>(type($iface), $signalName) `)`
`=` $rhs attr-dict `:` qualified(type($rhs))
Use this to continuously assign a signal inside an interface to a value or other signal.
sv.interface.signal.assign %iface(@handshake_example::@data)
= %zero32 : i32
Would result in the following SystemVerilog:
assign iface.data = zero32;
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
signalName | ::mlir::FlatSymbolRefAttr | flat symbol reference attribute |
Operands: ¶
Operand | Description |
---|---|
iface | SystemVerilog interface type pointing to an InterfaceOp |
rhs | any type |
sv.assign
(::circt::sv::AssignOp) ¶
Continuous assignment
Syntax:
operation ::= `sv.assign` $dest `,` $src attr-dict `:` qualified(type($src))
A SystemVerilog assignment statement ‘x = y;'. These occur in module scope. See SV Spec 10.3.2.
Traits: NonProceduralOp
Operands: ¶
Operand | Description |
---|---|
dest | InOutType |
src | a valid inout element |
sv.assume.concurrent
(::circt::sv::AssumeConcurrentOp) ¶
concurrent assume statement, i.e., assume property
Syntax:
operation ::= `sv.assume.concurrent` $event $clock `,` $property
(`label` $label^)?
(`message` $message^ (`(` $operands^ `)` `:` qualified(type($operands)))?)?
attr-dict
Specify that a property is assumed to be true whenever the property is evaluated. This can be used to both document the behavior of the design and to test that the design behaves as expected. See section 16.5 of the SystemVerilog 2017 specification.
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
event | circt::sv::EventControlAttr | edge control trigger |
label | ::mlir::StringAttr | string attribute |
message | ::mlir::StringAttr | string attribute |
Operands: ¶
Operand | Description |
---|---|
clock | 1-bit signless integer |
property | 1-bit signless integer |
operands | any type |
sv.assume
(::circt::sv::AssumeOp) ¶
immediate assume statement
Syntax:
operation ::= `sv.assume` $expression `,` $defer
(`label` $label^)?
(`message` $message^ (`(` $operands^ `)` `:` qualified(type($operands)))?)?
attr-dict
Specify that a Boolean expression is assumed to always be true. This can either be used as an assertion-like check that the expression is, in fact, always true or to bound legal input values during testing. See Section 16.3 of the SystemVerilog 2017 specification.
Traits: ProceduralOp
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
defer | circt::sv::DeferAssertAttr | assertion deferring mode |
label | ::mlir::StringAttr | string attribute |
message | ::mlir::StringAttr | string attribute |
Operands: ¶
Operand | Description |
---|---|
expression | 1-bit signless integer |
operands | any type |
sv.bpassign
(::circt::sv::BPAssignOp) ¶
Blocking procedural assignment
Syntax:
operation ::= `sv.bpassign` $dest `,` $src attr-dict `:` qualified(type($src))
A SystemVerilog blocking procedural assignment statement ‘x = y;'. These occur in initial, always, task, and function blocks. The statement is executed before any following statements are. See SV Spec 10.4.1.
Traits: ProceduralOp
Operands: ¶
Operand | Description |
---|---|
dest | InOutType |
src | a valid inout element |
sv.bind.interface
(::circt::sv::BindInterfaceOp) ¶
indirectly instantiate an interface
Syntax:
operation ::= `sv.bind.interface` $instance attr-dict
Indirectly instantiate an interface in the context of another module. This
operation must pair with a sv.interface.instance
.
Interfaces: SymbolUserOpInterface
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
instance | ::circt::hw::InnerRefAttr | Refer to a name inside a module |
sv.bind
(::circt::sv::BindOp) ¶
indirect instantiation statement
Syntax:
operation ::= `sv.bind` $instance attr-dict
Indirectly instantiate a module from the context of another module. BindOp
pairs with a hw.instance
(identified by a boundInstance
symbol) which
tracks all information except the emission point for the bind. BindOp also
tracks the instanceModule
symbol for the hw.module
that contains the
hw.instance
to accelerate symbol lookup.
See 23.11 of SV 2017 spec for more information about bind.
Interfaces: SymbolUserOpInterface
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
instance | ::circt::hw::InnerRefAttr | Refer to a name inside a module |
sv.case
(::circt::sv::CaseOp) ¶
‘case (cond)’ block
See SystemVerilog 2017 12.5. Traits: NoRegionArguments, NoTerminator, ProceduralOp, ProceduralRegion, SingleBlock
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
caseStyle | ::CaseStmtTypeAttr | case type |
casePatterns | ::mlir::ArrayAttr | array attribute |
validationQualifier | ::circt::sv::ValidationQualifierTypeEnumAttr | validation qualifier type |
Operands: ¶
Operand | Description |
---|---|
cond | an integer bitvector of one or more bits |
sv.constantX
(::circt::sv::ConstantXOp) ¶
A constant of value ‘x’
Syntax:
operation ::= `sv.constantX` attr-dict `:` qualified(type($result))
This operation produces a constant value of ‘x’. This ‘x’ follows the System Verilog rules for ‘x’ propagation.
Interfaces: HasCustomSSAName, NoSideEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Results: ¶
Result | Description |
---|---|
result | a known primitive element |
sv.constantZ
(::circt::sv::ConstantZOp) ¶
A constant of value ‘z’
Syntax:
operation ::= `sv.constantZ` attr-dict `:` qualified(type($result))
This operation produces a constant value of ‘z’. This ‘z’ follows the System Verilog rules for ‘z’ propagation.
Interfaces: HasCustomSSAName, NoSideEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Results: ¶
Result | Description |
---|---|
result | a known primitive element |
sv.cover.concurrent
(::circt::sv::CoverConcurrentOp) ¶
concurrent cover statement, i.e., cover property
Syntax:
operation ::= `sv.cover.concurrent` $event $clock `,` $property
(`label` $label^)?
(`message` $message^ (`(` $operands^ `)` `:` qualified(type($operands)))?)?
attr-dict
Specify that a specific property should be monitored for coverage, i.e., a simulation will watch if it occurrs and how many times it occurs. See section 16.5 of the SystemVerilog 2017 specification.
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
event | circt::sv::EventControlAttr | edge control trigger |
label | ::mlir::StringAttr | string attribute |
message | ::mlir::StringAttr | string attribute |
Operands: ¶
Operand | Description |
---|---|
clock | 1-bit signless integer |
property | 1-bit signless integer |
operands | any type |
sv.cover
(::circt::sv::CoverOp) ¶
immediate cover statement
Syntax:
operation ::= `sv.cover` $expression `,` $defer
(`label` $label^)?
(`message` $message^ (`(` $operands^ `)` `:` qualified(type($operands)))?)?
attr-dict
Specify that a Boolean expression should be monitored for coverage, i.e., a simulator will watch if it occurs and how many times it occurs. See section 16.3 of the SystemVerilog 2017 specification.
Traits: ProceduralOp
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
defer | circt::sv::DeferAssertAttr | assertion deferring mode |
label | ::mlir::StringAttr | string attribute |
message | ::mlir::StringAttr | string attribute |
Operands: ¶
Operand | Description |
---|---|
expression | 1-bit signless integer |
operands | any type |
sv.nonstandard.deposit
(::circt::sv::DepositOp) ¶
$deposit
system task
Syntax:
operation ::= `sv.nonstandard.deposit` $dest `,` $src attr-dict `:` qualified(type($src))
This system task sets the value of a net or variable, but doesn’t hold it. This is a common simulation vendor extension.
Traits: ProceduralOp, VendorExtension
Operands: ¶
Operand | Description |
---|---|
dest | InOutType |
src | a valid inout element |
sv.error
(::circt::sv::ErrorOp) ¶
$error
severity message task
Syntax:
operation ::= `sv.error` ($message^ (`(` $operands^ `)` `:` qualified(type($operands)))?)?
attr-dict
This system task indicates a run-time error.
If present, the optional message is printed with any additional operands interpolated into the message string.
Traits: ProceduralOp
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
message | ::mlir::StringAttr | string attribute |
Operands: ¶
Operand | Description |
---|---|
operands | any type |
sv.exit
(::circt::sv::ExitOp) ¶
$exit
system task
Syntax:
operation ::= `sv.exit` attr-dict
Waits for all program
blocks to complete and then makes an implicit call
to $finish
with default verbosity (level 1) to conclude the simulation.
Traits: ProceduralOp
sv.fwrite
(::circt::sv::FWriteOp) ¶
‘$fwrite’ statement
Syntax:
operation ::= `sv.fwrite` $fd `,` $string attr-dict (`(` $operands^ `)` `:` qualified(type($operands)))?
Traits: ProceduralOp
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
string | ::mlir::StringAttr | string attribute |
Operands: ¶
Operand | Description |
---|---|
fd | 32-bit signless integer |
operands | any type |
sv.fatal
(::circt::sv::FatalOp) ¶
$fatal
severity message task
Syntax:
operation ::= `sv.fatal` $verbosity
(`,` $message^ (`(` $operands^ `)` `:` qualified(type($operands)))?)?
attr-dict
Generates a run-time fatal error which terminates the simulation with an
error code. Makes an implicit call to $finish
, forwarding the verbosity
operand. If present, the optional message is printed with any additional
operands interpolated into the message string.
Traits: ProceduralOp
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
verbosity | ::mlir::IntegerAttr | 8-bit signless integer attribute whose minimum value is 0 whose maximum value is 2 |
message | ::mlir::StringAttr | string attribute |
Operands: ¶
Operand | Description |
---|---|
operands | any type |
sv.finish
(::circt::sv::FinishOp) ¶
$finish
system task
Syntax:
operation ::= `sv.finish` $verbosity attr-dict
Stops the simulation and exits/terminates the simulator process. In practice most GUI-based simulators will show a prompt to the user offering them an opportunity to not close the simulator altogether.
Other tasks such as $exit
or $fatal
implicitly call this system task.
The optional verbosity
parameter controls how much diagnostic information
is printed when the system task is executed (see section 20.2 of IEEE
1800-2017):
0
: Prints nothing1
: Prints simulation time and location (default)2
: Prints simulation time, location, and statistics about the memory and CPU time used in simulation
Traits: ProceduralOp
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
verbosity | ::mlir::IntegerAttr | 8-bit signless integer attribute whose minimum value is 0 whose maximum value is 2 |
sv.force
(::circt::sv::ForceOp) ¶
Force procedural statement
Syntax:
operation ::= `sv.force` $dest `,` $src attr-dict `:` qualified(type($src))
A SystemVerilog force procedural statement ‘force x = y;'. These occur in initial, always, task, and function blocks. A force statement shall override a procedural assignment until a release statement is executed on the variable. The left-hand side of the assignment can be avariable, a net, a constant bit-select of a vector net, a part-select of a vector net or a concatenation. It cannot be a memory word or a bit-select or part-select of a vector variable. See SV Spec 10.6.2.
Traits: ProceduralOp
Operands: ¶
Operand | Description |
---|---|
dest | InOutType |
src | a valid inout element |
sv.modport.get
(::circt::sv::GetModportOp) ¶
Get a modport out of an interface instance
Syntax:
operation ::= `sv.modport.get` $iface $field attr-dict `:` qualified(type($iface)) `->` qualified(type($result))
Use this to extract a modport view to an instantiated interface. For example, to get the ‘dataflow_in’ modport on the ‘handshake_example’ interface:
%ifaceModport = sv.modport.get @dataflow_in %iface :
!sv.interface<@handshake_example> ->
!sv.modport<@handshake_example::@dataflow_in>
Interfaces: NoSideEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
field | ::mlir::FlatSymbolRefAttr | flat symbol reference attribute |
Operands: ¶
Operand | Description |
---|---|
iface | SystemVerilog interface type pointing to an InterfaceOp |
Results: ¶
Result | Description |
---|---|
result | SystemVerilog type pointing to an InterfaceModportOp |
sv.ifdef
(::circt::sv::IfDefOp) ¶
‘ifdef MACRO’ block
Syntax:
operation ::= `sv.ifdef` $cond $thenRegion (`else` $elseRegion^)? attr-dict
This operation is an #ifdef block, which has a “then” and “else” region. This operation is for non-procedural regions and its body is non-procedural.
Traits: NoRegionArguments, NoTerminator, NonProceduralOp, SingleBlock
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
cond | ::circt::sv::MacroIdentAttr | Represents a reference to a macro identifier |
sv.ifdef.procedural
(::circt::sv::IfDefProceduralOp) ¶
‘ifdef MACRO’ block for procedural regions
Syntax:
operation ::= `sv.ifdef.procedural` $cond $thenRegion (`else` $elseRegion^)? attr-dict
This operation is an #ifdef block, which has a “then” and “else” region. This operation is for procedural regions and its body is procedural.
Traits: NoRegionArguments, NoTerminator, ProceduralOp, ProceduralRegion, SingleBlock
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
cond | ::circt::sv::MacroIdentAttr | Represents a reference to a macro identifier |
sv.if
(::circt::sv::IfOp) ¶
‘if (cond)’ block
Syntax:
operation ::= `sv.if` $cond $thenRegion (`else` $elseRegion^)? attr-dict
Traits: NoRegionArguments, NoTerminator, ProceduralOp, ProceduralRegion, SingleBlock
Operands: ¶
Operand | Description |
---|---|
cond | 1-bit signless integer |
sv.indexed_part_select_inout
(::circt::sv::IndexedPartSelectInOutOp) ¶
Address several contiguous bits of an inout type (e.g. a wire or inout port). This is an indexed part-select operator.The base is an integer expression and the width is an integer constant. The bits start from base and the number of bits selected is equal to width. If $decrement is true, then part select decrements starting from $base.See SV Spec 11.5.1.
Syntax:
operation ::= `sv.indexed_part_select_inout` $input`[`$base (`decrement` $decrement^)?`:` $width`]` attr-dict `:` qualified(type($input)) `,` qualified(type($base))
Interfaces: InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
width | ::mlir::IntegerAttr | 32-bit signless integer attribute |
decrement | ::mlir::UnitAttr | unit attribute |
Operands: ¶
Operand | Description |
---|---|
input | InOutType |
base | an integer bitvector of one or more bits |
Results: ¶
Result | Description |
---|---|
result | InOutType |
sv.indexed_part_select
(::circt::sv::IndexedPartSelectOp) ¶
Read several contiguous bits of an int type.This is an indexed part-select operator.The base is an integer expression and the width is an integer constant. The bits start from base and the number of bits selected is equal to width. If $decrement is true, then part select decrements starting from $base.See SV Spec 11.5.1.
Syntax:
operation ::= `sv.indexed_part_select` $input`[`$base (`decrement` $decrement^)?`:` $width`]` attr-dict `:` qualified(type($input)) `,` qualified(type($base))
Interfaces: InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
width | ::mlir::IntegerAttr | 32-bit signless integer attribute |
decrement | ::mlir::UnitAttr | unit attribute |
Operands: ¶
Operand | Description |
---|---|
input | an integer bitvector of one or more bits |
base | an integer bitvector of one or more bits |
Results: ¶
Result | Description |
---|---|
result | an integer bitvector of one or more bits |
sv.info
(::circt::sv::InfoOp) ¶
$info
severity message task
Syntax:
operation ::= `sv.info` ($message^ (`(` $operands^ `)` `:` qualified(type($operands)))?)?
attr-dict
This system task indicates a message with no specific severity.
If present, the optional message is printed with any additional operands interpolated into the message string.
Traits: ProceduralOp
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
message | ::mlir::StringAttr | string attribute |
Operands: ¶
Operand | Description |
---|---|
operands | any type |
sv.initial
(::circt::sv::InitialOp) ¶
‘initial’ block
Syntax:
operation ::= `sv.initial` $body attr-dict
See SV Spec 9.2.1. Traits: NoRegionArguments, NoTerminator, NonProceduralOp, ProceduralRegion, RecursiveSideEffects, SingleBlock
sv.interface.instance
(::circt::sv::InterfaceInstanceOp) ¶
Instantiate an interface
Syntax:
operation ::= `sv.interface.instance` (`sym` $inner_sym^)? custom<ImplicitSSAName>(attr-dict)
`:` qualified(type($result))
Use this to declare an instance of an interface:
%iface = sv.interface.instance : !sv.interface<@handshake_example>
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
name | ::mlir::StringAttr | string attribute |
inner_sym | ::mlir::StringAttr | string attribute |
Results: ¶
Result | Description |
---|---|
result | SystemVerilog interface type pointing to an InterfaceOp |
sv.interface.modport
(::circt::sv::InterfaceModportOp) ¶
Operation to define a SystemVerilog modport for interfaces
Syntax:
operation ::= `sv.interface.modport` attr-dict $sym_name custom<ModportStructs>($ports)
This operation defines a named modport within an interface. Its name is a symbol that can be looked up inside its parent interface. There is an array of structs that contains two fields: an enum to indicate the direction of the signal in the modport, and a symbol reference to refer to the signal.
Example:
sv.interface.modport @input_port (input @data)
sv.interface.modport @output_port (output @data)
Traits: HasParent
Interfaces: Symbol
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
sym_name | ::mlir::StringAttr | string attribute |
ports | ::mlir::ArrayAttr | array of modport structs |
sv.interface
(::circt::sv::InterfaceOp) ¶
Operation to define a SystemVerilog interface
Syntax:
operation ::= `sv.interface` attr-dict $sym_name $body
This operation defines a named interface. Its name is a symbol that can be looked up when declared inside a SymbolTable operation. This operation is also a SymbolTable itself, so the symbols in its region can be looked up.
Example:
sv.interface @myinterface {
sv.interface.signal @data : i32
sv.interface.modport @input_port (input @data)
sv.interface.modport @output_port (output @data)
}
Traits: NoTerminator, SingleBlock, SymbolTable
Interfaces: Symbol
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
sym_name | ::mlir::StringAttr | string attribute |
sv.interface.signal
(::circt::sv::InterfaceSignalOp) ¶
Operation to define a SystemVerilog signal for interfaces
Syntax:
operation ::= `sv.interface.signal` attr-dict $sym_name `:` $type
This operation defines a named signal within an interface. Its type is specified in an attribute, and currently supports IntegerTypes.
Example:
sv.interface.signal @data : i32
Traits: HasParent
Interfaces: Symbol
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
sym_name | ::mlir::StringAttr | string attribute |
type | ::mlir::TypeAttr | Any SV/HW type |
sv.localparam
(::circt::sv::LocalParamOp) ¶
Declare a localparam
Syntax:
operation ::= `sv.localparam` `:` qualified(type($result)) custom<ImplicitSSAName>(attr-dict)
The localparam operation produces a localparam
declaration. See SV spec
6.20.4 p125.
Traits: FirstAttrDerivedResultType
Interfaces: HasCustomSSAName, NoSideEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
value | ::mlir::Attribute | any attribute |
name | ::mlir::StringAttr | string attribute |
Results: ¶
Result | Description |
---|---|
result | a known primitive element |
sv.macro.ref
(::circt::sv::MacroRefExprOp) ¶
Expression to refer to a SystemVerilog macro
Syntax:
operation ::= `sv.macro.ref` `<` $ident `>` attr-dict `:` qualified(type($result))
This operation produces a value by referencing a named macro.
Presently, it is assumed that the referenced macro is a constant with no side effects. This expression is subject to CSE. It can be duplicated and emitted inline by the Verilog emitter.
Interfaces: HasCustomSSAName, NoSideEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
ident | ::circt::sv::MacroIdentAttr | Represents a reference to a macro identifier |
Results: ¶
Result | Description |
---|---|
result | a known primitive element or InOutType |
sv.passign
(::circt::sv::PAssignOp) ¶
Nonblocking procedural assignment
Syntax:
operation ::= `sv.passign` $dest `,` $src attr-dict `:` qualified(type($src))
A SystemVerilog nonblocking procedural assignment statement ‘x <= y;'. These occur in initial, always, task, and function blocks. The statement can be scheduled without blocking procedural flow. See SV Spec 10.4.2.
Traits: ProceduralOp
Operands: ¶
Operand | Description |
---|---|
dest | InOutType |
src | a valid inout element |
sv.read_inout
(::circt::sv::ReadInOutOp) ¶
Get the value of from something of inout type (e.g. a wire or inout port) as the value itself.
Syntax:
operation ::= `sv.read_inout` $input attr-dict `:` qualified(type($input))
Interfaces: NoSideEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Operands: ¶
Operand | Description |
---|---|
input | InOutType |
Results: ¶
Result | Description |
---|---|
result | a known primitive element |
sv.interface.signal.read
(::circt::sv::ReadInterfaceSignalOp) ¶
Access the data in an interface’s signal.
Syntax:
operation ::= `sv.interface.signal.read` $iface `(` custom<IfaceTypeAndSignal>(type($iface), $signalName) `)`
attr-dict `:` qualified(type($signalData))
This is an expression to access a signal inside of an interface.
%ifaceData = sv.interface.signal.read %iface
(@handshake_example::@data) : i32
Could result in the following SystemVerilog:
wire [31:0] ifaceData = iface.data;
Interfaces: NoSideEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
signalName | ::mlir::FlatSymbolRefAttr | flat symbol reference attribute |
Operands: ¶
Operand | Description |
---|---|
iface | SystemVerilog interface type pointing to an InterfaceOp |
Results: ¶
Result | Description |
---|---|
signalData | any type |
sv.reg
(::circt::sv::RegOp) ¶
Define a new reg
in SystemVerilog
Syntax:
operation ::= `sv.reg` (`sym` $inner_sym^)? custom<ImplicitSSAName>(attr-dict)
`:` qualified(type($result))
Declare a SystemVerilog Variable Declaration of ‘reg’ type. See SV Spec 6.8, pp100.
Interfaces: OpAsmOpInterface
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
name | ::mlir::StringAttr | string attribute |
inner_sym | ::mlir::StringAttr | string attribute |
Results: ¶
Result | Description |
---|---|
result | InOutType |
sv.release
(::circt::sv::ReleaseOp) ¶
Release procedural statement
Syntax:
operation ::= `sv.release` $dest attr-dict `:` qualified(type($dest))
Release is used in conjunction with force. When released, then if the variable does not currently have an active assign procedural continuous assignment, the variable shall not immediately change value. The variable shall maintain its current value until the next procedural assignment or procedural continuous assignment to the variable. Releasing a variable that currently has an active assign procedural continuous assignment shall immediately reestablish that assignment. See SV Spec 10.6.2.
Traits: ProceduralOp
Operands: ¶
Operand | Description |
---|---|
dest | InOutType |
sv.system.sampled
(::circt::sv::SampledOp) ¶
$sampled
system function to sample a value
Syntax:
operation ::= `sv.system.sampled` $expression attr-dict `:` qualified(type($expression))
Sample a value using System Verilog sampling semantics (see Section 16.5.1 of the SV 2017 specification for more information).
A use of $sampled
is to safely read the value of a net/variable in a
concurrent assertion action block such that the value will be the same as
the value used when the assertion is triggered. See Section 16.9.3 of the
SV 2017 specification for more information.
Traits: SameOperandsAndResultType
Interfaces: InferTypeOpInterface
Operands: ¶
Operand | Description |
---|---|
expression | any type |
Results: ¶
Result | Description |
---|---|
sampledValue | any type |
sv.stop
(::circt::sv::StopOp) ¶
$stop
system task
Syntax:
operation ::= `sv.stop` $verbosity attr-dict
Causes the simulation to be suspended. Does not terminate the simulator.
The optional verbosity
parameter controls how much diagnostic information
is printed when the system task is executed (see section 20.2 of IEEE
1800-2017):
0
: Prints nothing1
: Prints simulation time and location (default)2
: Prints simulation time, location, and statistics about the memory and CPU time used in simulation
Traits: ProceduralOp
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
verbosity | ::mlir::IntegerAttr | 8-bit signless integer attribute whose minimum value is 0 whose maximum value is 2 |
sv.struct_field_inout
(::circt::sv::StructFieldInOutOp) ¶
Create an subfield inout memory to produce an inout element.
Syntax:
operation ::= `sv.struct_field_inout` $input `[` $field `]` attr-dict `:` qualified(type($input))
See SV Spec 7.2. Interfaces: InferTypeOpInterface, NoSideEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
field | ::mlir::StringAttr | string attribute |
Operands: ¶
Operand | Description |
---|---|
input | an inout type with struct field |
Results: ¶
Result | Description |
---|---|
result | InOutType |
sv.verbatim.expr
(::circt::sv::VerbatimExprOp) ¶
Expression that expands to a value given SystemVerilog text
Syntax:
operation ::= `sv.verbatim.expr` $string (`(` $operands^ `)`)?
`:` functional-type($operands, $result) attr-dict
This operation produces a typed value expressed by a string of SystemVerilog. This can be used to access macros and other values that are only sensible as Verilog text.
The text string is expected to have the highest precedence, so you should include parentheses in the string if it isn’t a single token. This is also assumed to not have side effects (use sv.verbatim.expr.se) if you need them.
sv.verbatim.expr allows operand substitutions with {{0}} syntax.
Interfaces: HasCustomSSAName, NoSideEffect (MemoryEffectOpInterface)
Effects: MemoryEffects::Effect{}
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
string | ::mlir::StringAttr | string attribute |
symbols | ::mlir::ArrayAttr | name reference array attribute |
Operands: ¶
Operand | Description |
---|---|
operands | any type |
Results: ¶
Result | Description |
---|---|
result | a known primitive element or InOutType |
sv.verbatim.expr.se
(::circt::sv::VerbatimExprSEOp) ¶
Expression that expands to a value given SystemVerilog text
Syntax:
operation ::= `sv.verbatim.expr.se` $string (`(` $operands^ `)`)?
`:` functional-type($operands, $result) attr-dict
This operation produces a typed value expressed by a string of SystemVerilog. This can be used to access macros and other values that are only sensible as Verilog text.
The text string is expected to have the highest precedence, so you should include parentheses in the string if it isn’t a single token. This is allowed to have side effects.
sv.verbatim.se.expr allows operand substitutions with {{0}} syntax.
Interfaces: HasCustomSSAName
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
string | ::mlir::StringAttr | string attribute |
symbols | ::mlir::ArrayAttr | name reference array attribute |
Operands: ¶
Operand | Description |
---|---|
operands | any type |
Results: ¶
Result | Description |
---|---|
result | a known primitive element or InOutType |
sv.verbatim
(::circt::sv::VerbatimOp) ¶
Verbatim opaque text emitted inline.
Syntax:
operation ::= `sv.verbatim` $string (`(` $operands^ `)` `:` qualified(type($operands)))? attr-dict
This operation produces opaque text inline in the SystemVerilog output.
sv.verbatim allows operand substitutions with {{0}} syntax.
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
string | ::mlir::StringAttr | string attribute |
symbols | ::mlir::ArrayAttr | name reference array attribute |
Operands: ¶
Operand | Description |
---|---|
operands | any type |
sv.warning
(::circt::sv::WarningOp) ¶
$warning
severity message task
Syntax:
operation ::= `sv.warning` ($message^ (`(` $operands^ `)` `:` qualified(type($operands)))?)?
attr-dict
This system task indicates a run-time warning.
If present, the optional message is printed with any additional operands interpolated into the message string.
Traits: ProceduralOp
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
message | ::mlir::StringAttr | string attribute |
Operands: ¶
Operand | Description |
---|---|
operands | any type |
sv.wire
(::circt::sv::WireOp) ¶
Define a new wire
Syntax:
operation ::= `sv.wire` (`sym` $inner_sym^)? custom<ImplicitSSAName>(attr-dict)
`:` qualified(type($result))
Declare a SystemVerilog Net Declaration of ‘wire’ type. See SV Spec 6.7, pp97.
Traits: NonProceduralOp
Interfaces: OpAsmOpInterface
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
name | ::mlir::StringAttr | string attribute |
inner_sym | ::mlir::StringAttr | string attribute |
Results: ¶
Result | Description |
---|---|
result | InOutType |
sv.xmr
(::circt::sv::XMROp) ¶
Encode a reference to a non-local net.
Syntax:
operation ::= `sv.xmr` (`isRooted` $isRooted^)? custom<XMRPath>($path, $terminal) attr-dict `:` qualified(type($result))
This represents a non-local hierarchical name to a net, sometimes called a cross-module reference. A hierarchical name may be absolute, when prefixed with ‘$root’, in which case it is resolved from the set of top-level modules (any non-instantiated modules). Non-absolute paths are resolved by attempting resolution of the path locally, then recursively up the instance graph. See SV Spec 23.6, pp721.
It is impossible to completely resolve a hierarchical name without making a closed-world assumption in the compiler. We therefore don’t try to link hierarchical names to what they resolve to at compile time. A frontend generating this op should ensure that any instance or object in the intended path has public visibility so paths are not invalidated.
Attributes: ¶
Attribute | MLIR Type | Description |
---|---|---|
isRooted | ::mlir::UnitAttr | unit attribute |
path | ::mlir::ArrayAttr | string array attribute |
terminal | ::mlir::StringAttr | string attribute |
Results: ¶
Result | Description |
---|---|
result | InOutType |
Type definition ¶
InterfaceType ¶
SystemVerilog interface type pointing to an InterfaceOp
Syntax:
!sv.interface<
::mlir::FlatSymbolRefAttr # interface
>
A MLIR type for the SV dialect’s InterfaceOp
to allow instances in any
dialect with an open type system. Points at the InterfaceOp which defines
the SystemVerilog interface.
Parameters: ¶
Parameter | C++ type | Description |
---|---|---|
interface | ::mlir::FlatSymbolRefAttr |
ModportType ¶
SystemVerilog type pointing to an InterfaceModportOp
Syntax:
!sv.modport<
::mlir::SymbolRefAttr # modport
>
A MLIR type for the SV dialect’s InterfaceModportOp
to allow
interactions with any open type system dialect. Points at the
InterfaceModportOp which defines the SystemVerilog interface’s modport.
Parameters: ¶
Parameter | C++ type | Description |
---|---|---|
modport | ::mlir::SymbolRefAttr |