'sv' Dialect

Types and operations for SV dialect This dialect defines the sv dialect, which represents various SystemVerilog-specific constructs in an AST-like representation.

Attribute definition ¶

VerbatimParameterAttr ¶

Represents text to emit directly to SystemVerilog

Parameters: ¶

Type constraint definition ¶

SystemVerilog interface type pointing to an InterfaceOp ¶

A MLIR type for the SV dialect’s InterfaceOp to allow instances in any dialect with an open type system. Points at the InterfaceOp which defines the SystemVerilog interface.

SystemVerilog type pointing to an InterfaceModportOp ¶

A MLIR type for the SV dialect’s InterfaceModportOp to allow interactions with any open type system dialect. Points at the InterfaceModportOp which defines the SystemVerilog interface’s modport.

Operation definition ¶

sv.alias (::circt::sv::AliasOp) ¶

SystemVerilog ‘alias’ statement

Syntax:

operation ::= `sv.alias` $operands attr-dict `:` type($operands)

An alias statement declares multiple names for the same physical net, or bits within a net. Aliases always have at least two operands.

Operands: ¶

sv.alwayscomb (::circt::sv::AlwaysCombOp) ¶

‘alwayscomb block

Syntax:

operation ::= `sv.alwayscomb` $body attr-dict

See SV Spec 9.2, and 9.2.2.2.

sv.alwaysff (::circt::sv::AlwaysFFOp) ¶

‘alwaysff @’ block with optional reset

Syntax:

operation ::= `sv.alwaysff` `(` $clockEdge $clock `)` $bodyBlk
              ( `(` $resetStyle `:` $resetEdge^ $reset `)` $resetBlk )? attr-dict

alwaysff blocks represent always_ff verilog nodes, which enforce inference of registers. This block takes a clock signal and edge sensitivity and reset type. If the reset type is anything but ‘noreset’, the block takes a reset signal, reset sensitivity, and reset block. Appropriate if conditions are generated in the output code based on the reset type. A negative-edge, asynchronous reset will check the inverse of the reset condition (if (!reset) begin resetblock end) to match the sensitivity.

Attributes: ¶

Operands: ¶

sv.always (::circt::sv::AlwaysOp) ¶

‘always @’ block

Syntax:

operation ::= `sv.always` custom<EventList>($events, $clocks) $body attr-dict

See SV Spec 9.2, and 9.4.2.2.

Attributes: ¶

Operands: ¶

sv.array_index_inout (::circt::sv::ArrayIndexInOutOp) ¶

Index an inout memory to produce an inout element

Syntax:

operation ::= `sv.array_index_inout` $input`[`$index`]` attr-dict `:` type($input) `,` type($index)

See SV Spec 11.5.2.

Operands: ¶

Results: ¶

sv.assert.concurrent (::circt::sv::AssertConcurrentOp) ¶

concurrent assertion statement, i.e., assert property

Syntax:

operation ::= `sv.assert.concurrent` custom<OmitEmptyStringAttr>($label) $event $clock $property attr-dict `:` type($property)

Specify that a property of the hardware design is true whenever the property is evaluated. This can be used to both document the behavior of the design and to test that the design behaves as expected. See section 16.5 of the SystemVerilog 2017 specification.

Attributes: ¶

Operands: ¶

sv.assert (::circt::sv::AssertOp) ¶

immediate assertion statement

Syntax:

operation ::= `sv.assert` custom<OmitEmptyStringAttr>($label) attr-dict $expression `:` type($expression)

Specify that a Boolean expression is always true. This can be used to both document the behavior of the design and to test that the design behaves as expected. See Section 16.3 of the SystemVerilog 2017 specification.

Attributes: ¶

Operands: ¶

sv.interface.signal.assign (::circt::sv::AssignInterfaceSignalOp) ¶

Assign an interfaces signal to some other signal.

Syntax:

operation ::= `sv.interface.signal.assign` $iface `(` custom<IfaceTypeAndSignal>(type($iface), $signalName) `)`
              `=` $rhs attr-dict `:` type($rhs)

Use this to continuously assign a signal inside an interface to a value or other signal.

  sv.interface.signal.assign %iface(@handshake_example::@data)
    = %zero32 : i32

Would result in the following SystemVerilog:

  assign iface.data = zero32;

Attributes: ¶

Operands: ¶

sv.assign (::circt::sv::AssignOp) ¶

Continuous assignment

Syntax:

operation ::= `sv.assign` $dest `,` $src  attr-dict `:` type($src)

A SystemVerilog assignment statement ‘x = y;'. These occur in module scope. See SV Spec 10.3.2.

Operands: ¶

sv.assume.concurrent (::circt::sv::AssumeConcurrentOp) ¶

concurrent assume statement, i.e., assume property

Syntax:

operation ::= `sv.assume.concurrent` custom<OmitEmptyStringAttr>($label) $event $clock $property attr-dict `:` type($property)

Specify that a property is assumed to be true whenever the property is evaluated. This can be used to both document the behavior of the design and to test that the design behaves as expected. See section 16.5 of the SystemVerilog 2017 specification.

Attributes: ¶

Operands: ¶

sv.assume (::circt::sv::AssumeOp) ¶

immediate assume statement

Syntax:

operation ::= `sv.assume` custom<OmitEmptyStringAttr>($label) attr-dict $expression `:` type($expression)

Specify that a Boolean expression is assumed to always be true. This can either be used as an assertion-like check that the expression is, in fact, always true or to bound legal input values during testing. See Section 16.3 of the SystemVerilog 2017 specification.

Attributes: ¶

Operands: ¶

sv.bpassign (::circt::sv::BPAssignOp) ¶

Blocking procedural assignment

Syntax:

operation ::= `sv.bpassign` $dest `,` $src  attr-dict `:` type($src)

A SystemVerilog blocking procedural assignment statement ‘x = y;'. These occur in initial, always, task, and function blocks. The statement is executed before any following statements are. See SV Spec 10.4.1.

Operands: ¶

sv.bind.interface (::circt::sv::BindInterfaceOp) ¶

indirectly instantiate an interface

Syntax:

operation ::= `sv.bind.interface` $interface attr-dict

Indirectly instantiate an interface in the context of another module. This operation must pair with a sv.interface.instance.

Attributes: ¶

sv.bind (::circt::sv::BindOp) ¶

indirect instantiation statement

Syntax:

operation ::= `sv.bind` $boundInstance `in` $instanceModule attr-dict

Indirectly instantiate a module from the context of another module. BindOp pairs with a hw.instance (identified by a boundInstance symbol) which tracks all information except the emission point for the bind. BindOp also tracks the instanceModule symbol for the hw.module that contains the hw.instance to accelerate symbol lookup.

See 23.11 of SV 2017 spec for more information about bind.

Attributes: ¶

sv.casez (::circt::sv::CaseZOp) ¶

‘casez (cond)’ block

See SystemVerilog 2017 12.5.1.

Attributes: ¶

Operands: ¶

sv.constantX (::circt::sv::ConstantXOp) ¶

A constant of value ‘x’

Syntax:

operation ::= `sv.constantX` attr-dict `:` type($result)

This operation produces a constant value of ‘x’. This ‘x’ follows the System Verilog rules for ‘x’ propagation.

Results: ¶

sv.constantZ (::circt::sv::ConstantZOp) ¶

A constant of value ‘z’

Syntax:

operation ::= `sv.constantZ` attr-dict `:` type($result)

This operation produces a constant value of ‘z’. This ‘z’ follows the System Verilog rules for ‘z’ propagation.

Results: ¶

sv.cover.concurrent (::circt::sv::CoverConcurrentOp) ¶

concurrent cover statement, i.e., cover property

Syntax:

operation ::= `sv.cover.concurrent` custom<OmitEmptyStringAttr>($label) $event $clock $property attr-dict `:` type($property)

Specify that a specific property should be monitored for coverage, i.e., a simulation will watch if it occurrs and how many times it occurs. See section 16.5 of the SystemVerilog 2017 specification.

Attributes: ¶

Operands: ¶

sv.cover (::circt::sv::CoverOp) ¶

immediate cover statement

Syntax:

operation ::= `sv.cover` custom<OmitEmptyStringAttr>($label) attr-dict $expression `:` type($expression)

Specify that a Boolean expression should be monitored for coverage, i.e., a simulator will watch if it occurs and how many times it occurs. See section 16.3 of the SystemVerilog 2017 specification.

Attributes: ¶

Operands: ¶

sv.fwrite (::circt::sv::FWriteOp) ¶

‘$fwrite’ statement

Syntax:

operation ::= `sv.fwrite` $string attr-dict (`(` $operands^ `)` `:` type($operands))?

Attributes: ¶

Operands: ¶

sv.fatal (::circt::sv::FatalOp) ¶

‘$fatal’ statement

Syntax:

operation ::= `sv.fatal` attr-dict

Run-time fatal assertion error.

sv.finish (::circt::sv::FinishOp) ¶

‘$finish’ statement

Syntax:

operation ::= `sv.finish` attr-dict

Finishes a simulation and exits the simulation process.

sv.force (::circt::sv::ForceOp) ¶

Force procedural statement

Syntax:

operation ::= `sv.force` $dest `,` $src  attr-dict `:` type($src)

A SystemVerilog force procedural statement ‘force x = y;'. These occur in initial, always, task, and function blocks. A force statement shall override a procedural assignment until a release statement is executed on the variable. The left-hand side of the assignment can be avariable, a net, a constant bit-select of a vector net, a part-select of a vector net or a concatenation. It cannot be a memory word or a bit-select or part-select of a vector variable. See SV Spec 10.6.2.

Operands: ¶

sv.modport.get (::circt::sv::GetModportOp) ¶

Get a modport out of an interface instance

Syntax:

operation ::= `sv.modport.get` $iface $field attr-dict `:` type($iface) `->` type($result)

Use this to extract a modport view to an instantiated interface. For example, to get the ‘dataflow_in’ modport on the ‘handshake_example’ interface:

%ifaceModport = sv.modport.get @dataflow_in %iface :
  !sv.interface<@handshake_example> ->
  !sv.modport<@handshake_example::@dataflow_in>

Attributes: ¶

Operands: ¶

Results: ¶

sv.ifdef (::circt::sv::IfDefOp) ¶

‘ifdef MACRO’ block

Syntax:

operation ::= `sv.ifdef` $cond $thenRegion (`else` $elseRegion^)? attr-dict

This operation is an #ifdef block, which has a “then” and “else” region. This operation is for non-procedural regions and its body is non-procedural.

Attributes: ¶

sv.ifdef.procedural (::circt::sv::IfDefProceduralOp) ¶

‘ifdef MACRO’ block for procedural regions

Syntax:

operation ::= `sv.ifdef.procedural` $cond $thenRegion (`else` $elseRegion^)? attr-dict

This operation is an #ifdef block, which has a “then” and “else” region. This operation is for procedural regions and its body is procedural.

Attributes: ¶

sv.if (::circt::sv::IfOp) ¶

‘if (cond)’ block

Syntax:

operation ::= `sv.if` $cond $thenRegion (`else` $elseRegion^)? attr-dict

Operands: ¶

sv.initial (::circt::sv::InitialOp) ¶

‘initial’ block

Syntax:

operation ::= `sv.initial` $body attr-dict

See SV Spec 9.2.1.

sv.interface.instance (::circt::sv::InterfaceInstanceOp) ¶

Instantiate an interface

Syntax:

operation ::= `sv.interface.instance` (`sym` $sym_name^)? custom<ImplicitSSAName>(attr-dict) `:` type($result)

Use this to declare an instance of an interface:

%iface = sv.interface.instance : !sv.interface<@handshake_example>

Attributes: ¶

Results: ¶

sv.interface.modport (::circt::sv::InterfaceModportOp) ¶

Operation to define a SystemVerilog modport for interfaces

Syntax:

operation ::= `sv.interface.modport` attr-dict $sym_name custom<ModportStructs>($ports)

This operation defines a named modport within an interface. Its name is a symbol that can be looked up inside its parent interface. There is an array of structs that contains two fields: an enum to indicate the direction of the signal in the modport, and a symbol reference to refer to the signal.

Example:

sv.interface.modport @input_port ("input" @data)
sv.interface.modport @output_port ("output" @data)

Attributes: ¶

sv.interface (::circt::sv::InterfaceOp) ¶

Operation to define a SystemVerilog interface

Syntax:

operation ::= `sv.interface` attr-dict $sym_name $body

This operation defines a named interface. Its name is a symbol that can be looked up when declared inside a SymbolTable operation. This operation is also a SymbolTable itself, so the symbols in its region can be looked up.

Example:

sv.interface @myinterface {
  sv.interface.signal @data : i32
  sv.interface.modport @input_port ("input" @data)
  sv.interface.modport @output_port ("output" @data)
}

Attributes: ¶

sv.interface.signal (::circt::sv::InterfaceSignalOp) ¶

Operation to define a SystemVerilog signal for interfaces

Syntax:

operation ::= `sv.interface.signal` attr-dict $sym_name `:` $type

This operation defines a named signal within an interface. Its type is specified in an attribute, and currently supports IntegerTypes.

Example:

sv.interface.signal @data : i32

Attributes: ¶

sv.localparam (::circt::sv::LocalParamOp) ¶

Declare a localparam

Syntax:

operation ::= `sv.localparam` custom<ImplicitSSAName>(attr-dict) $input `:` type($result)

The localparam operation produces a localparam declaration. See SV spec 6.20.4 p125.

  %result = hw.localparam %input : t1

Attributes: ¶

Operands: ¶

Results: ¶

sv.passign (::circt::sv::PAssignOp) ¶

Nonblocking procedural assignment

Syntax:

operation ::= `sv.passign` $dest `,` $src  attr-dict `:` type($src)

A SystemVerilog nonblocking procedural assignment statement ‘x <= y;'. These occur in initial, always, task, and function blocks. The statement can be scheduled without blocking procedural flow. See SV Spec 10.4.2.

Operands: ¶

sv.read_inout (::circt::sv::ReadInOutOp) ¶

Get the value of from something of inout type (e.g. a wire or inout port) as the value itself.

Syntax:

operation ::= `sv.read_inout` $input attr-dict `:` type($input)

Operands: ¶

Results: ¶

sv.interface.signal.read (::circt::sv::ReadInterfaceSignalOp) ¶

Access the data in an interface’s signal.

Syntax:

operation ::= `sv.interface.signal.read` $iface `(` custom<IfaceTypeAndSignal>(type($iface), $signalName) `)`
              attr-dict `:` type($signalData)

This is an expression to access a signal inside of an interface.

  %ifaceData = sv.interface.signal.read %iface
      (@handshake_example::@data) : i32

Could result in the following SystemVerilog:

  wire [31:0] ifaceData = iface.data;

Attributes: ¶

Operands: ¶

Results: ¶

sv.reg (::circt::sv::RegOp) ¶

Define a new reg in SystemVerilog

Syntax:

operation ::= `sv.reg` (`sym` $sym_name^)? custom<ImplicitSSAName>(attr-dict)
              `:` type($result)

Declare a SystemVerilog Variable Declaration of ‘reg’ type. See SV Spec 6.8, pp100.

Attributes: ¶

Results: ¶

sv.release (::circt::sv::ReleaseOp) ¶

Release procedural statement

Syntax:

operation ::= `sv.release` $dest attr-dict `:` type($dest)

Release is used in conjunction with force. When released, then if the variable does not currently have an active assign procedural continuous assignment, the variable shall not immediately change value. The variable shall maintain its current value until the next procedural assignment or procedural continuous assignment to the variable. Releasing a variable that currently has an active assign procedural continuous assignment shall immediately reestablish that assignment. See SV Spec 10.6.2.

Operands: ¶

sv.verbatim.expr (::circt::sv::VerbatimExprOp) ¶

Expression that expands to a value given SystemVerilog text

Syntax:

operation ::= `sv.verbatim.expr` $string attr-dict (`(` $operands^ `)`)?
              `:` functional-type($operands, $result)

This operation produces a typed value expressed by a string of SystemVerilog. This can be used to access macros and other values that are only sensible as Verilog text.

The text string is expected to have the highest precedence, so you should include parentheses in the string if it isn’t a single token. This is also assumed to not have side effects (use sv.verbatim.expr.se) if you need them.

sv.verbatim.expr allows operand substitutions with {{0}} syntax.

Attributes: ¶

Operands: ¶

Results: ¶

sv.verbatim.expr.se (::circt::sv::VerbatimExprSEOp) ¶

Expression that expands to a value given SystemVerilog text

Syntax:

operation ::= `sv.verbatim.expr.se` $string attr-dict (`(` $operands^ `)`)?
              `:` functional-type($operands, $result)

This operation produces a typed value expressed by a string of SystemVerilog. This can be used to access macros and other values that are only sensible as Verilog text.

The text string is expected to have the highest precedence, so you should include parentheses in the string if it isn’t a single token. This is allowed to have side effects.

sv.verbatim.se.expr allows operand substitutions with {{0}} syntax.

Attributes: ¶

Operands: ¶

Results: ¶

sv.verbatim (::circt::sv::VerbatimOp) ¶

Verbatim opaque text emitted inline.

Syntax:

operation ::= `sv.verbatim` $string attr-dict (`(` $operands^ `)` `:` type($operands))?

This operation produces opaque text inline in the SystemVerilog output.

sv.verbatim allows operand substitutions with {{0}} syntax.

Attributes: ¶

Operands: ¶

sv.wire (::circt::sv::WireOp) ¶

Define a new wire

Syntax:

operation ::= `sv.wire` (`sym` $sym_name^)? custom<ImplicitSSAName>(attr-dict)
              `:` type($result)

Declare a SystemVerilog Net Declaration of ‘wire’ type. See SV Spec 6.7, pp97.

Attributes: ¶

Results: ¶

Type definition ¶

InterfaceType ¶

SystemVerilog interface type pointing to an InterfaceOp

A MLIR type for the SV dialect’s InterfaceOp to allow instances in any dialect with an open type system. Points at the InterfaceOp which defines the SystemVerilog interface.

Parameters: ¶

ModportType ¶

SystemVerilog type pointing to an InterfaceModportOp

A MLIR type for the SV dialect’s InterfaceModportOp to allow interactions with any open type system dialect. Points at the InterfaceModportOp which defines the SystemVerilog interface’s modport.

Parameters: ¶