'seq' Dialect

Types and operations for seq dialect The seq dialect is intended to model digital sequential logic.

Operation definition

seq.compreg (::circt::seq::CompRegOp)

Register a value, storing it for one cycle

See the Seq dialect rationale for a longer description Traits: SameVariadicOperandSize

Interfaces: NoSideEffect (MemoryEffectOpInterface), OpAsmOpInterface

Effects: MemoryEffects::Effect{}

Attributes:

Operands:

Results:

seq.firreg (::circt::seq::FirRegOp)

Register with preset and sync or async reset

firreg represents registers originating from FIRRTL after the lowering of the IR to HW. The register is used as an intermediary in the process of lowering to SystemVerilog to facilitate optimisation at the HW level, compactly representing a register with a single operation instead of composing it from register definitions, always blocks and if statements.

The data output of the register accesses the value it stores. On the rising edge of the clk input, the register takes a new value provided by the next signal. Optionally, the register can also be provided with a synchronous or an asynchronous reset signal and resetValue, as shown in the example below.

%name = seq.firreg %next clock %clk [ sym @sym ]
    [ reset (sync|async) %reset, %value ] : type

Implicitly, all registers are pre-set to a randomized value.

A register implementing a counter starting at 0 from reset can be defined as follows:

%zero = hw.constant 0 : i32
%reg = seq.firreg %next clock %clk reset sync %reset, %zero : i32
%one = hw.constant 1 : i32
%next = comb.add %zero, %one : i32

Traits: SameVariadicOperandSize

Interfaces: NoSideEffect (MemoryEffectOpInterface), OpAsmOpInterface

Effects: MemoryEffects::Effect{}

Attributes:

Operands:

Results:

'seq' Dialect Docs

• Seq(uential) Dialect Rationale