CIRCT

Circuit IR Compilers and Tools

'seq' Dialect

Types and operations for seq dialect The seq dialect is intended to model digital sequential logic.

Operation definition

seq.compreg (::circt::seq::CompRegOp)

Register a value, storing it for one cycle

See the Seq dialect rationale for a longer description Traits: AlwaysSpeculatableImplTrait, SameVariadicOperandSize

Interfaces: Clocked, ConditionallySpeculatable, NoMemoryEffect (MemoryEffectOpInterface), OpAsmOpInterface, Resettable

Effects: MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
name::mlir::StringAttrstring attribute
sym_name::mlir::StringAttrstring attribute

Operands:

OperandDescription
inputany type
clk1-bit signless integer
reset1-bit signless integer
resetValueany type

Results:

ResultDescription
dataany type

seq.firreg (::circt::seq::FirRegOp)

Register with preset and sync or async reset

firreg represents registers originating from FIRRTL after the lowering of the IR to HW. The register is used as an intermediary in the process of lowering to SystemVerilog to facilitate optimisation at the HW level, compactly representing a register with a single operation instead of composing it from register definitions, always blocks and if statements.

The data output of the register accesses the value it stores. On the rising edge of the clk input, the register takes a new value provided by the next signal. Optionally, the register can also be provided with a synchronous or an asynchronous reset signal and resetValue, as shown in the example below.

%name = seq.firreg %next clock %clk [ sym @sym ]
    [ reset (sync|async) %reset, %value ] : type

Implicitly, all registers are pre-set to a randomized value.

A register implementing a counter starting at 0 from reset can be defined as follows:

%zero = hw.constant 0 : i32
%reg = seq.firreg %next clock %clk reset sync %reset, %zero : i32
%one = hw.constant 1 : i32
%next = comb.add %reg, %one : i32

Traits: AlwaysSpeculatableImplTrait, SameVariadicOperandSize

Interfaces: Clocked, ConditionallySpeculatable, MemoryEffectOpInterface (MemoryEffectOpInterface), NoMemoryEffect (MemoryEffectOpInterface), OpAsmOpInterface, Resettable

Effects: MemoryEffects::Effect{MemoryEffects::Write on ::mlir::SideEffects::DefaultResource, MemoryEffects::Read on ::mlir::SideEffects::DefaultResource, MemoryEffects::Allocate on ::mlir::SideEffects::DefaultResource}, MemoryEffects::Effect{}

Attributes:

AttributeMLIR TypeDescription
name::mlir::StringAttrstring attribute
inner_sym::mlir::StringAttrstring attribute
isAsync::mlir::UnitAttrunit attribute

Operands:

OperandDescription
nextany type
clk1-bit signless integer
reset1-bit signless integer
resetValueany type

Results:

ResultDescription
dataany type

seq.hlmem (::circt::seq::HLMemOp)

Instantiate a high-level memory.

Syntax:

operation ::= `seq.hlmem` $sym_name $clk `,` $rst attr-dict `:` type($handle)

See the Seq dialect rationale for a longer description Interfaces: Clocked, OpAsmOpInterface, Symbol

Attributes:

AttributeMLIR TypeDescription
sym_name::mlir::StringAttrstring attribute

Operands:

OperandDescription
clk1-bit signless integer
rst1-bit signless integer

Results:

ResultDescription
handleMulti-dimensional memory type

seq.read (::circt::seq::ReadPortOp)

Structural read access to a seq.hlmem, with an optional read enable signal.

Traits: AttrSizedOperandSegments

Interfaces: OpAsmOpInterface

Attributes:

AttributeMLIR TypeDescription
latency::mlir::IntegerAttr64-bit signless integer attribute

Operands:

OperandDescription
memoryMulti-dimensional memory type
addressesa signless integer bitvector
rdEn1-bit signless integer

Results:

ResultDescription
readDataany type

seq.write (::circt::seq::WritePortOp)

Structural write access to a seq.hlmem

Attributes:

AttributeMLIR TypeDescription
latency::mlir::IntegerAttr64-bit signless integer attribute

Operands:

OperandDescription
memoryMulti-dimensional memory type
addressesa signless integer bitvector
inDataany type
wrEn1-bit signless integer

Type definition

HLMemType

Multi-dimensional memory type

Syntax:

hlmem-type ::== `hlmem` `<` dim-list element-type `>`

The HLMemType represents the type of an addressable memory structure. The type is inherently multidimensional. Dimensions must be known integer values.

Note: unidimensional memories are represented as <1x{element type}> - <{element type}> is illegal.

Parameters:

ParameterC++ typeDescription
shape::llvm::ArrayRef<int64_t>
elementTypeType

'seq' Dialect Docs