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Circuit IR Compilers and Tools
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'sim' Dialect
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Simulation (Sim) Dialect Rationale
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Talks and Related Publications
Getting Started
Code Documentation
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CommandGuide
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handshake-runner
CIRCT Charter
Dialects
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'arc' Dialect
'calyx' Dialect
'chirrtl' Dialect
'comb' Dialect
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`comb` Dialect Rationale
'dc' Dialect
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DC Dialect Rationale
'emit' Dialect
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Emission (Emit) Dialect Rationale
'esi' Dialect
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ESI cosimulation model
ESI data types and communication types
ESI Global Services
ESI Software APIs
Miscellaneous Notes
The Elastic Silicon Interconnect dialect
'firrtl' Dialect
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FIRRTL Annotations
FIRRTL Dialect Rationale
Intrinsics
'fsm' Dialect
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FSM Dialect Rationale
'handshake' Dialect
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Handshake Dialect Rationale
'hw' Dialect
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HW Dialect Rationale
'hwarith' Dialect
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HW Arith Dialect Rationale
'ibis' Dialect
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`ibis` Dialect Rationale
'llhd' Dialect
'loopschedule' Dialect
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LoopSchedule Dialect Rationale
'ltl' Dialect
'moore' Dialect
'msft' Dialect
'om' Dialect
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Object Model Dialect Rationale
'pipeline' Dialect
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Pipeline Dialect Rationale
'seq' Dialect
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Seq(uential) Dialect Rationale
'sim' Dialect
'sim' Dialect
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Simulation (Sim) Dialect Rationale
'ssp' Dialect
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SSP Dialect Rationale
'sv' Dialect
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SV Dialect Rationale
'systemc' Dialect
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SystemC Dialect Rationale
'verif' Dialect
Debug Dialect
Interop Dialect
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Interoperability Dialect Rationale
SMT Dialect
EDA Tool Workarounds
Formal Verification Tooling
Getting Started with the CIRCT Project
HLS in CIRCT
Passes
Python CIRCT Design Entry (PyCDE)
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Compiling CIRCT and PyCDE
PyCDE Basics
Static scheduling infrastructure
Symbol and Inner Symbol Rationale
Using the Python Bindings
Verilog and SystemVerilog Generation
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