Operation definition ¶
staticlogic.pipeline (::circt::staticlogic::PipelineOp) ¶
The “staticlogic.pipeline” operation represents a statically scheduled pipeline stucture which contains several MLIR blocks. Each MLIR block is corresponding to a pipeline stage.
Interfaces: NoSideEffect (MemoryEffectOpInterface)
staticlogic.pipeline.register (::circt::staticlogic::PipelineRegisterOp) ¶
StaticLogic dialect pipeline register.
operation ::= `staticlogic.pipeline.register` $operands (`:` type($operands)^)? attr-dict
staticlogic.pipeline.register terminates a pipeline stage and
“registers” the values specified as operands. These values become the
results of the stage.
Traits: HasParent<PipelineWhileOp, PipelineStageOp>, Terminator
staticlogic.pipeline.stage (::circt::staticlogic::PipelineStageOp) ¶
StaticLogic dialect pipeline stage.
operation ::= `staticlogic.pipeline.stage` (`when` $when^)? $body (`:` type($results)^)? attr-dict
This operation has a single-block region which dictates the operations that may occur concurrently.
It may have an optional
when predicate, which supports conditional
execution for each stage. This is in addition to the
condition region that
controls the execution of the whole pipeline. A stage with a
predicate should only execute when the predicate is
true : i1, and push a
bubble through the pipeline otherwise.
It has a
staticlogic.register terminator, which passes the concurrently
computed values forward to the next stage.
Any stage may access
iter_args. If a stage accesses an
the stage in which it is defined, it is up to lowering passes to preserve
this value until the last stage that needs it.
iter_args, stages may only access SSA values dominating the
pipeline or SSA values computed by a previous stage. This ensures the stages
capture the coarse-grained schedule of the pipeline and how values feed
forward and backward.
|1-bit signless integer|
staticlogic.pipeline.terminator (::circt::staticlogic::PipelineTerminatorOp) ¶
StaticLogic dialect pipeline terminator.
operation ::= `staticlogic.pipeline.terminator` `iter_args` `(` $iter_args `)` `,` `results` `(` $results `)` `:` functional-type($iter_args, $results) attr-dict
staticlogic.pipeline.terminator operation represents the terminator of
results section accepts a variadic list of values which become the
pipeline’s return values. These must be results of a stage, and their types
must match the pipeline’s return types. The results need not be defined in
the final stage, and it is up to lowering passes to preserve these values
until the final stage is complete.
iter_args section accepts a variadic list of values which become the
iter_args. These may be the results of any stage, and
their types must match the pipeline’s
Traits: AttrSizedOperandSegments, HasParent
staticlogic.pipeline.while (::circt::staticlogic::PipelineWhileOp) ¶
StaticLogic dialect pipeline while-loop.
staticlogic.pipeline.while operation represents a statically scheduled
pipeline stucture that executes while a condition is true. For more details,
A pipeline captures the result of scheduling, and is not generally safe to transform, besides lowering to hardware dialects. For more discussion about relaxing this, see: https://github.com/llvm/circt/issues/2204.
This is the top-level operation representing a high-level pipeline. It is
not isolated from above, but could be if this is helpful. A pipeline
contains two regions:
The pipeline may accept an optional
iter_args, similar to the SCF dialect,
for representing loop-carried values like induction variables or reductions.
When the pipeline starts execution, the registers indicated as
staticlogic.pipeline.terminator should be initialized to the initial
values specified in the
iter_args section here. The
iter_args relate to
the initiation interval of the loop. The maximum distance in stages between
iter_arg is used and where that
iter_arg is registered must be
less than the loop’s initiation interval. For example, with II=1, each
iter_arg must be used and registered in the same stage.
condition region dictates the condition under which the
pipeline should execute. It has a
staticlogic.register terminator, and the
pipeline initiates new iterations while the registered value is
true : i1.
It may access SSA values dominating the pipeline, as well as
which are block arguments. The body of the block may only contain
“combinational” operations, which are currently defined to be simple
arithmetic, comparisons, and selects from the
stages region wraps
operations. It has a
staticlogic.pipeline.terminator terminator, which can
both return results from the pipeline and register
iter_args. Stages may
access SSA values dominating the pipeline, as well as
iter_args, which are
|::mlir::IntegerAttr||64-bit signless integer attribute|
staticlogic.return (::circt::staticlogic::ReturnOp) ¶
StaticLogic dialect return.
The “staticlogic.return” operation represents a terminator of a statically scheduled module, which is similar to a standard return operation.