14 #include "mlir/IR/Builders.h"
16 using namespace circt;
24 MLIRContext *context, std::optional<Location> loc, ValueRange operands,
25 DictionaryAttr attrs, mlir::OpaqueProperties properties,
26 mlir::RegionRange regions, SmallVectorImpl<Type> &results) {
29 for (
auto operand : operands) {
30 auto type = operand.getType().cast<
UnpackedType>().getSimpleBitVector();
46 if (p.parseType(type))
47 return p.emitError(p.getCurrentLocation(),
"expected type");
53 p.printType(lValueType.cast<LValueType>().getNestedType());
61 #define GET_OP_CLASSES
62 #include "circt/Dialect/Moore/Moore.cpp.inc"
63 #include "circt/Dialect/Moore/MooreEnums.cpp.inc"
static ParseResult parseLValueType(OpAsmParser &p, Type &lValueType)
static void printLValueType(OpAsmPrinter &p, Operation *, Type lValueType)
An unpacked SystemVerilog type.
Direction get(bool isOutput)
Returns an output direction if isOutput is true, otherwise returns an input direction.
LogicalResult inferReturnTypes(MLIRContext *context, std::optional< Location > loc, ValueRange operands, DictionaryAttr attrs, mlir::OpaqueProperties properties, mlir::RegionRange regions, SmallVectorImpl< Type > &results, llvm::function_ref< FIRRTLType(ValueRange, ArrayRef< NamedAttribute >, std::optional< Location >)> callback)
Domain
The number of values each bit of a type can assume.
@ FourValued
Four-valued types such as logic or integer.
@ TwoValued
Two-valued types such as bit or int.
@ Unsigned
An unsigned type.
This file defines an intermediate representation for circuits acting as an abstraction for constraint...
A simple bit vector type.