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| List[int] | esiaccel.components.channel_arbiter._select_reg_levels (int num_inputs, Optional[int] mux_pipeline_levels) |
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| int | esiaccel.components.channel_arbiter._select_latency (int num_inputs, Optional[int] mux_pipeline_levels) |
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| BitsSignal | esiaccel.components.channel_arbiter._select_mux (BitsSignal sel, List[BitsSignal] values, ClockSignal clk, Signal rst, Optional[int] mux_pipeline_levels) |
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| BitsSignal | esiaccel.components.channel_arbiter._onehot_to_index (BitsSignal onehot) |
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| Tuple[BitsSignal, BitsSignal, BitsSignal] | esiaccel.components.channel_arbiter._build_grant_state (ports, ClockSignal clk, Signal rst, int num_inputs, BitsSignal next_grant, BitsSignal next_busy) |
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| | esiaccel.components.channel_arbiter.GrantSchedulerMod (int num_inputs, int queue_depth) |
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| | esiaccel.components.channel_arbiter.RoundRobinArbiterMod (int num_inputs) |
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| | esiaccel.components.channel_arbiter.RoundRobinControlMod (int num_inputs) |
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| | esiaccel.components.channel_arbiter.ChannelArbiterMod (Channel channel_type, int num_inputs, int output_fifo_depth, bool buffer_inputs, bool telemetry, Optional[int] mux_pipeline_levels, bool pipelined_scheduler, int grant_queue_depth) |
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| ChannelSignal | esiaccel.components.channel_arbiter.ChannelArbiter (List[ChannelSignal] input_channels, ClockSignal clk, Signal rst, *Optional[AppID] appid=None, Optional[int] output_fifo_depth=None, bool buffer_inputs=True, Optional[int] mux_pipeline_levels=None, bool pipelined_scheduler=False, int grant_queue_depth=4, bool telemetry=True) |
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