124 active = Wire(Bits(1))
127 in_ready = Wire(Bits(1))
128 win, valid = ports.in_.unwrap(in_ready)
134 is_completing = valid & last
137 report_valid = is_completing
140 start_any = valid & in_ready & ~active
141 cur_src = src.reg(ports.clk, ports.rst, ce=start_any, rst_value=0)
144 interleave_err = (valid & in_ready) & active & (src != cur_src)
145 err.assign((err | interleave_err).reg(ports.clk, ports.rst, rst_value=0))
149 xact = valid & in_ready
150 begin_multi = xact & ~active & ~last
151 end_msg = xact & last
152 active_next = Mux(end_msg, Mux(begin_multi, active, Bits(1)(1)), Bits(1)(0))
153 active.assign(active_next.reg(ports.clk, ports.rst, rst_value=0))
156 msg_count = Counter(16)(clk=ports.clk,
161 report_data = ((err.as_uint(32) * UInt(32)(0x1000000)).as_uint(32) +
162 (cur_src.as_uint(32) * UInt(32)(0x10000)).as_uint(32) +
163 msg_count.out.as_uint(32)).as_uint(32)
164 report_chan, report_ready = Channel(UInt(32)).
wrap(report_data,
166 ports.report = report_chan
170 in_ready.assign(Mux(is_completing, Bits(1)(1), report_ready))