CIRCT
Circuit IR Compilers and Tools
Community
Forums
Chat
Source
Doxygen
GitHub
Getting Started
See
https://circt.llvm.org/docs/GettingStarted/
.
Edit on GitHub
Prev - Talks and Related Publications
Next - Code Documentation
Home
Talks and Related Publications
Getting Started
Code Documentation
+
CommandGuide
+
handshake-runner
CIRCT Charter
Dialects
+
'arc' Dialect
'calyx' Dialect
'chirrtl' Dialect
'comb' Dialect
+
`comb` Dialect Rationale
'dc' Dialect
+
DC Dialect Rationale
'emit' Dialect
+
Emission (Emit) Dialect Rationale
'esi' Dialect
+
ESI cosimulation model
ESI data types and communication types
ESI Global Services
ESI Software APIs
Miscellaneous Notes
The Elastic Silicon Interconnect dialect
'firrtl' Dialect
+
FIRRTL Annotations
FIRRTL Dialect Rationale
Intrinsics
'fsm' Dialect
+
FSM Dialect Rationale
'handshake' Dialect
+
Handshake Dialect Rationale
'hw' Dialect
+
HW Dialect Rationale
'hwarith' Dialect
+
HW Arith Dialect Rationale
'ibis' Dialect
+
`ibis` Dialect Rationale
'llhd' Dialect
'loopschedule' Dialect
+
LoopSchedule Dialect Rationale
'ltl' Dialect
'moore' Dialect
'msft' Dialect
'om' Dialect
+
Object Model Dialect Rationale
'pipeline' Dialect
+
Pipeline Dialect Rationale
'seq' Dialect
+
Seq(uential) Dialect Rationale
'sim' Dialect
'sim' Dialect
+
Simulation (Sim) Dialect Rationale
'ssp' Dialect
+
SSP Dialect Rationale
'sv' Dialect
+
SV Dialect Rationale
'systemc' Dialect
+
SystemC Dialect Rationale
'verif' Dialect
Debug Dialect
Interop Dialect
+
Interoperability Dialect Rationale
SMT Dialect
EDA Tool Workarounds
Formal Verification Tooling
Getting Started with the CIRCT Project
HLS in CIRCT
Passes
Python CIRCT Design Entry (PyCDE)
+
Compiling CIRCT and PyCDE
PyCDE Basics
Static scheduling infrastructure
Symbol and Inner Symbol Rationale
Using the Python Bindings
Verilog and SystemVerilog Generation
CIRCT
CIRCT