CIRCT 24.0.0git
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circt::firrtl::GatedClockConversion Member List

This is the complete list of members for circt::firrtl::GatedClockConversion, including all inherited members.

addRoot(Operation *op)circt::firrtl::GatedClockConversion
analyzeFrom(ArrayRef< Value > seeds)circt::firrtl::GatedClockConversionprivate
applyPlan()circt::firrtl::GatedClockConversionprivate
baseClkscirct::firrtl::GatedClockConversionprivate
clockEnablePairscirct::firrtl::GatedClockConversionprivate
clockTypecirct::firrtl::GatedClockConversionprivate
computeGatedClocks()circt::firrtl::GatedClockConversionprivate
connectMaterializedToInstancePorts(InstanceOp inst, unsigned clkPortIndex, unsigned enPortIndex, Value materializedClk, Value materializedEn)circt::firrtl::GatedClockConversionprivate
constU1Cachecirct::firrtl::GatedClockConversionprivate
contextcirct::firrtl::GatedClockConversionprivate
createPlannedWires()circt::firrtl::GatedClockConversionprivate
deadInstancescirct::firrtl::GatedClockConversionprivate
dump() constcirct::firrtl::GatedClockConversion
dumpPlan() constcirct::firrtl::GatedClockConversionprivate
eliminateTemporaryWires()circt::firrtl::GatedClockConversionprivate
emitPlannedIR()circt::firrtl::GatedClockConversionprivate
enableNodescirct::firrtl::GatedClockConversionprivate
GatedClockConversion(InstanceGraph &ig)circt::firrtl::GatedClockConversioninlineexplicit
gatedClockscirct::firrtl::GatedClockConversionprivate
gateEnableCachecirct::firrtl::GatedClockConversionprivate
gateEnableOf(ClockGateIntrinsicOp gate)circt::firrtl::GatedClockConversionprivate
getOrCreateConstU1One(FModuleOp mod)circt::firrtl::GatedClockConversionprivate
igcirct::firrtl::GatedClockConversionprivate
insertPlannedPorts()circt::firrtl::GatedClockConversionprivate
instanceDrivescirct::firrtl::GatedClockConversionprivate
instClonescirct::firrtl::GatedClockConversionprivate
kNoEnablecirct::firrtl::GatedClockConversionprivatestatic
liveInstance(Operation *inst) constcirct::firrtl::GatedClockConversioninlineprivate
lower(unsigned enableId)circt::firrtl::GatedClockConversionprivate
loweredEnablescirct::firrtl::GatedClockConversionprivate
newEnableLeaf(MatRef term, Location loc)circt::firrtl::GatedClockConversioninlineprivate
newEnableNode(unsigned parent, MatRef term, Location loc, MatRef anchor)circt::firrtl::GatedClockConversionprivate
nextPortIdxcirct::firrtl::GatedClockConversionprivate
plan()circt::firrtl::GatedClockConversionprivate
planAlias(Value dstClk, FModuleOp srcMod, MatRef baseClk, unsigned enableId)circt::firrtl::GatedClockConversionprivate
planGate(ClockGateIntrinsicOp gate, Value dstClk, MatRef baseClk, unsigned enableId)circt::firrtl::GatedClockConversionprivate
planGatedPorts(InstanceOp inst, FModuleOp childMod, unsigned gatedClkIndex, Direction dir, MatRef baseClk, unsigned enableId)circt::firrtl::GatedClockConversionprivate
planInstancePort(Direction dir, InstanceOp inst, Value dstClk, Value srcClk, MatRef baseClk, unsigned enableId)circt::firrtl::GatedClockConversionprivate
planMultiplyInstantiatedInput(Value srcClk, MatRef baseClk, unsigned enableId)circt::firrtl::GatedClockConversionprivate
plannedWireValuescirct::firrtl::GatedClockConversionprivate
plansPerModulecirct::firrtl::GatedClockConversionprivate
PortPlanKey typedefcirct::firrtl::GatedClockConversionprivate
portPlanscirct::firrtl::GatedClockConversionprivate
processEdge(const ClockEdge &edge, Value srcClk, FModuleOp srcMod, MatRef baseClk, unsigned enableId)circt::firrtl::GatedClockConversionprivate
recordInstanceDrive(InstanceOp inst, const PortPairPlan &plan, MatRef baseClk, unsigned enableId)circt::firrtl::GatedClockConversionprivate
resolve(MatRef ref)circt::firrtl::GatedClockConversionprivate
rewriteRoot(Operation *op, Value baseClk, Value enable)circt::firrtl::GatedClockConversionprivate
rootRewritescirct::firrtl::GatedClockConversionprivate
rootscirct::firrtl::GatedClockConversionprivate
run()circt::firrtl::GatedClockConversion
srcToDstClockscirct::firrtl::GatedClockConversionprivate
u1Typecirct::firrtl::GatedClockConversionprivate
visitedcirct::firrtl::GatedClockConversionprivate
wireOpscirct::firrtl::GatedClockConversionprivate
wirePlanscirct::firrtl::GatedClockConversionprivate