esiaccel.bsp.xrt.MMIOAxiWriteCombine Class Reference

Inheritance diagram for esiaccel.bsp.xrt.MMIOAxiWriteCombine:

Collaboration diagram for esiaccel.bsp.xrt.MMIOAxiWriteCombine:

Public Member Functions
	build (ports)

Static Public Attributes
	clk = Clock()
	rst = Reset()
	write_address = InputChannel(Bits(AxiMMIOAddrWidth))
	write_data = InputChannel(Bits(32))
	cmd = OutputChannel(MMIOIntermediateCmd)
	write_resp = OutputChannel(Bits(2))

Detailed Description

MMIO AXI Lite writes on XRT are 32 bits, but the MMIO service expects 64.
Furthermore, there are two separate channels for writes: address and data. All
four transactions must take place before an ESI MMIO write is considered
complete.

Definition at line 45 of file xrt.py.

Member Function Documentation

build()

esiaccel.bsp.xrt.MMIOAxiWriteCombine.build

(

ports

)

Definition at line 60 of file xrt.py.

Member Data Documentation

clk

esiaccel.bsp.xrt.MMIOAxiWriteCombine.clk = Clock()

static

Definition at line 51 of file xrt.py.

Referenced by esiaccel.bsp.common.ESI_Manifest_ROM_Wrapper.build().

cmd

esiaccel.bsp.xrt.MMIOAxiWriteCombine.cmd = OutputChannel(MMIOIntermediateCmd)

static

Definition at line 56 of file xrt.py.

rst

esiaccel.bsp.xrt.MMIOAxiWriteCombine.rst = Reset()

static

Definition at line 52 of file xrt.py.

write_address

esiaccel.bsp.xrt.MMIOAxiWriteCombine.write_address = InputChannel(Bits(AxiMMIOAddrWidth))

static

Definition at line 53 of file xrt.py.

write_data

esiaccel.bsp.xrt.MMIOAxiWriteCombine.write_data = InputChannel(Bits(32))

static

Definition at line 54 of file xrt.py.

write_resp

esiaccel.bsp.xrt.MMIOAxiWriteCombine.write_resp = OutputChannel(Bits(2))

static

Definition at line 57 of file xrt.py.

---

The documentation for this class was generated from the following file:

• /home/runner/work/circt-www/circt-www/circt_src/lib/Dialect/ESI/runtime/python/esiaccel/bsp/xrt.py