esiaccel.bsp.common Namespace Reference

Classes
class	ChannelMMIO
class	ESI_Manifest_ROM
class	ESI_Manifest_ROM_Wrapper
class	MMIOIndirection

Functions
Module	HeaderMMIO (int manifest_loc)
type["ChannelDemuxNImpl"]	ChannelDemuxN_HalfStage_ReadyBlocking (Type data_type, int num_outs, int next_sel_width)
type["ChannelDemuxTree"]	ChannelDemuxTree_HalfStage_ReadyBlocking (Type data_type, int num_outs, int branching_factor_log2)
type["DesignResetControllerImpl"]	DesignResetController (int delay_cycles)
type["TaggedReadGearboxImpl"]	TaggedReadGearbox (int input_bitwidth, int output_bitwidth)
	HostmemReadProcessor (int read_width, hostmem_module, List[esi._OutputBundleSetter] reqs)
type["TaggedWriteGearboxImpl"]	TaggedWriteGearbox (int input_bitwidth, int output_bitwidth)
type[ 'EmitEveryNImpl']	EmitEveryN (Type message_type, int N)
type["HostMemWriteProcessorImpl"]	HostMemWriteProcessor (int write_width, hostmem_module, List[esi._OutputBundleSetter] reqs)
typing.Type[ 'ChannelHostMemImpl']	ChannelHostMem (int read_width, int write_width)
type[ 'DummyToHostEngineImpl']	DummyToHostEngine (Type client_type)
type[ 'DummyFromHostEngineImpl']	DummyFromHostEngine (Type client_type)
type[ 'ChannelEngineService']	ChannelEngineService (Callable to_host_engine_gen, Callable from_host_engine_gen)

Variables
int	MagicNumber = 0x207D98E5_E5100E51
int	VersionNumber = 0
int	IndirectionMagicNumber = 0x312bf0cc_E5100E51
int	IndirectionVersionNumber = 0
int	ResetMagicNumber = 0x00000E510000B007
int	ResetCycles = 8192

Function Documentation

ChannelDemuxN_HalfStage_ReadyBlocking()

type["ChannelDemuxNImpl"] esiaccel.bsp.common.ChannelDemuxN_HalfStage_ReadyBlocking	(	Type	data_type,
		int	num_outs,
		int	next_sel_width
	)

N-way channel demultiplexer for valid/ready signaling. Contains
  valid/ready registers on the output channels. The selection signal is now
  embedded in the input channel payload as a struct {sel, data}. Input
  signals ready when the selected output register is empty.

Definition at line 169 of file common.py.

References wrap().

Referenced by esiaccel.bsp.common.ChannelDemuxTree_HalfStage_ReadyBlocking().

ChannelDemuxTree_HalfStage_ReadyBlocking()

type["ChannelDemuxTree"] esiaccel.bsp.common.ChannelDemuxTree_HalfStage_ReadyBlocking	(	Type	data_type,
		int	num_outs,
		int	branching_factor_log2
	)

Pipelined N-way channel demultiplexer for valid/ready signaling. This
  implementation uses a tree structure of
  ChannelDemuxN_HalfStage_ReadyBlocking modules to reduce fanout pressure.
  Supports maximum half-throughput to save complexity and area.

Definition at line 262 of file common.py.

References esiaccel.bsp.common.ChannelDemuxN_HalfStage_ReadyBlocking().

Referenced by esiaccel.bsp.common.ChannelMMIO.build_read().

ChannelEngineService()

type['ChannelEngineService'] esiaccel.bsp.common.ChannelEngineService	(	Callable	to_host_engine_gen,
		Callable	from_host_engine_gen
	)

Returns a channel service implementation which calls
to_host_engine_gen(<client_type>) or from_host_engine_gen(<client_type>) to
generate the to_host and from_host engines for each channel. Does not support
engines which can service multiple clients at once.

Definition at line 1300 of file common.py.

ChannelHostMem()

typing.Type['ChannelHostMemImpl'] esiaccel.bsp.common.ChannelHostMem	(	int	read_width,
		int	write_width
	)

Definition at line 1188 of file common.py.

References esiaccel.bsp.common.HostmemReadProcessor(), and esiaccel.bsp.common.HostMemWriteProcessor().

DesignResetController()

type["DesignResetControllerImpl"] esiaccel.bsp.common.DesignResetController

(

int

delay_cycles

)

Counts `delay_cycles` clock cycles after a reset request is observed, then
asserts `design_reset` for one cycle. This module must be driven by the
*external* reset only (not the reset it generates) so that the countdown is
not disturbed by the reset it produces.

`reset_pending` is asserted from the moment a reset is requested until it
fires. It is intended to be used to quiesce the design (e.g. stop accepting
new transactions) so that nothing is in flight when the reset is asserted.

Definition at line 373 of file common.py.

DummyFromHostEngine()

type['DummyFromHostEngineImpl'] esiaccel.bsp.common.DummyFromHostEngine

(

Type

client_type

)

Create a fake DMA engine which just never produces messages.

Definition at line 1277 of file common.py.

References wrap().

DummyToHostEngine()

type['DummyToHostEngineImpl'] esiaccel.bsp.common.DummyToHostEngine

(

Type

client_type

)

Create a fake DMA engine which just throws everything away.

Definition at line 1256 of file common.py.

EmitEveryN()

type['EmitEveryNImpl'] esiaccel.bsp.common.EmitEveryN	(	Type	message_type,
		int	N
	)

Emit (forward) one message for every N input messages. The emitted message
is the last one of the N received. N must be >= 1.

Definition at line 1025 of file common.py.

Referenced by esiaccel.bsp.common.HostMemWriteProcessor().

HeaderMMIO()

Module esiaccel.bsp.common.HeaderMMIO

(

int

manifest_loc

)

Definition at line 70 of file common.py.

References wrap().

Referenced by esiaccel.bsp.common.ChannelMMIO.build_read().

HostmemReadProcessor()

esiaccel.bsp.common.HostmemReadProcessor	(	int	read_width,
			hostmem_module,
		List[esi._OutputBundleSetter]	reqs
	)

Construct a host memory read request module to orchestrate the the read
connections. Responsible for both gearboxing the data, multiplexing the
requests, reassembling out-of-order responses and routing the responses to the
correct clients.

Generate this module dynamically to allow for multiple read clients of
multiple types to be directly accomodated.

Definition at line 789 of file common.py.

References esiaccel.bsp.common.TaggedReadGearbox(), and wrap().

Referenced by esiaccel.bsp.common.ChannelHostMem().

HostMemWriteProcessor()

type["HostMemWriteProcessorImpl"] esiaccel.bsp.common.HostMemWriteProcessor	(	int	write_width,
			hostmem_module,
		List[esi._OutputBundleSetter]	reqs
	)

Construct a host memory write request module to orchestrate the the write
connections. Responsible for both gearboxing the data, multiplexing the
requests, reassembling out-of-order responses and routing the responses to the
correct clients.

Generate this module dynamically to allow for multiple write clients of
multiple types to be directly accomodated.

Definition at line 1077 of file common.py.

References esiaccel.bsp.common.EmitEveryN(), esiaccel.bsp.common.TaggedWriteGearbox(), and wrap().

Referenced by esiaccel.bsp.common.ChannelHostMem().

TaggedReadGearbox()

type["TaggedReadGearboxImpl"] esiaccel.bsp.common.TaggedReadGearbox	(	int	input_bitwidth,
		int	output_bitwidth
	)

Build a gearbox to convert the upstream data to the client data
type. Assumes a struct {tag, data} and only gearboxes the data. Tag is stored
separately and the struct is re-assembled later on.

Definition at line 703 of file common.py.

Referenced by esiaccel.bsp.common.HostmemReadProcessor().

TaggedWriteGearbox()

type["TaggedWriteGearboxImpl"] esiaccel.bsp.common.TaggedWriteGearbox	(	int	input_bitwidth,
		int	output_bitwidth
	)

Build a gearbox to convert the client data to upstream write chunks.
Assumes a struct {address, tag, data} and only gearboxes the data. Tag is
stored separately and the struct is re-assembled later on.

Definition at line 900 of file common.py.

Referenced by esiaccel.bsp.common.HostMemWriteProcessor().

Variable Documentation

IndirectionMagicNumber

int esiaccel.bsp.common.IndirectionMagicNumber = 0x312bf0cc_E5100E51

Definition at line 25 of file common.py.

IndirectionVersionNumber

int esiaccel.bsp.common.IndirectionVersionNumber = 0

Definition at line 26 of file common.py.

MagicNumber

int esiaccel.bsp.common.MagicNumber = 0x207D98E5_E5100E51

Definition at line 22 of file common.py.

ResetCycles

int esiaccel.bsp.common.ResetCycles = 8192

Definition at line 35 of file common.py.

ResetMagicNumber

int esiaccel.bsp.common.ResetMagicNumber = 0x00000E510000B007

Definition at line 32 of file common.py.

VersionNumber

int esiaccel.bsp.common.VersionNumber = 0

Definition at line 23 of file common.py.