MMIO register file with automatically-numbered registers (RO < RW < WO)
addressed at an 8-byte stride (``index = offset >> 3``).
Numbering::
[0, num_ro) -> read-only (RO)
[num_ro, num_ro + num_rw) -> read-write (RW)
[num_ro + num_rw, num_ro+num_rw+num_wo) -> write-only (WO)
The RO and RW registers ("read registers", ``num_ro + num_rw`` of them) are
held internally. The client updates any of them via the per-read-register
``read_reg_ce`` / ``read_reg_data`` arrays and observes their current value
on ``read_reg_value`` (all length ``num_ro + num_rw``, indexed RO-first then
RW). A host write to an RW register additionally stores the written data into
that register directly; a host write takes priority over a coincident client
update of the same register.
Reads -- and the read-back value returned for a write -- respond with the
selected register's value, or all-ones (-1) if the offset selects a WO
register or is out of bounds.
Writes to RW/WO registers are registered and presented to the client on
``write_cmd_r`` / ``write_cmd_xact_r`` (writes to RO offsets or out-of-bounds
offsets are dropped). ``mmio_write_we`` derives per-offset write strobes from
these.
The MMIO bundle is created inside this submodule's ``@generator``, so the
request's AppID is anchored at this instance's hierarchical position.
Ports:
read_reg_ce : Input Array(Bits(1), num_ro + num_rw)
read_reg_data : Input Array(Bits(64), num_ro + num_rw)
read_reg_value : Output Array(Bits(64), num_ro + num_rw)
write_cmd_r : Output MMIOWriteCmdType (last presented write)
write_cmd_xact_r : Output Bits(1) (1-cycle pulse on a presented write)
Definition at line 32 of file mmio.py.
References esiaccel.components.mmio.MMIOWriteCmdType, and wrap().
