CIRCT 24.0.0git
Loading...
Searching...
No Matches
Classes | Functions | Variables
esiaccel.esitester Namespace Reference

Classes

class  AutoSerialCoordTranslator
 
class  CallbackTest
 
class  ChannelTest
 
class  CoordTranslator
 
class  EsiTester
 
class  LoopbackInOutAdd
 
class  SerialCoordTranslator
 

Functions

 IterationGate (int count_width)
 
 StreamingAdder (int numItems)
 
Type[Module] MMIOAdd (int add_amt)
 
 BurstCommand (int width)
 
 ReadMem (int width)
 
Type[Module] WriteMem (int width)
 
 ToHostDMATest (int width)
 
 FromHostDMATest (int width)
 
 _one_item_buffers_pair ()
 

Variables

int _ESITESTER_SEQ_SEED = 0x5A5A5A5A5A5A5A5A
 

Function Documentation

◆ _one_item_buffers_pair()

esiaccel.esitester._one_item_buffers_pair ( )
protected

Definition at line 1311 of file esitester.py.

◆ BurstCommand()

esiaccel.esitester.BurstCommand ( int  width)
MMIO-controlled single-burst command surface. Replaces AddressCommand's
  per-flit address stream: exposes one {address, tag, length} burst request
  per command -- for a ``read_list`` or a windowed (list) write -- and tracks
  completion.

  MMIO register map (8-byte stride):
    0x00 Read : flits_left (elements remaining in the active command).
    0x08 Write: base address.
    0x10 Write: list length (flits).
    0x18 Write: start.

Definition at line 693 of file esitester.py.

References esiaccel.esitester.IterationGate(), and wrap().

Referenced by esiaccel.esitester.ReadMem(), and esiaccel.esitester.WriteMem().

◆ FromHostDMATest()

esiaccel.esitester.FromHostDMATest ( int  width)
Construct a module that receives the write count over a channel from the
  host the specified number of times. Exercises any DMA engine.

Definition at line 1146 of file esitester.py.

References wrap().

Referenced by esiaccel.esitester.EsiTester.construct().

◆ IterationGate()

esiaccel.esitester.IterationGate ( int  count_width)
Run an internal counter for `limit` iterations gated by `iter_xact`,
  and always report cycle telemetry for the active window.

  `start_pulse` asserts `active` (and clears the counters) for one cycle.
  `iter_xact` is the per-iteration handshake strobe; it feeds only a
  Counter clock enable. `active` clears the cycle after `iter_count`
  reaches `limit`.

  The consumer's channel-ready signal can flow into `iter_xact` without
  re-emerging combinationally through any output: only Counters (FFs)
  consume it.

  Telemetry reported under this instance's AppID:
      cycles : ui64
          Cycles `active` was asserted between `start_pulse` and
          `count_reached`; latched on `count_reached` so the host always
          reads the final value of the most recent run.

  Ports:
      start_pulse   : Input  Bits(1)
      limit         : Input  UInt(count_width)
      iter_xact     : Input  Bits(1)
      active        : Output Bits(1)            -- ControlReg, FF output
      count_reached : Output Bits(1)            -- iter_count == limit
      iter_count    : Output UInt(count_width)
      iters_left    : Output UInt(count_width)

Definition at line 65 of file esitester.py.

Referenced by esiaccel.esitester.BurstCommand().

◆ MMIOAdd()

Type[Module] esiaccel.esitester.MMIOAdd ( int  add_amt)

Definition at line 663 of file esitester.py.

References wrap().

Referenced by esiaccel.esitester.EsiTester.construct().

◆ ReadMem()

esiaccel.esitester.ReadMem ( int  width)

Definition at line 800 of file esitester.py.

References esiaccel.esitester.BurstCommand().

Referenced by esiaccel.esitester.EsiTester.construct().

◆ StreamingAdder()

esiaccel.esitester.StreamingAdder ( int  numItems)
Creates a StreamingAdder module parameterized by the number of items per
window frame. The module exposes a function which has an argument of struct
{add_amt, list<uint32>}. It then adds add_amt to each element of the list in
parallel (numItems at a time) and returns the resulting list.

Definition at line 232 of file esitester.py.

References wrap().

Referenced by esiaccel.esitester.EsiTester.construct().

◆ ToHostDMATest()

esiaccel.esitester.ToHostDMATest ( int  width)
Construct a module that sends the write count over a channel to the host
  the specified number of times. Exercises any DMA engine.

Definition at line 1022 of file esitester.py.

References wrap().

Referenced by esiaccel.esitester.EsiTester.construct().

◆ WriteMem()

Type[Module] esiaccel.esitester.WriteMem ( int  width)

Definition at line 904 of file esitester.py.

References esiaccel.esitester.BurstCommand(), and wrap().

Referenced by esiaccel.esitester.EsiTester.construct().

Variable Documentation

◆ _ESITESTER_SEQ_SEED

int esiaccel.esitester._ESITESTER_SEQ_SEED = 0x5A5A5A5A5A5A5A5A
protected

Definition at line 38 of file esitester.py.