Lowering information for a single signal flattened from an interface port. More...
#include <ImportVerilogInternals.h>
Public Attributes | |
| StringAttr | name |
| hw::ModulePort::Direction | direction |
| mlir::Type | type |
| Location | loc |
| BlockArgument | arg |
| const slang::ast::InterfacePortSymbol * | origin |
| the origin interface port symbol this was flattened from. | |
| const slang::ast::Symbol * | bodySym |
| the interface body member (VariableSymbol , NetSymbol) | |
Detailed Description
Lowering information for a single signal flattened from an interface port.
Definition at line 42 of file ImportVerilogInternals.h.
Member Data Documentation
◆ arg
| BlockArgument circt::ImportVerilog::FlattenedIfacePort::arg |
Definition at line 47 of file ImportVerilogInternals.h.
◆ bodySym
| const slang::ast::Symbol* circt::ImportVerilog::FlattenedIfacePort::bodySym |
the interface body member (VariableSymbol , NetSymbol)
Definition at line 51 of file ImportVerilogInternals.h.
◆ direction
| hw::ModulePort::Direction circt::ImportVerilog::FlattenedIfacePort::direction |
Definition at line 44 of file ImportVerilogInternals.h.
◆ loc
| Location circt::ImportVerilog::FlattenedIfacePort::loc |
Definition at line 46 of file ImportVerilogInternals.h.
◆ name
| StringAttr circt::ImportVerilog::FlattenedIfacePort::name |
Definition at line 43 of file ImportVerilogInternals.h.
Referenced by esiaccel.types.TypeAlias::__str__().
◆ origin
| const slang::ast::InterfacePortSymbol* circt::ImportVerilog::FlattenedIfacePort::origin |
the origin interface port symbol this was flattened from.
Definition at line 49 of file ImportVerilogInternals.h.
◆ type
| mlir::Type circt::ImportVerilog::FlattenedIfacePort::type |
Definition at line 45 of file ImportVerilogInternals.h.
Referenced by esiaccel.types.WritePort::__serialize_msg(), hw.HWModuleOp::add_entry_block(), esiaccel.types.Port::connect(), hw.HWModuleOp::input_indices(), fsm.MachineOp::instantiate(), hw.HWModuleOp::outputs(), and esiaccel.types.ReadPort::read().
The documentation for this struct was generated from the following file:
- /home/runner/work/circt-www/circt-www/circt_src/lib/Conversion/ImportVerilog/ImportVerilogInternals.h
