circt::LlhdToCorePipelineOptions Struct Reference

Convert LLHD dialect IR into core dialect IR. More...

#include <ImportVerilog.h>

Inheritance diagram for circt::LlhdToCorePipelineOptions:

Collaboration diagram for circt::LlhdToCorePipelineOptions:

Public Attributes
Option< bool >	detectMemories
Option< bool >	inferClockPorts
Option< bool >	sroa

Detailed Description

Convert LLHD dialect IR into core dialect IR.

Definition at line 176 of file ImportVerilog.h.

Member Data Documentation

detectMemories

Option<bool> circt::LlhdToCorePipelineOptions::detectMemories

Initial value:

{
      *this, "detect-memories",
      llvm::cl::desc("Detect memories and lower them to `seq.firmem`"),
      llvm::cl::init(true)}

Definition at line 178 of file ImportVerilog.h.

inferClockPorts

Option<bool> circt::LlhdToCorePipelineOptions::inferClockPorts

Initial value:

{
      *this, "infer-clock-ports",
      llvm::cl::desc("Retype `i1` ports used as clocks to `!seq.clock`"),
      llvm::cl::init(true)}

Definition at line 182 of file ImportVerilog.h.

sroa

Option<bool> circt::LlhdToCorePipelineOptions::sroa

Initial value:

{
      *this, "sroa",
      llvm::cl::desc("Destructure arrays and structs into individual signals. "
                     "See https://github.com/llvm/circt/issues/8804."),
      llvm::cl::init(false)}

Definition at line 186 of file ImportVerilog.h.

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The documentation for this struct was generated from the following file:

• /home/runner/work/circt-www/circt-www/circt_src/include/circt/Conversion/ImportVerilog.h