CIRCT 23.0.0git
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test_ram.py
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1from __future__ import annotations
2
3from pathlib import Path
4import random
5import sys
6import time
7from typing import cast
8
9import esiaccel as esi
10from esiaccel.accelerator import AcceleratorConnection
11from esiaccel.cosim.pytest import cosim_test
12
13HW_DIR = Path(__file__).resolve().parent.parent / "hw"
14
15
16def run(conn: AcceleratorConnection) -> None:
17 d = conn.build_accelerator()
18
19 mem_write = d.ports[esi.AppID("write")].write_port("req")
20 mem_write.connect()
21 mem_read_addr = d.ports[esi.AppID("read")].write_port("address")
22 mem_read_addr.connect()
23 mem_read_data = d.ports[esi.AppID("read")].read_port("data")
24 mem_read_data.connect()
25
26 # Baseline
27 m = conn.manifest()
28 # TODO: I broke this. Need to fix it.
29 # if (platform == "cosim"):
30 # MMIO method
31 # conn.cpp_accel.set_manifest_method(esi.esiCppAccel.ManifestMMIO)
32 # m_alt = conn.manifest()
33 # assert len(m.type_table) == len(m_alt.type_table)
34
35 info = m.module_infos
36 dummy_info = None
37 for i in info:
38 if i.name == "Dummy":
39 dummy_info = i
40 break
41 assert dummy_info is not None
42
43 def read(addr: int) -> bytearray:
44 mem_read_addr.write(addr)
45 resp = cast(bytearray, mem_read_data.read())
46 print(f"resp: {resp}")
47 return resp
48
49 # The contents of address 3 are continuously updated to the contents of
50 # address 2 by the accelerator.
51 data = bytearray([random.randint(0, 2**8 - 1) for _ in range(8)])
52 mem_write.write({"address": 2, "data": data})
53 resp = read(2)
54 try_count = 0
55
56 # Spin until the accelerator has updated the data. Only try a certain number
57 # of times. In practice, this should not be used (write should be a function
58 # which blocks until the write is complete). Since we are testing
59 # functionality, this is appropriate.
60 while resp != data and try_count < 10:
61 time.sleep(0.01)
62 try_count += 1
63 resp = read(2)
64 assert resp == data
65 resp = read(3)
66 assert resp == data
67
68 # Check this by writing to address 3 and reading from it. Shouldn't have
69 # changed.
70 resp = None
71 zeros = bytearray([0] * 8)
72 mem_write.write({"address": 3, "data": zeros})
73 try_count = 0
74 while resp != data and try_count < 10:
75 time.sleep(0.01)
76 try_count += 1
77 resp = read(3)
78 assert resp == data
79
80
81@cosim_test(HW_DIR / "esi_ram.py")
82def test_cosim_ram(conn: AcceleratorConnection) -> None:
83 run(conn)
84
85
86if __name__ == "__main__":
87 platform = sys.argv[1]
88 conn_str = sys.argv[2]
89 conn = esi.connect(platform, conn_str)
90 run(conn)
static void print(TypedAttr val, llvm::raw_ostream &os)
static mlir::Operation * resolve(Context &context, mlir::SymbolRefAttr sym)
None run(AcceleratorConnection conn)
Definition test_ram.py:16
None test_cosim_ram(AcceleratorConnection conn)
Definition test_ram.py:82