CIRCT 20.0.0git
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accelerator.py
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1# ===-----------------------------------------------------------------------===#
2# Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
3# See https://llvm.org/LICENSE.txt for license information.
4# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
5# ===-----------------------------------------------------------------------===#
6#
7# The structure of the Python classes and hierarchy roughly mirrors the C++
8# side, but wraps the C++ objects. The wrapper classes sometimes add convenience
9# functionality and serve to return wrapped versions of the returned objects.
10#
11# ===-----------------------------------------------------------------------===#
12
13from typing import Dict, List, Optional
14
15from .types import BundlePort
16from . import esiCppAccel as cpp
17
18# Global context for the C++ side.
19ctxt = cpp.Context()
20
21
23 """A connection to an ESI accelerator."""
24
25 def __init__(self, platform: str, connection_str: str):
26 self.cpp_accel = cpp.AcceleratorConnection(ctxt, platform, connection_str)
27
28 def manifest(self) -> cpp.Manifest:
29 """Get and parse the accelerator manifest."""
30 return cpp.Manifest(ctxt, self.cpp_accel.sysinfo().json_manifest())
31
32 def sysinfo(self) -> cpp.SysInfo:
33 return self.cpp_accel.sysinfo()
34
35 def build_accelerator(self) -> "Accelerator":
37
38 def get_service_mmio(self) -> cpp.MMIO:
39 return self.cpp_accel.get_service_mmio()
40
41 def get_service_hostmem(self) -> cpp.HostMem:
42 return self.cpp_accel.get_service_hostmem()
43
44
45from .esiCppAccel import HostMemOptions
46
47
49 """Represents either the top level or an instance of a hardware module."""
50
51 def __init__(self, parent: Optional["HWModule"], cpp_hwmodule: cpp.HWModule):
52 self.parent = parent
53 self.cpp_hwmodule = cpp_hwmodule
54
55 @property
56 def children(self) -> Dict[cpp.AppID, "Instance"]:
57 return {
58 name: Instance(self, inst)
59 for name, inst in self.cpp_hwmodule.children.items()
60 }
61
62 @property
63 def ports(self) -> Dict[cpp.AppID, BundlePort]:
64 return {
65 name: BundlePort(self, port)
66 for name, port in self.cpp_hwmodule.ports.items()
67 }
68
69 @property
70 def services(self) -> List[cpp.AppID]:
71 return self.cpp_hwmodule.services
72
73
74MMIO = cpp.MMIO
75
76
78 """Subclass of `HWModule` which represents a submodule instance. Adds an
79 AppID, which the top level doesn't have or need."""
80
81 def __init__(self, parent: Optional["HWModule"], cpp_instance: cpp.Instance):
82 super().__init__(parent, cpp_instance)
83 self.cpp_hwmodule: cpp.Instance = cpp_instance
84
85 @property
86 def id(self) -> cpp.AppID:
87 return self.cpp_hwmodule.id
88
89
91 """Root of the accelerator design hierarchy."""
92
93 def __init__(self, cpp_accelerator: cpp.Accelerator):
94 super().__init__(None, cpp_accelerator)
95 self.cpp_hwmodulecpp_hwmodule = cpp_accelerator
__init__(self, str platform, str connection_str)
__init__(self, cpp.Accelerator cpp_accelerator)
Dict[cpp.AppID, BundlePort] ports(self)
Dict[cpp.AppID, "Instance"] children(self)
__init__(self, Optional["HWModule"] parent, cpp.HWModule cpp_hwmodule)
List[cpp.AppID] services(self)
__init__(self, Optional["HWModule"] parent, cpp.Instance cpp_instance)