15 #include "mlir/IR/Builders.h"
16 #include "mlir/IR/DialectImplementation.h"
17 #include "llvm/ADT/TypeSwitch.h"
19 using namespace circt;
23 return TypeSwitch<Type, Type>(type)
24 .Case<InputType, OutputType,
InOutType, SignalType>(
25 [](
auto ty) {
return ty.getBaseType(); })
26 .Default([](
auto ty) {
return Type(); });
30 return llvm::TypeSwitch<Type, std::optional<size_t>>(type)
33 [](
auto ty) {
return ty.getWidth(); })
34 .Case<LogicType>([](
auto ty) {
return 1; })
35 .Default([](
auto ty) {
return std::nullopt; });
46 return llvm::hash_combine(pi.
name, pi.
type);
58 Type ModuleType::parse(AsmParser &odsParser) {
59 if (odsParser.parseLess())
63 if (odsParser.parseKeyword(&moduleName))
66 SmallVector<ModuleType::PortInfo> ports;
68 if (odsParser.parseCommaSeparatedList(
69 AsmParser::Delimiter::Paren, [&]() -> ParseResult {
72 if (odsParser.parseKeyword(&name) || odsParser.parseColon() ||
73 odsParser.parseType(port.type))
76 port.name = StringAttr::get(odsParser.getContext(), name);
77 ports.push_back(port);
83 if (odsParser.parseGreater())
86 return ModuleType::getChecked(
93 void ModuleType::print(AsmPrinter &odsPrinter)
const {
94 odsPrinter <<
'<' << getModuleName().getValue() <<
'(';
95 llvm::interleaveComma(getPorts(), odsPrinter, [&](
auto port) {
96 odsPrinter << port.name.getValue() <<
": " << port.type;
203 #define GET_TYPEDEF_CLASSES
204 #include "circt/Dialect/SystemC/SystemCTypes.cpp.inc"
206 void SystemCDialect::registerTypes() {
208 #define GET_TYPEDEF_LIST
209 #include "circt/Dialect/SystemC/SystemCTypes.cpp.inc"
220 template <
typename Ty>
224 auto *ctxt = parser.getContext();
226 if (parser.parseLess() || parser.parseInteger(
width) || parser.parseGreater())
235 llvm::SMLoc loc, Type &type) {
236 auto *ctxt = parser.getContext();
263 return parseIntegerOrBitVector<IntType>(parser, type);
265 return parseIntegerOrBitVector<UIntType>(parser, type);
267 return parseIntegerOrBitVector<BigIntType>(parser, type);
269 return parseIntegerOrBitVector<BigUIntType>(parser, type);
271 return parseIntegerOrBitVector<BitVectorType>(parser, type);
273 return parseIntegerOrBitVector<LogicVectorType>(parser, type);
279 return TypeSwitch<Type, LogicalResult>(type)
282 printer << ty.getMnemonic() <<
"<" << ty.getWidth() <<
">";
287 printer << ty.getMnemonic();
290 .Default([](
auto ty) {
return failure(); });
296 llvm::SMLoc loc = parser.getCurrentLocation();
299 mlir::OptionalParseResult result =
300 generatedTypeParser(parser, &mnemonic, type);
301 if (result.has_value() && !result.value())
305 if (result.has_value() && !result.value())
308 parser.emitError(loc) <<
"unknown type `" << mnemonic
309 <<
"` in dialect `systemc`";
314 void SystemCDialect::printType(Type type, DialectAsmPrinter &printer)
const {
315 if (succeeded(generatedTypePrinter(type, printer)) ||
319 assert(
false &&
"no printer for unknown `systemc` dialect type");
320 printer <<
"<<UnknownType>>";
assert(baseType &&"element must be base type")
static ParseResult parseType(Type &result, StringRef name, AsmParser &parser)
Parse a type defined by this dialect.
bool operator==(const ResetDomain &a, const ResetDomain &b)
static mlir::OptionalParseResult customTypeParser(DialectAsmParser &parser, StringRef mnemonic, llvm::SMLoc loc, Type &type)
static LogicalResult parseIntegerOrBitVector(DialectAsmParser &parser, Type &type)
static LogicalResult customTypePrinter(Type type, DialectAsmPrinter &printer)
Represents a finite word-length signed integer in SystemC as described in IEEE 1666-2011 §7....
static BigIntType get(MLIRContext *context, unsigned width)
static constexpr StringLiteral getMnemonic()
Represents a finite word-length unsigned integer in SystemC as described in IEEE 1666-2011 §7....
static constexpr StringLiteral getMnemonic()
static BigUIntType get(MLIRContext *context, unsigned width)
Represents a finite word-length bit vector in SystemC as described in IEEE 1666-2011 §7....
static constexpr StringLiteral getMnemonic()
static BitVectorBaseType get(MLIRContext *context)
Represents a finite word-length bit vector in SystemC as described in IEEE 1666-2011 §7....
static constexpr StringLiteral getMnemonic()
static BitVectorType get(MLIRContext *context, unsigned width)
Represents a limited word-length signed integer in SystemC as described in IEEE 1666-2011 §7....
static constexpr StringLiteral getMnemonic()
static IntBaseType get(MLIRContext *context)
Represents a limited word-length signed integer in SystemC as described in IEEE 1666-2011 §7....
static constexpr StringLiteral getMnemonic()
static IntType get(MLIRContext *context, unsigned width)
Represents a finite word-length bit vector in SystemC as described in IEEE 1666-2011 §7....
static LogicVectorBaseType get(MLIRContext *context)
static constexpr StringLiteral getMnemonic()
Represents a finite word-length bit vector (of four-state values) in SystemC as described in IEEE 166...
static LogicVectorType get(MLIRContext *context, unsigned width)
static constexpr StringLiteral getMnemonic()
Represents a finite word-length signed integer in SystemC as described in IEEE 1666-2011 §7....
static SignedType get(MLIRContext *context)
static constexpr StringLiteral getMnemonic()
Represents a limited word-length unsigned integer in SystemC as described in IEEE 1666-2011 §7....
static UIntBaseType get(MLIRContext *context)
static constexpr StringLiteral getMnemonic()
Represents a limited word-length unsigned integer in SystemC as described in IEEE 1666-2011 §7....
static UIntType get(MLIRContext *context, unsigned width)
static constexpr StringLiteral getMnemonic()
Represents a finite word-length unsigned integer in SystemC as described in IEEE 1666-2011 §7....
static constexpr StringLiteral getMnemonic()
static UnsignedType get(MLIRContext *context)
Direction get(bool isOutput)
Returns an output direction if isOutput is true, otherwise returns an input direction.
circt::hw::InOutType InOutType
llvm::hash_code hash_value(const PortInfo &pi)
Type getSignalBaseType(Type type)
Get the type wrapped by a signal or port (in, inout, out) type.
std::optional< size_t > getBitWidth(Type type)
Return the bitwidth of a type.
This file defines an intermediate representation for circuits acting as an abstraction for constraint...
inline ::llvm::hash_code hash_value(const FieldRef &fieldRef)
Get a hash code for a FieldRef.
Integer Type Storage and Uniquing.
bool operator==(const KeyTy &key) const
unsigned KeyTy
The hash key used for uniquing.
static llvm::hash_code hashKey(const KeyTy &key)
IntegerWidthStorage(unsigned width)
static IntegerWidthStorage * construct(mlir::TypeStorageAllocator &allocator, KeyTy key)
A struct containing minimal information for a systemc module port.