ImportVerilog Elaboration Phases for Hierarchical Names.
Hierarchical name resolution is performed in four distinct phases:
- Collection: The traverseInstanceBody pass walks the Slang AST to identify all hierarchical references (e.g., Top.sub.var). It records these in hierPaths mapped by module body.
- Port Generation: In convertModuleHeader, we inspect hierPaths for the module and add corresponding input/output ports to the generated moore.module to allow cross-module communication.
- Wiring: In Structure.cpp during instance creation, we look up the canonical module body's hierPaths to determine which hierarchical values need to be passed as inputs or captured as outputs from the instance.
- Resolution: In Expressions.cpp, visitors for rvalues and lvalues resolve hierarchical names by first checking function captures (inside a function body the capture argument must be used to respect region isolation), then the instance-aware hierValueSymbols map, and finally standard scoped lookups.
Definition at line 201 of file ImportVerilogInternals.h.