Temporary (base clock, enable) carrier wires at the top of mod, standing in for a wire/node alias of a gated clock.
More...
Collaboration diagram for circt::firrtl::GatedClockConversion::WirePairPlan:
Public Attributes | |
| FModuleOp | mod |
| MatRef | baseClk |
| unsigned | enableId |
| Location | loc |
Detailed Description
Temporary (base clock, enable) carrier wires at the top of mod, standing in for a wire/node alias of a gated clock.
Wires 2*i / 2*i+1 of plannedWireValues belong to wirePlans[i].
Definition at line 194 of file GatedClockConversion.h.
Member Data Documentation
◆ baseClk
| MatRef circt::firrtl::GatedClockConversion::WirePairPlan::baseClk |
Definition at line 196 of file GatedClockConversion.h.
◆ enableId
| unsigned circt::firrtl::GatedClockConversion::WirePairPlan::enableId |
Definition at line 197 of file GatedClockConversion.h.
◆ loc
| Location circt::firrtl::GatedClockConversion::WirePairPlan::loc |
Definition at line 198 of file GatedClockConversion.h.
◆ mod
| FModuleOp circt::firrtl::GatedClockConversion::WirePairPlan::mod |
Definition at line 195 of file GatedClockConversion.h.
The documentation for this struct was generated from the following file:
- /home/runner/work/circt-www/circt-www/circt_src/include/circt/Dialect/FIRRTL/GatedClockConversion.h
