22#include "mlir/IR/Builders.h"
23#include "mlir/IR/DialectImplementation.h"
24#include "mlir/IR/ImplicitLocOpBuilder.h"
25#include "mlir/IR/Threading.h"
26#include "mlir/Pass/Pass.h"
27#include "mlir/Transforms/DialectConversion.h"
29#define DEBUG_TYPE "lower-sim-to-sv"
32#define GEN_PASS_DEF_LOWERSIMTOSV
33#include "circt/Conversion/Passes.h.inc"
41struct SimConversionState {
43 bool usedSynthesisMacro =
false;
44 SetVector<StringAttr> dpiCallees;
49 explicit SimConversionPattern(MLIRContext *context, SimConversionState &state)
52 SimConversionState &state;
61 using SimConversionPattern<PlusArgsTestOp>::SimConversionPattern;
65 ConversionPatternRewriter &rewriter)
const final {
66 auto loc = op.getLoc();
67 auto resultType = rewriter.getIntegerType(1);
68 auto str = rewriter.create<sv::ConstantStrOp>(loc, op.getFormatString());
69 auto reg = rewriter.create<
sv::RegOp>(loc, resultType,
70 rewriter.getStringAttr(
"_pargs"));
71 rewriter.create<sv::InitialOp>(loc, [&] {
72 auto call = rewriter.create<sv::SystemFunctionOp>(
73 loc, resultType,
"test$plusargs", ArrayRef<Value>{str});
74 rewriter.create<sv::BPAssignOp>(loc, reg, call);
86 using SimConversionPattern<PlusArgsValueOp>::SimConversionPattern;
90 ConversionPatternRewriter &rewriter)
const final {
91 auto loc = op.getLoc();
93 auto i1ty = rewriter.getIntegerType(1);
94 auto type = op.getResult().getType();
96 auto regv = rewriter.create<
sv::RegOp>(loc, type,
97 rewriter.getStringAttr(
"_pargs_v_"));
98 auto regf = rewriter.create<
sv::RegOp>(loc, i1ty,
99 rewriter.getStringAttr(
"_pargs_f"));
101 state.usedSynthesisMacro =
true;
105 auto cstFalse = rewriter.create<
hw::ConstantOp>(loc, APInt(1, 0));
106 auto cstZ = rewriter.
create<sv::ConstantZOp>(loc, type);
107 auto assignZ = rewriter.create<
sv::AssignOp>(loc, regv, cstZ);
110 sv::SVAttributeAttr::get(
111 rewriter.getContext(),
112 "This dummy assignment exists to avoid undriven lint "
113 "warnings (e.g., Verilator UNDRIVEN).",
118 rewriter.
create<sv::InitialOp>(loc, [&] {
120 auto tmpResultType = rewriter.getIntegerType(32);
122 rewriter.
create<sv::ConstantStrOp>(loc, op.getFormatString());
123 auto call = rewriter.create<sv::SystemFunctionOp>(
124 loc, tmpResultType,
"value$plusargs",
125 ArrayRef<Value>{str, regv});
126 auto test = rewriter.create<comb::ICmpOp>(
127 loc, comb::ICmpPredicate::ne, call, zero32,
true);
128 rewriter.create<sv::BPAssignOp>(loc, regf, test);
136 readf = rewriter.
create<comb::ICmpOp>(loc, comb::ICmpPredicate::ceq, readf,
139 rewriter.replaceOp(op, {readf, readv});
144template <
typename FromOp,
typename ToOp>
147 using SimConversionPattern<FromOp>::SimConversionPattern;
151 ConversionPatternRewriter &rewriter)
const final {
152 auto loc = op.getLoc();
154 Value clockCast = rewriter.create<seq::FromClockOp>(loc, adaptor.getClk());
156 this->state.usedSynthesisMacro =
true;
158 loc,
"SYNTHESIS", [&] {},
160 rewriter.create<sv::AlwaysOp>(
161 loc, sv::EventControl::AtPosEdge, clockCast, [&] {
162 rewriter.create<sv::IfOp>(loc, adaptor.getCond(),
163 [&] { rewriter.create<ToOp>(loc); });
167 rewriter.eraseOp(op);
175 using SimConversionPattern<DPICallOp>::SimConversionPattern;
179 ConversionPatternRewriter &rewriter)
const final {
180 auto loc = op.getLoc();
182 state.dpiCallees.insert(op.getCalleeAttr().getAttr());
184 bool isClockedCall = !!op.getClock();
185 bool hasEnable = !!op.getEnable();
187 SmallVector<sv::RegOp> temporaries;
188 SmallVector<Value> reads;
189 for (
auto [type, result] :
190 llvm::zip(op.getResultTypes(), op.getResults())) {
191 temporaries.push_back(rewriter.create<
sv::RegOp>(op.getLoc(), type));
196 auto emitCall = [&]() {
197 auto call = rewriter.create<sv::FuncCallProceduralOp>(
198 op.getLoc(), op.getResultTypes(), op.getCalleeAttr(),
199 adaptor.getInputs());
200 for (
auto [lhs, rhs] : llvm::zip(temporaries, call.getResults())) {
202 rewriter.create<sv::PAssignOp>(op.getLoc(), lhs, rhs);
204 rewriter.create<sv::BPAssignOp>(op.getLoc(), lhs, rhs);
209 rewriter.create<seq::FromClockOp>(loc, adaptor.getClock());
210 rewriter.create<sv::AlwaysOp>(
211 loc, ArrayRef<sv::EventControl>{sv::EventControl::AtPosEdge},
212 ArrayRef<Value>{clockCast}, [&]() {
215 rewriter.create<sv::IfOp>(op.getLoc(), adaptor.getEnable(),
222 rewriter.create<sv::AlwaysCombOp>(loc, [&]() {
225 auto assignXToResults = [&] {
226 for (
auto lhs : temporaries) {
227 auto xValue = rewriter.create<sv::ConstantXOp>(
228 op.getLoc(), lhs.getType().getElementType());
229 rewriter.create<sv::BPAssignOp>(op.getLoc(), lhs, xValue);
232 rewriter.create<sv::IfOp>(op.getLoc(), adaptor.getEnable(), emitCall,
237 rewriter.replaceOp(op, reads);
247 void lower(sim::DPIFuncOp func);
249 ArrayRef<StringAttr> dpiCallees)
const;
253 ImplicitLocOpBuilder builder(func.getLoc(), func);
254 ArrayAttr inputLocsAttr, outputLocsAttr;
255 if (func.getArgumentLocs()) {
256 SmallVector<Attribute> inputLocs, outputLocs;
257 for (
auto [port, loc] :
258 llvm::zip(func.getModuleType().getPorts(),
259 func.getArgumentLocsAttr().getAsRange<LocationAttr>())) {
263 inputLocsAttr = builder.getArrayAttr(inputLocs);
264 outputLocsAttr = builder.getArrayAttr(outputLocs);
268 builder.create<sv::FuncOp>(func.getSymNameAttr(), func.getModuleType(),
269 func.getPerArgumentAttrsAttr(), inputLocsAttr,
270 outputLocsAttr, func.getVerilogNameAttr());
272 svFuncDecl.setPrivate();
274 func.getSymNameAttr().getValue(),
"dpi_import_fragument"));
278 "__CIRCT_DPI_IMPORT", func.getSymNameAttr().getValue().upper()));
279 builder.create<emit::FragmentOp>(name, [&]() {
281 macroDecl.getSymNameAttr(), []() {},
283 builder.create<sv::FuncDPIImportOp>(func.getSymNameAttr(),
285 builder.create<sv::MacroDefOp>(macroDecl.getSymNameAttr(),
"");
294 ArrayRef<StringAttr> dpiCallees)
const {
295 llvm::SetVector<Attribute> fragments;
297 if (
auto exstingFragments =
298 module->getAttrOfType<ArrayAttr>(emit::getFragmentsAttrName()))
299 for (
auto fragment : exstingFragments.getAsRange<FlatSymbolRefAttr>())
300 fragments.insert(fragment);
301 for (
auto callee : dpiCallees) {
303 fragments.insert(FlatSymbolRefAttr::get(attr));
305 if (!fragments.empty())
307 emit::getFragmentsAttrName(),
308 ArrayAttr::get(module.getContext(), fragments.takeVector()));
312struct SimToSVPass :
public circt::impl::LowerSimToSVBase<SimToSVPass> {
313 void runOnOperation()
override {
314 auto circuit = getOperation();
315 MLIRContext *context = &getContext();
320 llvm::make_early_inc_range(circuit.getOps<sim::DPIFuncOp>()))
321 lowerDPIFunc.lower(func);
323 std::atomic<bool> usedSynthesisMacro =
false;
325 SimConversionState state;
326 ConversionTarget target(*context);
327 target.addIllegalDialect<SimDialect>();
328 target.addLegalDialect<sv::SVDialect>();
329 target.addLegalDialect<hw::HWDialect>();
330 target.addLegalDialect<seq::SeqDialect>();
331 target.addLegalDialect<comb::CombDialect>();
333 RewritePatternSet
patterns(context);
341 auto result = applyPartialConversion(module, target, std::move(
patterns));
347 lowerDPIFunc.addFragments(module, state.dpiCallees.takeVector());
349 if (state.usedSynthesisMacro)
350 usedSynthesisMacro =
true;
354 if (failed(mlir::failableParallelForEach(
356 return signalPassFailure();
358 if (usedSynthesisMacro) {
359 Operation *op = circuit.lookupSymbol(
"SYNTHESIS");
361 if (!isa<sv::MacroDeclOp>(op)) {
362 op->emitOpError(
"should be a macro declaration");
363 return signalPassFailure();
366 auto builder = ImplicitLocOpBuilder::atBlockBegin(
367 UnknownLoc::get(context), circuit.getBody());
368 builder.create<sv::MacroDeclOp>(
"SYNTHESIS");
376 return std::make_unique<SimToSVPass>();
LogicalResult matchAndRewrite(DPICallOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const final
LogicalResult matchAndRewrite(PlusArgsTestOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const final
LogicalResult matchAndRewrite(PlusArgsValueOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const final
LogicalResult matchAndRewrite(FromOp op, typename FromOp::Adaptor adaptor, ConversionPatternRewriter &rewriter) const final
A namespace that is used to store existing names and generate new names in some scope within the IR.
void add(mlir::ModuleOp module)
StringRef newName(const Twine &name)
Return a unique name, derived from the input name, and add the new name to the internal namespace.
void setSVAttributes(mlir::Operation *op, mlir::ArrayAttr attrs)
Set the SV attributes of an operation.
The InstanceGraph op interface, see InstanceGraphInterface.td for more details.
std::unique_ptr< mlir::Pass > createLowerSimToSVPass()
circt::Namespace nameSpace
void lower(sim::DPIFuncOp func)
void addFragments(hw::HWModuleOp module, ArrayRef< StringAttr > dpiCallees) const
llvm::DenseMap< StringAttr, StringAttr > symbolToFragment
LowerDPIFunc(mlir::ModuleOp module)