22#include "mlir/IR/Builders.h"
23#include "mlir/IR/DialectImplementation.h"
24#include "mlir/IR/ImplicitLocOpBuilder.h"
25#include "mlir/IR/Threading.h"
26#include "mlir/Pass/Pass.h"
27#include "mlir/Transforms/DialectConversion.h"
29#define DEBUG_TYPE "lower-sim-to-sv"
32#define GEN_PASS_DEF_LOWERSIMTOSV
33#include "circt/Conversion/Passes.h.inc"
41struct SimConversionState {
43 bool usedSynthesisMacro =
false;
44 SetVector<StringAttr> dpiCallees;
49 explicit SimConversionPattern(MLIRContext *context, SimConversionState &state)
52 SimConversionState &state;
61 using SimConversionPattern<PlusArgsTestOp>::SimConversionPattern;
65 ConversionPatternRewriter &rewriter)
const final {
66 auto loc = op.getLoc();
67 auto resultType = rewriter.getIntegerType(1);
68 auto str = rewriter.create<sv::ConstantStrOp>(loc, op.getFormatString());
69 auto reg = rewriter.create<
sv::RegOp>(loc, resultType,
70 rewriter.getStringAttr(
"_pargs"));
71 rewriter.create<sv::InitialOp>(loc, [&] {
72 auto call = rewriter.create<sv::SystemFunctionOp>(
73 loc, resultType,
"test$plusargs", ArrayRef<Value>{str});
74 rewriter.create<sv::BPAssignOp>(loc, reg, call);
86 using SimConversionPattern<PlusArgsValueOp>::SimConversionPattern;
90 ConversionPatternRewriter &rewriter)
const final {
91 auto loc = op.getLoc();
93 auto i1ty = rewriter.getIntegerType(1);
94 auto type = op.getResult().getType();
97 loc, type, rewriter.getStringAttr(
"_pargs_v"));
99 loc, i1ty, rewriter.getStringAttr(
"_pargs_f"));
101 state.usedSynthesisMacro =
true;
106 auto cstZ = rewriter.
create<sv::ConstantZOp>(loc, type);
107 auto assignZ = rewriter.create<
sv::AssignOp>(loc, wirev, cstZ);
110 sv::SVAttributeAttr::get(
111 rewriter.getContext(),
112 "This dummy assignment exists to avoid undriven lint "
113 "warnings (e.g., Verilator UNDRIVEN).",
118 auto i32ty = rewriter.getIntegerType(32);
120 loc, i32ty, rewriter.getStringAttr(
"_found"));
122 loc, type, rewriter.getStringAttr(
"_value"));
123 rewriter.create<sv::InitialOp>(loc, [&] {
125 rewriter.create<sv::ConstantStrOp>(loc, op.getFormatString());
126 auto call = rewriter.create<sv::SystemFunctionOp>(
127 loc, i32ty,
"value$plusargs", ArrayRef<Value>{str, regv});
128 rewriter.create<sv::BPAssignOp>(loc, regf, call);
134 auto cmp = rewriter.
create<comb::ICmpOp>(
135 loc, comb::ICmpPredicate::ceq, readRegF, cstTrue);
143 rewriter.replaceOp(op, {readf, readv});
148template <
typename FromOp,
typename ToOp>
151 using SimConversionPattern<FromOp>::SimConversionPattern;
155 ConversionPatternRewriter &rewriter)
const final {
156 auto loc = op.getLoc();
158 Value clockCast = rewriter.create<seq::FromClockOp>(loc, adaptor.getClk());
160 this->state.usedSynthesisMacro =
true;
162 loc,
"SYNTHESIS", [&] {},
164 rewriter.create<sv::AlwaysOp>(
165 loc, sv::EventControl::AtPosEdge, clockCast, [&] {
166 rewriter.create<sv::IfOp>(loc, adaptor.getCond(),
167 [&] { rewriter.create<ToOp>(loc); });
171 rewriter.eraseOp(op);
179 using SimConversionPattern<DPICallOp>::SimConversionPattern;
183 ConversionPatternRewriter &rewriter)
const final {
184 auto loc = op.getLoc();
186 state.dpiCallees.insert(op.getCalleeAttr().getAttr());
188 bool isClockedCall = !!op.getClock();
189 bool hasEnable = !!op.getEnable();
191 SmallVector<sv::RegOp> temporaries;
192 SmallVector<Value> reads;
193 for (
auto [type, result] :
194 llvm::zip(op.getResultTypes(), op.getResults())) {
195 temporaries.push_back(rewriter.create<
sv::RegOp>(op.getLoc(), type));
200 auto emitCall = [&]() {
201 auto call = rewriter.create<sv::FuncCallProceduralOp>(
202 op.getLoc(), op.getResultTypes(), op.getCalleeAttr(),
203 adaptor.getInputs());
204 for (
auto [lhs, rhs] : llvm::zip(temporaries, call.getResults())) {
206 rewriter.create<sv::PAssignOp>(op.getLoc(), lhs, rhs);
208 rewriter.create<sv::BPAssignOp>(op.getLoc(), lhs, rhs);
213 rewriter.create<seq::FromClockOp>(loc, adaptor.getClock());
214 rewriter.create<sv::AlwaysOp>(
215 loc, ArrayRef<sv::EventControl>{sv::EventControl::AtPosEdge},
216 ArrayRef<Value>{clockCast}, [&]() {
219 rewriter.create<sv::IfOp>(op.getLoc(), adaptor.getEnable(),
226 rewriter.create<sv::AlwaysCombOp>(loc, [&]() {
229 auto assignXToResults = [&] {
230 for (
auto lhs : temporaries) {
231 auto xValue = rewriter.create<sv::ConstantXOp>(
232 op.getLoc(), lhs.getType().getElementType());
233 rewriter.create<sv::BPAssignOp>(op.getLoc(), lhs, xValue);
236 rewriter.create<sv::IfOp>(op.getLoc(), adaptor.getEnable(), emitCall,
241 rewriter.replaceOp(op, reads);
251 void lower(sim::DPIFuncOp func);
253 ArrayRef<StringAttr> dpiCallees)
const;
257 ImplicitLocOpBuilder builder(func.getLoc(), func);
258 ArrayAttr inputLocsAttr, outputLocsAttr;
259 if (func.getArgumentLocs()) {
260 SmallVector<Attribute> inputLocs, outputLocs;
261 for (
auto [port, loc] :
262 llvm::zip(func.getModuleType().getPorts(),
263 func.getArgumentLocsAttr().getAsRange<LocationAttr>())) {
267 inputLocsAttr = builder.getArrayAttr(inputLocs);
268 outputLocsAttr = builder.getArrayAttr(outputLocs);
272 builder.create<sv::FuncOp>(func.getSymNameAttr(), func.getModuleType(),
273 func.getPerArgumentAttrsAttr(), inputLocsAttr,
274 outputLocsAttr, func.getVerilogNameAttr());
276 svFuncDecl.setPrivate();
278 func.getSymNameAttr().getValue(),
"dpi_import_fragument"));
282 "__CIRCT_DPI_IMPORT", func.getSymNameAttr().getValue().upper()));
283 builder.create<emit::FragmentOp>(name, [&]() {
285 macroDecl.getSymNameAttr(), []() {},
287 builder.create<sv::FuncDPIImportOp>(func.getSymNameAttr(),
289 builder.create<sv::MacroDefOp>(macroDecl.getSymNameAttr(),
"");
298 ArrayRef<StringAttr> dpiCallees)
const {
299 llvm::SetVector<Attribute> fragments;
301 if (
auto exstingFragments =
302 module->getAttrOfType<ArrayAttr>(emit::getFragmentsAttrName()))
303 for (
auto fragment : exstingFragments.getAsRange<FlatSymbolRefAttr>())
304 fragments.insert(fragment);
305 for (
auto callee : dpiCallees) {
307 fragments.insert(FlatSymbolRefAttr::get(attr));
309 if (!fragments.empty())
311 emit::getFragmentsAttrName(),
312 ArrayAttr::get(module.getContext(), fragments.takeVector()));
316struct SimToSVPass :
public circt::impl::LowerSimToSVBase<SimToSVPass> {
317 void runOnOperation()
override {
318 auto circuit = getOperation();
319 MLIRContext *context = &getContext();
324 llvm::make_early_inc_range(circuit.getOps<sim::DPIFuncOp>()))
325 lowerDPIFunc.lower(func);
327 std::atomic<bool> usedSynthesisMacro =
false;
329 SimConversionState state;
330 ConversionTarget target(*context);
331 target.addIllegalDialect<SimDialect>();
332 target.addLegalDialect<sv::SVDialect>();
333 target.addLegalDialect<hw::HWDialect>();
334 target.addLegalDialect<seq::SeqDialect>();
335 target.addLegalDialect<comb::CombDialect>();
337 RewritePatternSet
patterns(context);
345 auto result = applyPartialConversion(module, target, std::move(
patterns));
351 lowerDPIFunc.addFragments(module, state.dpiCallees.takeVector());
353 if (state.usedSynthesisMacro)
354 usedSynthesisMacro =
true;
358 if (failed(mlir::failableParallelForEach(
360 return signalPassFailure();
362 if (usedSynthesisMacro) {
363 Operation *op = circuit.lookupSymbol(
"SYNTHESIS");
365 if (!isa<sv::MacroDeclOp>(op)) {
366 op->emitOpError(
"should be a macro declaration");
367 return signalPassFailure();
370 auto builder = ImplicitLocOpBuilder::atBlockBegin(
371 UnknownLoc::get(context), circuit.getBody());
372 builder.create<sv::MacroDeclOp>(
"SYNTHESIS");
380 return std::make_unique<SimToSVPass>();
LogicalResult matchAndRewrite(DPICallOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const final
LogicalResult matchAndRewrite(PlusArgsTestOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const final
LogicalResult matchAndRewrite(PlusArgsValueOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const final
LogicalResult matchAndRewrite(FromOp op, typename FromOp::Adaptor adaptor, ConversionPatternRewriter &rewriter) const final
A namespace that is used to store existing names and generate new names in some scope within the IR.
void add(mlir::ModuleOp module)
StringRef newName(const Twine &name)
Return a unique name, derived from the input name, and add the new name to the internal namespace.
create(data_type, name=None, sym_name=None)
void setSVAttributes(mlir::Operation *op, mlir::ArrayAttr attrs)
Set the SV attributes of an operation.
The InstanceGraph op interface, see InstanceGraphInterface.td for more details.
std::unique_ptr< mlir::Pass > createLowerSimToSVPass()
circt::Namespace nameSpace
void lower(sim::DPIFuncOp func)
void addFragments(hw::HWModuleOp module, ArrayRef< StringAttr > dpiCallees) const
llvm::DenseMap< StringAttr, StringAttr > symbolToFragment
LowerDPIFunc(mlir::ModuleOp module)