SimToSV.cpp

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//===- LowerSimToSV.cpp - Sim to SV lowering ------------------------------===//
//
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
//
//===----------------------------------------------------------------------===//
//
// This transform translates Sim ops to SV.
//
//===----------------------------------------------------------------------===//
 
#include "circt/Conversion/SimToSV.h"
#include "circt/Conversion/SVLoweringUtils.h"
#include "circt/Dialect/Comb/CombOps.h"
#include "circt/Dialect/Emit/EmitOps.h"
#include "circt/Dialect/HW/HWOps.h"
#include "circt/Dialect/SV/SVOps.h"
#include "circt/Dialect/Seq/SeqOps.h"
#include "circt/Dialect/Sim/SimDialect.h"
#include "circt/Dialect/Sim/SimOps.h"
#include "circt/Dialect/Sim/SimTypes.h"
#include "circt/Support/Namespace.h"
#include "circt/Support/ProceduralRegionTrait.h"
#include "circt/Support/SparseOpSCC.h"
#include "mlir/IR/Builders.h"
#include "mlir/IR/BuiltinOps.h"
#include "mlir/IR/DialectImplementation.h"
#include "mlir/IR/ImplicitLocOpBuilder.h"
#include "mlir/IR/Threading.h"
#include "mlir/IR/Visitors.h"
#include "mlir/Pass/Pass.h"
#include "mlir/Transforms/DialectConversion.h"
#include "llvm/ADT/Twine.h"
#include "llvm/Support/LogicalResult.h"
 
#define DEBUG_TYPE "lower-sim-to-sv"
 
namespace circt {
#define GEN_PASS_DEF_LOWERSIMTOSV
#include "circt/Conversion/Passes.h.inc"
} // namespace circt
 
using namespace circt;
using namespace sim;
using namespace mlir;
 
/// Check whether an op should be placed inside an ifdef guard that prevents it
/// from affecting synthesis runs.
static bool needsIfdefGuard(Operation *op) {
  return isa<ClockedTerminateOp, ClockedPauseOp, TerminateOp, PauseOp>(op);
}
 
/// Check whether an op should be placed inside an always process triggered on a
/// clock, and an if statement checking for a condition.
static std::pair<Value, Value> needsClockAndConditionWrapper(Operation *op) {
  return TypeSwitch<Operation *, std::pair<Value, Value>>(op)
      .Case<ClockedTerminateOp, ClockedPauseOp>(
          [](auto op) -> std::pair<Value, Value> {
            return {op.getClock(), op.getCondition()};
          })
      .Default({});
}
 
namespace {
 
struct SimConversionState {
  hw::HWModuleOp module;
  bool usedSynthesisMacro = false;
  bool usedFileDescriptorRuntime = false;
  SetVector<StringAttr> dpiCallees;
};
 
struct SimTypeConverter : public TypeConverter {
  explicit SimTypeConverter(MLIRContext *context) {
    addConversion([](Type type) { return type; });
    addConversion([&](OutputStreamType type) -> Type {
      return IntegerType::get(type.getContext(), 32);
    });
  }
};
 
template <typename T>
struct SimConversionPattern : public OpConversionPattern<T> {
  explicit SimConversionPattern(MLIRContext *context, SimConversionState &state)
      : OpConversionPattern<T>(context), state(state) {}
 
  SimConversionState &state;
};
 
hw::ModuleType
DPIFunctionTypeToHWModuleType(const DPIFunctionType &dpiFuncType) {
  SmallVector<hw::ModulePort> hwPorts;
  for (auto &arg : dpiFuncType.getArguments()) {
    hw::ModulePort::Direction hwDir;
    switch (arg.dir) {
    case DPIDirection::Input:
    case DPIDirection::Ref:
      hwDir = hw::ModulePort::Direction::Input;
      break;
    case DPIDirection::Output:
    case DPIDirection::Return:
      hwDir = hw::ModulePort::Direction::Output;
      break;
    case DPIDirection::InOut:
      hwDir = hw::ModulePort::Direction::InOut;
      break;
    }
    hwPorts.push_back({arg.name, arg.type, hwDir});
  }
  return hw::ModuleType::get(dpiFuncType.getContext(), hwPorts);
}
} // namespace
 
// Lower `sim.plusargs.test` to a standard SV implementation.
//
class PlusArgsTestLowering : public SimConversionPattern<PlusArgsTestOp> {
public:
  using SimConversionPattern<PlusArgsTestOp>::SimConversionPattern;
 
  LogicalResult
  matchAndRewrite(PlusArgsTestOp op, OpAdaptor adaptor,
                  ConversionPatternRewriter &rewriter) const final {
    auto loc = op.getLoc();
    auto resultType = rewriter.getIntegerType(1);
    auto str = sv::ConstantStrOp::create(rewriter, loc, op.getFormatString());
    auto reg = sv::RegOp::create(rewriter, loc, resultType,
                                 rewriter.getStringAttr("_pargs"));
    sv::InitialOp::create(rewriter, loc, [&] {
      auto call = sv::SystemFunctionOp::create(
          rewriter, loc, resultType, "test$plusargs", ArrayRef<Value>{str});
      sv::BPAssignOp::create(rewriter, loc, reg, call);
    });
 
    rewriter.replaceOpWithNewOp<sv::ReadInOutOp>(op, reg);
    return success();
  }
};
 
// Lower `sim.plusargs.value` to a standard SV implementation.
//
class PlusArgsValueLowering : public SimConversionPattern<PlusArgsValueOp> {
public:
  using SimConversionPattern<PlusArgsValueOp>::SimConversionPattern;
 
  LogicalResult
  matchAndRewrite(PlusArgsValueOp op, OpAdaptor adaptor,
                  ConversionPatternRewriter &rewriter) const final {
    auto loc = op.getLoc();
 
    auto i1ty = rewriter.getIntegerType(1);
    auto type = op.getResult().getType();
 
    auto wirev = sv::WireOp::create(rewriter, loc, type,
                                    rewriter.getStringAttr("_pargs_v"));
    auto wiref = sv::WireOp::create(rewriter, loc, i1ty,
                                    rewriter.getStringAttr("_pargs_f"));
 
    state.usedSynthesisMacro = true;
    sv::IfDefOp::create(
        rewriter, loc, "SYNTHESIS",
        [&]() {
          auto cstFalse = hw::ConstantOp::create(rewriter, loc, APInt(1, 0));
          auto cstZ = sv::ConstantZOp::create(rewriter, loc, type);
          auto assignZ = sv::AssignOp::create(rewriter, loc, wirev, cstZ);
          circt::sv::setSVAttributes(
              assignZ,
              sv::SVAttributeAttr::get(
                  rewriter.getContext(),
                  "This dummy assignment exists to avoid undriven lint "
                  "warnings (e.g., Verilator UNDRIVEN).",
                  /*emitAsComment=*/true));
          sv::AssignOp::create(rewriter, loc, wiref, cstFalse);
        },
        [&]() {
          auto i32ty = rewriter.getIntegerType(32);
          auto regf = sv::RegOp::create(rewriter, loc, i32ty,
                                        rewriter.getStringAttr("_found"));
          auto regv = sv::RegOp::create(rewriter, loc, type,
                                        rewriter.getStringAttr("_value"));
          sv::InitialOp::create(rewriter, loc, [&] {
            auto str =
                sv::ConstantStrOp::create(rewriter, loc, op.getFormatString());
            auto call = sv::SystemFunctionOp::create(
                rewriter, loc, i32ty, "value$plusargs",
                ArrayRef<Value>{str, regv});
            sv::BPAssignOp::create(rewriter, loc, regf, call);
          });
          Value readRegF = sv::ReadInOutOp::create(rewriter, loc, regf);
          Value readRegV = sv::ReadInOutOp::create(rewriter, loc, regv);
          auto cstTrue = hw::ConstantOp::create(rewriter, loc, i32ty, 1);
          // Squash any X coming from the regf to 0.
          auto cmp = comb::ICmpOp::create(
              rewriter, loc, comb::ICmpPredicate::ceq, readRegF, cstTrue);
          sv::AssignOp::create(rewriter, loc, wiref, cmp);
          sv::AssignOp::create(rewriter, loc, wirev, readRegV);
        });
 
    Value readf = sv::ReadInOutOp::create(rewriter, loc, wiref);
    Value readv = sv::ReadInOutOp::create(rewriter, loc, wirev);
 
    rewriter.replaceOp(op, {readf, readv});
    return success();
  }
};
 
template <typename OpTy, unsigned StreamValue>
class StreamLowering : public OpConversionPattern<OpTy> {
public:
  using OpConversionPattern<OpTy>::OpConversionPattern;
  using OpAdaptor = typename OpConversionPattern<OpTy>::OpAdaptor;
 
  LogicalResult
  matchAndRewrite(OpTy op, OpAdaptor adaptor,
                  ConversionPatternRewriter &rewriter) const final {
    auto streamValue =
        hw::ConstantOp::create(rewriter, op.getLoc(), APInt(32, StreamValue));
    rewriter.replaceOp(op, streamValue);
    return success();
  }
};
 
using StdoutStreamLowering = StreamLowering<StdoutStreamOp, 0x80000001>;
using StderrStreamLowering = StreamLowering<StderrStreamOp, 0x80000002>;
 
class UnrealizedConversionCastLowering
    : public OpConversionPattern<mlir::UnrealizedConversionCastOp> {
public:
  using OpConversionPattern<
      mlir::UnrealizedConversionCastOp>::OpConversionPattern;
 
  LogicalResult
  matchAndRewrite(mlir::UnrealizedConversionCastOp op, OpAdaptor adaptor,
                  ConversionPatternRewriter &rewriter) const final {
    SmallVector<Type> convertedResultTypes;
    if (failed(typeConverter->convertTypes(op.getResultTypes(),
                                           convertedResultTypes)))
      return failure();
 
    if (!llvm::equal(convertedResultTypes, adaptor.getOperands().getTypes()))
      return failure();
 
    rewriter.replaceOp(op, adaptor.getOperands());
    return success();
  }
};
 
static LogicalResult convert(ClockedTerminateOp op, PatternRewriter &rewriter) {
  if (op.getSuccess())
    rewriter.replaceOpWithNewOp<sv::FinishOp>(op, op.getVerbose());
  else
    rewriter.replaceOpWithNewOp<sv::FatalProceduralOp>(op, op.getVerbose());
  return success();
}
 
static LogicalResult convert(ClockedPauseOp op, PatternRewriter &rewriter) {
  rewriter.replaceOpWithNewOp<sv::StopOp>(op, op.getVerbose());
  return success();
}
 
static LogicalResult convert(TerminateOp op, PatternRewriter &rewriter) {
  if (op.getSuccess())
    rewriter.replaceOpWithNewOp<sv::FinishOp>(op, op.getVerbose());
  else
    rewriter.replaceOpWithNewOp<sv::FatalProceduralOp>(op, op.getVerbose());
  return success();
}
 
static LogicalResult convert(PauseOp op, PatternRewriter &rewriter) {
  rewriter.replaceOpWithNewOp<sv::StopOp>(op, op.getVerbose());
  return success();
}
 
class TriggeredLowering : public SimConversionPattern<TriggeredOp> {
public:
  using SimConversionPattern<TriggeredOp>::SimConversionPattern;
 
  LogicalResult
  matchAndRewrite(TriggeredOp op, OpAdaptor adaptor,
                  ConversionPatternRewriter &rewriter) const final {
    auto loc = op.getLoc();
    state.usedSynthesisMacro = true;
 
    sv::IfDefOp::create(
        rewriter, loc, "SYNTHESIS", [] {},
        [&] {
          auto trigger =
              seq::FromClockOp::create(rewriter, loc, adaptor.getClock());
          auto alwaysOp = sv::AlwaysOp::create(
              rewriter, loc,
              ArrayRef<sv::EventControl>{sv::EventControl::AtPosEdge},
              ArrayRef<Value>{trigger});
 
          Block *destination = alwaysOp.getBodyBlock();
          if (auto condition = adaptor.getCondition()) {
            rewriter.setInsertionPointToStart(destination);
            destination = sv::IfOp::create(rewriter, loc, condition, [] {
                          }).getThenBlock();
          }
 
          rewriter.mergeBlocks(op.getBodyBlock(), destination);
        });
    rewriter.eraseOp(op);
    return success();
  }
};
 
class FlushLowering : public OpConversionPattern<FlushOp> {
public:
  using OpConversionPattern<FlushOp>::OpConversionPattern;
 
  LogicalResult
  matchAndRewrite(FlushOp op, OpAdaptor adaptor,
                  ConversionPatternRewriter &rewriter) const final {
    Value fd = adaptor.getStream();
    if (!fd.getType().isInteger(32))
      return rewriter.notifyMatchFailure(op, "expected converted i32 stream");
    rewriter.replaceOpWithNewOp<sv::FFlushOp>(op, fd);
    return success();
  }
};
 
class DPICallLowering : public SimConversionPattern<DPICallOp> {
public:
  using SimConversionPattern<DPICallOp>::SimConversionPattern;
 
  LogicalResult
  matchAndRewrite(DPICallOp op, OpAdaptor adaptor,
                  ConversionPatternRewriter &rewriter) const final {
    auto loc = op.getLoc();
    // Record the callee.
    state.dpiCallees.insert(op.getCalleeAttr().getAttr());
 
    bool isClockedCall = !!op.getClock();
    bool hasEnable = !!op.getEnable();
 
    SmallVector<sv::RegOp> temporaries;
    SmallVector<Value> reads;
    for (auto [type, result] :
         llvm::zip(op.getResultTypes(), op.getResults())) {
      temporaries.push_back(sv::RegOp::create(rewriter, op.getLoc(), type));
      reads.push_back(
          sv::ReadInOutOp::create(rewriter, op.getLoc(), temporaries.back()));
    }
 
    auto emitCall = [&]() {
      auto call = sv::FuncCallProceduralOp::create(
          rewriter, op.getLoc(), op.getResultTypes(), op.getCalleeAttr(),
          adaptor.getInputs());
      for (auto [lhs, rhs] : llvm::zip(temporaries, call.getResults())) {
        if (isClockedCall)
          sv::PAssignOp::create(rewriter, op.getLoc(), lhs, rhs);
        else
          sv::BPAssignOp::create(rewriter, op.getLoc(), lhs, rhs);
      }
    };
    if (isClockedCall) {
      Value clockCast =
          seq::FromClockOp::create(rewriter, loc, adaptor.getClock());
      sv::AlwaysOp::create(
          rewriter, loc,
          ArrayRef<sv::EventControl>{sv::EventControl::AtPosEdge},
          ArrayRef<Value>{clockCast}, [&]() {
            if (!hasEnable)
              return emitCall();
            sv::IfOp::create(rewriter, op.getLoc(), adaptor.getEnable(),
                             emitCall);
          });
    } else {
      // Unclocked call is lowered into always_comb.
      // TODO: If there is a return value and no output argument, use an
      // unclocked call op.
      sv::AlwaysCombOp::create(rewriter, loc, [&]() {
        if (!hasEnable)
          return emitCall();
        auto assignXToResults = [&] {
          for (auto lhs : temporaries) {
            auto xValue = sv::ConstantXOp::create(
                rewriter, op.getLoc(), lhs.getType().getElementType());
            sv::BPAssignOp::create(rewriter, op.getLoc(), lhs, xValue);
          }
        };
        sv::IfOp::create(rewriter, op.getLoc(), adaptor.getEnable(), emitCall,
                         assignXToResults);
      });
    }
 
    rewriter.replaceOp(op, reads);
    return success();
  }
};
 
// A helper struct to lower DPI function/call.
struct LowerDPIFunc {
  llvm::DenseMap<StringAttr, StringAttr> symbolToFragment;
  circt::Namespace nameSpace;
  LowerDPIFunc(mlir::ModuleOp module) { nameSpace.add(module); }
  void lower(sim::DPIFuncOp func);
};
 
static ArrayAttr buildSVPerArgumentAttrs(MLIRContext *context,
                                         sim::DPIFuncOp func) {
  Builder builder(context);
  SmallVector<Attribute> convertedAttrs;
  auto dpiType = func.getDpiFunctionType();
  auto dpiArgs = dpiType.getArguments();
  convertedAttrs.reserve(dpiArgs.size());
  for (auto &arg : dpiArgs) {
    NamedAttrList newAttrs;
    if (arg.dir == sim::DPIDirection::Return)
      newAttrs.append(
          builder.getStringAttr(sv::FuncOp::getExplicitlyReturnedAttrName()),
          builder.getUnitAttr());
    convertedAttrs.push_back(newAttrs.getDictionary(context));
  }
  return ArrayAttr::get(context, convertedAttrs);
}
 
void LowerDPIFunc::lower(sim::DPIFuncOp func) {
  ImplicitLocOpBuilder builder(func.getLoc(), func);
  ArrayAttr inputLocsAttr, outputLocsAttr;
 
  // Build ModuleType from DPI arguments for sv::FuncOp.
  auto moduleType = DPIFunctionTypeToHWModuleType(func.getDpiFunctionType());
 
  if (func.getArgumentLocs()) {
    SmallVector<Attribute> inputLocs, outputLocs;
    auto hwPorts = moduleType.getPorts();
    for (auto [port, loc] : llvm::zip(
             hwPorts, func.getArgumentLocsAttr().getAsRange<LocationAttr>())) {
      (port.dir == hw::ModulePort::Output ? outputLocs : inputLocs)
          .push_back(loc);
    }
    inputLocsAttr = builder.getArrayAttr(inputLocs);
    outputLocsAttr = builder.getArrayAttr(outputLocs);
  }
 
  auto svFuncDecl = sv::FuncOp::create(
      builder, func.getSymNameAttr(), moduleType,
      buildSVPerArgumentAttrs(builder.getContext(), func), inputLocsAttr,
      outputLocsAttr, func.getVerilogNameAttr());
  // DPI function is a declaration so it must be a private function.
  svFuncDecl.setPrivate();
  auto name = builder.getStringAttr(nameSpace.newName(
      func.getSymNameAttr().getValue(), "dpi_import_fragument"));
 
  // Add include guards to avoid duplicate declarations. See Issue 7458.
  auto macroDecl = sv::MacroDeclOp::create(
      builder, nameSpace.newName("__CIRCT_DPI_IMPORT",
                                 func.getSymNameAttr().getValue().upper()));
  emit::FragmentOp::create(builder, name, [&]() {
    sv::IfDefOp::create(
        builder, macroDecl.getSymNameAttr(), []() {},
        [&]() {
          sv::FuncDPIImportOp::create(builder, func.getSymNameAttr(),
                                      StringAttr());
          sv::MacroDefOp::create(builder, macroDecl.getSymNameAttr(), "");
        });
  });
 
  symbolToFragment.insert({func.getSymNameAttr(), name});
  func.erase();
}
 
static void
addFragments(hw::HWModuleOp module,
             const llvm::DenseMap<StringAttr, StringAttr> &symbolToFragment,
             const SimConversionState &state) {
  llvm::SetVector<Attribute> fragments;
  // Add existing emit fragments.
  if (auto exstingFragments =
          module->getAttrOfType<ArrayAttr>(emit::getFragmentsAttrName()))
    for (auto fragment : exstingFragments.getAsRange<FlatSymbolRefAttr>())
      fragments.insert(fragment);
  for (auto callee : state.dpiCallees) {
    auto attr = symbolToFragment.at(callee);
    fragments.insert(FlatSymbolRefAttr::get(attr));
  }
  if (state.usedFileDescriptorRuntime)
    fragments.insert(sv::getFileDescriptorFragmentRef(module.getContext()));
  if (!fragments.empty())
    module->setAttr(
        emit::getFragmentsAttrName(),
        ArrayAttr::get(module.getContext(), fragments.takeVector()));
}
 
static bool moveOpsIntoIfdefGuardsAndProcesses(Operation *rootOp) {
  bool usedSynthesisMacro = false;
 
  rootOp->walk<WalkOrder::PreOrder>([&](Operation *op) {
    // `sim.triggered` is lowered as a whole later on. Do not pre-wrap the
    // ops nested inside it here, or we may create redundant/invalid
    // structure.
    if (isa<TriggeredOp>(op))
      return WalkResult::skip();
 
    auto loc = op->getLoc();
 
    // Move the op into an ifdef guard if needed.
    if (needsIfdefGuard(op)) {
      // Try to reuse an ifdef guard immediately before the op.
      Block *block = nullptr;
      if (op->getPrevNode())
        block = TypeSwitch<Operation *, Block *>(op->getPrevNode())
                    .Case<sv::IfDefOp, sv::IfDefProceduralOp>(
                        [&](auto guardOp) -> Block * {
                          if (guardOp.getCond().getIdent().getAttr() ==
                                  "SYNTHESIS" &&
                              guardOp.hasElse())
                            return guardOp.getElseBlock();
                          return nullptr;
                        })
                    .Default([](auto) { return nullptr; });
 
      // If there was no pre-existing guard, create one.
      if (!block) {
        OpBuilder builder(op);
        if (isInProceduralRegion(op))
          block = sv::IfDefProceduralOp::create(
                      builder, loc, "SYNTHESIS", [] {}, [] {})
                      .getElseBlock();
        else
          block = sv::IfDefOp::create(
                      builder, loc, "SYNTHESIS", [] {}, [] {})
                      .getElseBlock();
        usedSynthesisMacro = true;
      }
 
      // Move the op into the guard block.
      op->moveBefore(block, block->end());
    }
 
    // Check if the op requires an clock and condition wrapper.
    auto [clock, condition] = needsClockAndConditionWrapper(op);
 
    // Create an enclosing always process.
    if (clock) {
      // Try to reuse an always process immediately before the op.
      Block *block = nullptr;
      if (auto alwaysOp = dyn_cast_or_null<sv::AlwaysOp>(op->getPrevNode()))
        if (alwaysOp.getNumConditions() == 1 &&
            alwaysOp.getCondition(0).event == sv::EventControl::AtPosEdge)
          if (auto clockOp = alwaysOp.getCondition(0)
                                 .value.getDefiningOp<seq::FromClockOp>())
            if (clockOp.getInput() == clock)
              block = alwaysOp.getBodyBlock();
 
      // If there was no pre-existing always process, create one.
      if (!block) {
        OpBuilder builder(op);
        clock = seq::FromClockOp::create(builder, loc, clock);
        block = sv::AlwaysOp::create(builder, loc, sv::EventControl::AtPosEdge,
                                     clock, [] {})
                    .getBodyBlock();
      }
 
      // Move the op into the process.
      op->moveBefore(block, block->end());
    }
 
    // Create an enclosing if condition.
    if (condition) {
      // Try to reuse an if statement immediately before the op.
      Block *block = nullptr;
      if (auto ifOp = dyn_cast_or_null<sv::IfOp>(op->getPrevNode()))
        if (ifOp.getCond() == condition)
          block = ifOp.getThenBlock();
 
      // If there was no pre-existing if statement, create one.
      if (!block) {
        OpBuilder builder(op);
        block = sv::IfOp::create(builder, loc, condition, [] {}).getThenBlock();
      }
 
      // Move the op into the if body.
      op->moveBefore(block, block->end());
    }
    return WalkResult::advance();
  });
 
  return usedSynthesisMacro;
}
 
namespace {
 
void appendLiteralToSVFormat(SmallString<128> &formatString,
                             StringRef literal) {
  for (char ch : literal) {
    if (ch == '%')
      formatString += "%%";
    else
      formatString.push_back(ch);
  }
}
 
LogicalResult appendIntegerSpecifier(SmallString<128> &formatString,
                                     bool isLeftAligned, uint8_t paddingChar,
                                     std::optional<int32_t> width, char spec) {
  formatString.push_back('%');
  if (isLeftAligned)
    formatString.push_back('-');
 
  // SystemVerilog formatting only has built-in support for '0' and ' '. Keep
  // this lowering strict to avoid silently changing formatting semantics.
  if (paddingChar == '0')
    formatString.push_back('0');
  else if (paddingChar != ' ')
    return failure();
 
  if (width.has_value())
    llvm::Twine(width.value()).toVector(formatString);
 
  formatString.push_back(spec);
  return success();
}
 
void appendFloatSpecifier(SmallString<128> &formatString, bool isLeftAligned,
                          std::optional<int32_t> fieldWidth, int32_t fracDigits,
                          char spec) {
  formatString.push_back('%');
  if (isLeftAligned)
    formatString.push_back('-');
  if (fieldWidth.has_value())
    llvm::Twine(fieldWidth.value()).toVector(formatString);
  formatString.push_back('.');
  llvm::Twine(fracDigits).toVector(formatString);
  formatString.push_back(spec);
}
 
LogicalResult getFlattenedFormatFragments(Value input,
                                          SmallVectorImpl<Value> &fragments) {
  if (auto concat = input.getDefiningOp<FormatStringConcatOp>()) {
    if (failed(concat.getFlattenedInputs(fragments)))
      return mlir::emitError(input.getLoc(),
                             "cyclic sim.fmt.concat is unsupported");
    return success();
  }
 
  fragments.push_back(input);
  return success();
}
 
LogicalResult appendFormatFragmentToSVFormat(Value fragment,
                                             SmallString<128> &formatString,
                                             SmallVectorImpl<Value> &args,
                                             OpBuilder &builder) {
  Operation *fragmentOp = fragment.getDefiningOp();
  if (!fragmentOp)
    return mlir::emitError(fragment.getLoc(),
                           "block argument format strings are unsupported");
 
  return TypeSwitch<Operation *, LogicalResult>(fragmentOp)
      .Case<FormatLiteralOp>([&](auto literal) -> LogicalResult {
        appendLiteralToSVFormat(formatString, literal.getLiteral());
        return success();
      })
      .Case<FormatCurrentTimeOp>([&](auto fmt) -> LogicalResult {
        formatString += "%0t";
        args.push_back(sv::TimeOp::create(builder, fmt.getLoc()));
        return success();
      })
      .Case<FormatHierPathOp>([&](auto hierPath) -> LogicalResult {
        formatString += hierPath.getUseEscapes() ? "%M" : "%m";
        return success();
      })
      .Case<FormatCharOp>([&](auto fmt) -> LogicalResult {
        formatString += "%c";
        args.push_back(fmt.getValue());
        return success();
      })
      .Case<FormatDecOp>([&](auto fmt) -> LogicalResult {
        if (failed(appendIntegerSpecifier(formatString, fmt.getIsLeftAligned(),
                                          fmt.getPaddingChar(),
                                          fmt.getSpecifierWidth(), 'd'))) {
          return mlir::emitError(fmt.getLoc())
                 << "sim.fmt.dec only supports paddingChar 32 (' ') or 48 "
                    "('0')";
        }
        // Match sim.fmt.dec signedness semantics explicitly in SV.
        if (fmt.getIsSigned()) {
          auto signedValue = sv::SystemFunctionOp::create(
              builder, fmt.getLoc(), fmt.getValue().getType(), "signed",
              ValueRange{fmt.getValue()});
          args.push_back(signedValue);
        } else {
          auto unsignedValue = sv::SystemFunctionOp::create(
              builder, fmt.getLoc(), fmt.getValue().getType(), "unsigned",
              ValueRange{fmt.getValue()});
          args.push_back(unsignedValue);
        }
        return success();
      })
      .Case<FormatHexOp>([&](auto fmt) -> LogicalResult {
        if (failed(appendIntegerSpecifier(
                formatString, fmt.getIsLeftAligned(), fmt.getPaddingChar(),
                fmt.getSpecifierWidth(),
                fmt.getIsHexUppercase() ? 'X' : 'x'))) {
          return mlir::emitError(fmt.getLoc())
                 << "sim.fmt.hex only supports paddingChar 32 (' ') or 48 "
                    "('0')";
        }
        args.push_back(fmt.getValue());
        return success();
      })
      .Case<FormatOctOp>([&](auto fmt) -> LogicalResult {
        if (failed(appendIntegerSpecifier(formatString, fmt.getIsLeftAligned(),
                                          fmt.getPaddingChar(),
                                          fmt.getSpecifierWidth(), 'o'))) {
          return mlir::emitError(fmt.getLoc())
                 << "sim.fmt.oct only supports paddingChar 32 (' ') or 48 "
                    "('0')";
        }
        args.push_back(fmt.getValue());
        return success();
      })
      .Case<FormatBinOp>([&](auto fmt) -> LogicalResult {
        if (failed(appendIntegerSpecifier(formatString, fmt.getIsLeftAligned(),
                                          fmt.getPaddingChar(),
                                          fmt.getSpecifierWidth(), 'b'))) {
          return mlir::emitError(fmt.getLoc())
                 << "sim.fmt.bin only supports paddingChar 32 (' ') or 48 "
                    "('0')";
        }
        args.push_back(fmt.getValue());
        return success();
      })
      .Case<FormatScientificOp>([&](auto fmt) -> LogicalResult {
        appendFloatSpecifier(formatString, fmt.getIsLeftAligned(),
                             fmt.getFieldWidth(), fmt.getFracDigits(), 'e');
        args.push_back(fmt.getValue());
        return success();
      })
      .Case<FormatFloatOp>([&](auto fmt) -> LogicalResult {
        appendFloatSpecifier(formatString, fmt.getIsLeftAligned(),
                             fmt.getFieldWidth(), fmt.getFracDigits(), 'f');
        args.push_back(fmt.getValue());
        return success();
      })
      .Case<FormatGeneralOp>([&](auto fmt) -> LogicalResult {
        appendFloatSpecifier(formatString, fmt.getIsLeftAligned(),
                             fmt.getFieldWidth(), fmt.getFracDigits(), 'g');
        args.push_back(fmt.getValue());
        return success();
      })
      .Default([&](auto unsupportedOp) {
        return mlir::emitError(unsupportedOp->getLoc())
               << "unsupported format fragment '"
               << unsupportedOp->getName().getStringRef() << "'";
      });
}
 
LogicalResult lowerFormatStringToSVFormat(Value input,
                                          SmallString<128> &formatString,
                                          SmallVectorImpl<Value> &args,
                                          OpBuilder &builder) {
  SmallVector<Value, 8> fragments;
  if (failed(getFlattenedFormatFragments(input, fragments)))
    return failure();
  for (auto fragment : fragments)
    if (failed(appendFormatFragmentToSVFormat(fragment, formatString, args,
                                              builder)))
      return failure();
  return success();
}
 
FailureOr<Value> createFileDescriptorGetterForGetFile(GetFileOp getFileOp,
                                                      OpBuilder &builder) {
  SmallString<128> formatString;
  SmallVector<Value> args;
  if (failed(lowerFormatStringToSVFormat(getFileOp.getFileName(), formatString,
                                         args, builder))) {
    getFileOp.emitError("cannot lower 'sim.get_file' to SystemVerilog")
            .attachNote(getFileOp.getFileName().getLoc())
        << "while lowering file name";
    return failure();
  }
 
  Value fileName =
      args.empty()
          ? sv::ConstantStrOp::create(builder, getFileOp.getLoc(),
                                      builder.getStringAttr(formatString))
                .getResult()
          : sv::SFormatFOp::create(builder, getFileOp.getLoc(),
                                   builder.getStringAttr(formatString), args)
                .getResult();
 
  return sv::createProceduralFileDescriptorGetterCall(
      builder, getFileOp.getLoc(), fileName);
}
 
static void cleanupDeadSimFmtOps(ArrayRef<Operation *> seedOps) {
  auto filter = [](Operation *op, OpOperand &operand) {
    return isa<FormatStringType>(operand.get().getType()) &&
           isa_and_present<SimDialect>(op->getDialect());
  };
 
  SparseOpSCC<OpSCCDirection::Backward> sccs(filter);
  sccs.visit(seedOps);
  assert(sccs.getNumCyclicSCCs() == 0 &&
         "Cyclic graph should have been rejected");
 
  for (OpSCC entry : sccs.reverseTopological()) {
    auto *op = cast<Operation *>(entry);
    if (op->use_empty())
      op->erase();
    else
      op->emitWarning("sim format/stream op still has users after lowering; "
                      "dialect conversion will fail");
  }
}
 
LogicalResult lowerPrintFormattedProcToSV(hw::HWModuleOp module,
                                          const TypeConverter &typeConverter,
                                          SimConversionState &state) {
  SmallVector<GetFileOp> getFileOps;
  SmallVector<PrintFormattedProcOp> printOps;
  SmallVector<Operation *, 8> cleanupSeeds;
  module.walk([&](Operation *op) {
    if (auto getFileOp = dyn_cast<GetFileOp>(op))
      getFileOps.push_back(getFileOp);
    if (auto printOp = dyn_cast<PrintFormattedProcOp>(op))
      printOps.push_back(printOp);
  });
 
  for (auto getFileOp : getFileOps) {
    OpBuilder builder(getFileOp);
    auto fdOrFailure = createFileDescriptorGetterForGetFile(getFileOp, builder);
    if (failed(fdOrFailure))
      return failure();
 
    auto stream = mlir::UnrealizedConversionCastOp::create(
        builder, getFileOp.getLoc(), getFileOp.getResult().getType(),
        *fdOrFailure);
    getFileOp.replaceAllUsesWith(stream.getResult(0));
    state.usedFileDescriptorRuntime = true;
    state.usedSynthesisMacro = true;
    cleanupSeeds.push_back(getFileOp);
  }
 
  for (auto printOp : printOps) {
    OpBuilder builder(printOp);
    SmallString<128> formatString;
    SmallVector<Value> args;
    if (failed(lowerFormatStringToSVFormat(printOp.getInput(), formatString,
                                           args, builder))) {
      printOp.emitError("cannot lower 'sim.proc.print' to SystemVerilog")
              .attachNote(printOp.getInput().getLoc())
          << "while lowering format string";
      return failure();
    }
    auto stream = printOp.getStream();
    if (!stream) {
      // no stream is specified, emit sv.write.
      sv::WriteOp::create(builder, printOp.getLoc(), formatString, args);
    } else {
      auto fdType = typeConverter.convertType(stream.getType());
      assert(fdType && "expected output stream type conversion");
      Value fd = mlir::UnrealizedConversionCastOp::create(
                     builder, printOp.getLoc(), fdType, stream)
                     ->getResult(0);
      sv::FWriteOp::create(builder, printOp.getLoc(), fd, formatString, args);
    }
    cleanupSeeds.push_back(printOp);
  }
 
  cleanupDeadSimFmtOps(cleanupSeeds);
 
  return success();
}
 
struct SimToSVPass : public circt::impl::LowerSimToSVBase<SimToSVPass> {
  void runOnOperation() override {
    auto circuit = getOperation();
    MLIRContext *context = &getContext();
    LowerDPIFunc lowerDPIFunc(circuit);
 
    // Lower DPI functions.
    for (auto func :
         llvm::make_early_inc_range(circuit.getOps<sim::DPIFuncOp>()))
      lowerDPIFunc.lower(func);
 
    std::atomic<bool> usedSynthesisMacro = false;
    std::atomic<bool> usedFileDescriptorRuntime = false;
    auto lowerModule = [&](hw::HWModuleOp module) {
      SimTypeConverter typeConverter(context);
      SimConversionState state;
 
      if (failed(lowerPrintFormattedProcToSV(module, typeConverter, state)))
        return failure();
 
      if (moveOpsIntoIfdefGuardsAndProcesses(module))
        usedSynthesisMacro = true;
 
      ConversionTarget target(*context);
      target.addIllegalDialect<SimDialect>();
      target.addLegalDialect<sv::SVDialect>();
      target.addLegalDialect<hw::HWDialect>();
      target.addLegalDialect<seq::SeqDialect>();
      target.addLegalDialect<comb::CombDialect>();
      target.addDynamicallyLegalOp<mlir::UnrealizedConversionCastOp>(
          [&](mlir::UnrealizedConversionCastOp op) {
            return typeConverter.isLegal(op);
          });
 
      RewritePatternSet patterns(context);
      patterns.add<PlusArgsTestLowering>(context, state);
      patterns.add<PlusArgsValueLowering>(context, state);
      patterns.add<StdoutStreamLowering>(typeConverter, context);
      patterns.add<StderrStreamLowering>(typeConverter, context);
      patterns.add<FlushLowering>(typeConverter, context);
      patterns.add<UnrealizedConversionCastLowering>(typeConverter, context);
      patterns.add<ClockedTerminateOp>(convert);
      patterns.add<ClockedPauseOp>(convert);
      patterns.add<TerminateOp>(convert);
      patterns.add<PauseOp>(convert);
      patterns.add<TriggeredLowering>(context, state);
      patterns.add<DPICallLowering>(context, state);
      auto result = applyPartialConversion(module, target, std::move(patterns));
 
      if (failed(result))
        return result;
 
      // Set the emit fragments required by this module.
      addFragments(module, lowerDPIFunc.symbolToFragment, state);
 
      if (state.usedSynthesisMacro)
        usedSynthesisMacro = true;
      if (state.usedFileDescriptorRuntime)
        usedFileDescriptorRuntime = true;
      return result;
    };
 
    if (failed(mlir::failableParallelForEach(
            context, circuit.getOps<hw::HWModuleOp>(), lowerModule)))
      return signalPassFailure();
 
    if (usedSynthesisMacro) {
      Operation *op = circuit.lookupSymbol("SYNTHESIS");
      if (op) {
        if (!isa<sv::MacroDeclOp>(op)) {
          op->emitOpError("should be a macro declaration");
          return signalPassFailure();
        }
      } else {
        auto builder = ImplicitLocOpBuilder::atBlockBegin(
            UnknownLoc::get(context), circuit.getBody());
        sv::MacroDeclOp::create(builder, "SYNTHESIS");
      }
    }
 
    if (usedFileDescriptorRuntime) {
      auto builder = ImplicitLocOpBuilder::atBlockBegin(
          UnknownLoc::get(context), circuit.getBody());
      sv::emitFileDescriptorRuntime(circuit, builder);
    }
  }
};
} // anonymous namespace
 
std::unique_ptr<Pass> circt::createLowerSimToSVPass() {
  return std::make_unique<SimToSVPass>();
}