CIRCT 21.0.0git
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SimToSV.cpp
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1//===- LowerSimToSV.cpp - Sim to SV lowering ------------------------------===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This transform translates Sim ops to SV.
10//
11//===----------------------------------------------------------------------===//
12
22#include "mlir/IR/Builders.h"
23#include "mlir/IR/DialectImplementation.h"
24#include "mlir/IR/ImplicitLocOpBuilder.h"
25#include "mlir/IR/Threading.h"
26#include "mlir/Pass/Pass.h"
27#include "mlir/Transforms/DialectConversion.h"
28
29#define DEBUG_TYPE "lower-sim-to-sv"
30
31namespace circt {
32#define GEN_PASS_DEF_LOWERSIMTOSV
33#include "circt/Conversion/Passes.h.inc"
34} // namespace circt
35
36using namespace circt;
37using namespace sim;
38
39namespace {
40
41struct SimConversionState {
42 hw::HWModuleOp module;
43 bool usedSynthesisMacro = false;
44 SetVector<StringAttr> dpiCallees;
45};
46
47template <typename T>
48struct SimConversionPattern : public OpConversionPattern<T> {
49 explicit SimConversionPattern(MLIRContext *context, SimConversionState &state)
50 : OpConversionPattern<T>(context), state(state) {}
51
52 SimConversionState &state;
53};
54
55} // namespace
56
57// Lower `sim.plusargs.test` to a standard SV implementation.
58//
59class PlusArgsTestLowering : public SimConversionPattern<PlusArgsTestOp> {
60public:
61 using SimConversionPattern<PlusArgsTestOp>::SimConversionPattern;
62
63 LogicalResult
64 matchAndRewrite(PlusArgsTestOp op, OpAdaptor adaptor,
65 ConversionPatternRewriter &rewriter) const final {
66 auto loc = op.getLoc();
67 auto resultType = rewriter.getIntegerType(1);
68 auto str = rewriter.create<sv::ConstantStrOp>(loc, op.getFormatString());
69 auto reg = rewriter.create<sv::RegOp>(loc, resultType,
70 rewriter.getStringAttr("_pargs"));
71 rewriter.create<sv::InitialOp>(loc, [&] {
72 auto call = rewriter.create<sv::SystemFunctionOp>(
73 loc, resultType, "test$plusargs", ArrayRef<Value>{str});
74 rewriter.create<sv::BPAssignOp>(loc, reg, call);
75 });
76
77 rewriter.replaceOpWithNewOp<sv::ReadInOutOp>(op, reg);
78 return success();
79 }
80};
81
82// Lower `sim.plusargs.value` to a standard SV implementation.
83//
84class PlusArgsValueLowering : public SimConversionPattern<PlusArgsValueOp> {
85public:
86 using SimConversionPattern<PlusArgsValueOp>::SimConversionPattern;
87
88 LogicalResult
89 matchAndRewrite(PlusArgsValueOp op, OpAdaptor adaptor,
90 ConversionPatternRewriter &rewriter) const final {
91 auto loc = op.getLoc();
92
93 auto i1ty = rewriter.getIntegerType(1);
94 auto type = op.getResult().getType();
95
96 auto regv = rewriter.create<sv::RegOp>(loc, type,
97 rewriter.getStringAttr("_pargs_v_"));
98 auto regf = rewriter.create<sv::RegOp>(loc, i1ty,
99 rewriter.getStringAttr("_pargs_f"));
100
101 state.usedSynthesisMacro = true;
102 rewriter.create<sv::IfDefOp>(
103 loc, "SYNTHESIS",
104 [&]() {
105 auto cstFalse = rewriter.create<hw::ConstantOp>(loc, APInt(1, 0));
106 auto cstZ = rewriter.create<sv::ConstantZOp>(loc, type);
107 auto assignZ = rewriter.create<sv::AssignOp>(loc, regv, cstZ);
109 assignZ,
110 sv::SVAttributeAttr::get(
111 rewriter.getContext(),
112 "This dummy assignment exists to avoid undriven lint "
113 "warnings (e.g., Verilator UNDRIVEN).",
114 /*emitAsComment=*/true));
115 rewriter.create<sv::AssignOp>(loc, regf, cstFalse);
116 },
117 [&]() {
118 rewriter.create<sv::InitialOp>(loc, [&] {
119 auto zero32 = rewriter.create<hw::ConstantOp>(loc, APInt(32, 0));
120 auto tmpResultType = rewriter.getIntegerType(32);
121 auto str =
122 rewriter.create<sv::ConstantStrOp>(loc, op.getFormatString());
123 auto call = rewriter.create<sv::SystemFunctionOp>(
124 loc, tmpResultType, "value$plusargs",
125 ArrayRef<Value>{str, regv});
126 auto test = rewriter.create<comb::ICmpOp>(
127 loc, comb::ICmpPredicate::ne, call, zero32, true);
128 rewriter.create<sv::BPAssignOp>(loc, regf, test);
129 });
130 });
131
132 Value readf = rewriter.create<sv::ReadInOutOp>(loc, regf);
133 Value readv = rewriter.create<sv::ReadInOutOp>(loc, regv);
134
135 auto cstTrue = rewriter.create<hw::ConstantOp>(loc, APInt(1, 1));
136 readf = rewriter.create<comb::ICmpOp>(loc, comb::ICmpPredicate::ceq, readf,
137 cstTrue);
138
139 rewriter.replaceOp(op, {readf, readv});
140 return success();
141 }
142};
143
144template <typename FromOp, typename ToOp>
145class SimulatorStopLowering : public SimConversionPattern<FromOp> {
146public:
147 using SimConversionPattern<FromOp>::SimConversionPattern;
148
149 LogicalResult
150 matchAndRewrite(FromOp op, typename FromOp::Adaptor adaptor,
151 ConversionPatternRewriter &rewriter) const final {
152 auto loc = op.getLoc();
153
154 Value clockCast = rewriter.create<seq::FromClockOp>(loc, adaptor.getClk());
155
156 this->state.usedSynthesisMacro = true;
157 rewriter.create<sv::IfDefOp>(
158 loc, "SYNTHESIS", [&] {},
159 [&] {
160 rewriter.create<sv::AlwaysOp>(
161 loc, sv::EventControl::AtPosEdge, clockCast, [&] {
162 rewriter.create<sv::IfOp>(loc, adaptor.getCond(),
163 [&] { rewriter.create<ToOp>(loc); });
164 });
165 });
166
167 rewriter.eraseOp(op);
168
169 return success();
170 }
171};
172
173class DPICallLowering : public SimConversionPattern<DPICallOp> {
174public:
175 using SimConversionPattern<DPICallOp>::SimConversionPattern;
176
177 LogicalResult
178 matchAndRewrite(DPICallOp op, OpAdaptor adaptor,
179 ConversionPatternRewriter &rewriter) const final {
180 auto loc = op.getLoc();
181 // Record the callee.
182 state.dpiCallees.insert(op.getCalleeAttr().getAttr());
183
184 bool isClockedCall = !!op.getClock();
185 bool hasEnable = !!op.getEnable();
186
187 SmallVector<sv::RegOp> temporaries;
188 SmallVector<Value> reads;
189 for (auto [type, result] :
190 llvm::zip(op.getResultTypes(), op.getResults())) {
191 temporaries.push_back(rewriter.create<sv::RegOp>(op.getLoc(), type));
192 reads.push_back(
193 rewriter.create<sv::ReadInOutOp>(op.getLoc(), temporaries.back()));
194 }
195
196 auto emitCall = [&]() {
197 auto call = rewriter.create<sv::FuncCallProceduralOp>(
198 op.getLoc(), op.getResultTypes(), op.getCalleeAttr(),
199 adaptor.getInputs());
200 for (auto [lhs, rhs] : llvm::zip(temporaries, call.getResults())) {
201 if (isClockedCall)
202 rewriter.create<sv::PAssignOp>(op.getLoc(), lhs, rhs);
203 else
204 rewriter.create<sv::BPAssignOp>(op.getLoc(), lhs, rhs);
205 }
206 };
207 if (isClockedCall) {
208 Value clockCast =
209 rewriter.create<seq::FromClockOp>(loc, adaptor.getClock());
210 rewriter.create<sv::AlwaysOp>(
211 loc, ArrayRef<sv::EventControl>{sv::EventControl::AtPosEdge},
212 ArrayRef<Value>{clockCast}, [&]() {
213 if (!hasEnable)
214 return emitCall();
215 rewriter.create<sv::IfOp>(op.getLoc(), adaptor.getEnable(),
216 emitCall);
217 });
218 } else {
219 // Unclocked call is lowered into always_comb.
220 // TODO: If there is a return value and no output argument, use an
221 // unclocked call op.
222 rewriter.create<sv::AlwaysCombOp>(loc, [&]() {
223 if (!hasEnable)
224 return emitCall();
225 auto assignXToResults = [&] {
226 for (auto lhs : temporaries) {
227 auto xValue = rewriter.create<sv::ConstantXOp>(
228 op.getLoc(), lhs.getType().getElementType());
229 rewriter.create<sv::BPAssignOp>(op.getLoc(), lhs, xValue);
230 }
231 };
232 rewriter.create<sv::IfOp>(op.getLoc(), adaptor.getEnable(), emitCall,
233 assignXToResults);
234 });
235 }
236
237 rewriter.replaceOp(op, reads);
238 return success();
239 }
240};
241
242// A helper struct to lower DPI function/call.
244 llvm::DenseMap<StringAttr, StringAttr> symbolToFragment;
246 LowerDPIFunc(mlir::ModuleOp module) { nameSpace.add(module); }
247 void lower(sim::DPIFuncOp func);
248 void addFragments(hw::HWModuleOp module,
249 ArrayRef<StringAttr> dpiCallees) const;
250};
251
252void LowerDPIFunc::lower(sim::DPIFuncOp func) {
253 ImplicitLocOpBuilder builder(func.getLoc(), func);
254 ArrayAttr inputLocsAttr, outputLocsAttr;
255 if (func.getArgumentLocs()) {
256 SmallVector<Attribute> inputLocs, outputLocs;
257 for (auto [port, loc] :
258 llvm::zip(func.getModuleType().getPorts(),
259 func.getArgumentLocsAttr().getAsRange<LocationAttr>())) {
260 (port.dir == hw::ModulePort::Output ? outputLocs : inputLocs)
261 .push_back(loc);
262 }
263 inputLocsAttr = builder.getArrayAttr(inputLocs);
264 outputLocsAttr = builder.getArrayAttr(outputLocs);
265 }
266
267 auto svFuncDecl =
268 builder.create<sv::FuncOp>(func.getSymNameAttr(), func.getModuleType(),
269 func.getPerArgumentAttrsAttr(), inputLocsAttr,
270 outputLocsAttr, func.getVerilogNameAttr());
271 // DPI function is a declaration so it must be a private function.
272 svFuncDecl.setPrivate();
273 auto name = builder.getStringAttr(nameSpace.newName(
274 func.getSymNameAttr().getValue(), "dpi_import_fragument"));
275
276 // Add include guards to avoid duplicate declarations. See Issue 7458.
277 auto macroDecl = builder.create<sv::MacroDeclOp>(nameSpace.newName(
278 "__CIRCT_DPI_IMPORT", func.getSymNameAttr().getValue().upper()));
279 builder.create<emit::FragmentOp>(name, [&]() {
280 builder.create<sv::IfDefOp>(
281 macroDecl.getSymNameAttr(), []() {},
282 [&]() {
283 builder.create<sv::FuncDPIImportOp>(func.getSymNameAttr(),
284 StringAttr());
285 builder.create<sv::MacroDefOp>(macroDecl.getSymNameAttr(), "");
286 });
287 });
288
289 symbolToFragment.insert({func.getSymNameAttr(), name});
290 func.erase();
291}
292
294 ArrayRef<StringAttr> dpiCallees) const {
295 llvm::SetVector<Attribute> fragments;
296 // Add existing emit fragments.
297 if (auto exstingFragments =
298 module->getAttrOfType<ArrayAttr>(emit::getFragmentsAttrName()))
299 for (auto fragment : exstingFragments.getAsRange<FlatSymbolRefAttr>())
300 fragments.insert(fragment);
301 for (auto callee : dpiCallees) {
302 auto attr = symbolToFragment.at(callee);
303 fragments.insert(FlatSymbolRefAttr::get(attr));
304 }
305 if (!fragments.empty())
306 module->setAttr(
307 emit::getFragmentsAttrName(),
308 ArrayAttr::get(module.getContext(), fragments.takeVector()));
309}
310
311namespace {
312struct SimToSVPass : public circt::impl::LowerSimToSVBase<SimToSVPass> {
313 void runOnOperation() override {
314 auto circuit = getOperation();
315 MLIRContext *context = &getContext();
316 LowerDPIFunc lowerDPIFunc(circuit);
317
318 // Lower DPI functions.
319 for (auto func :
320 llvm::make_early_inc_range(circuit.getOps<sim::DPIFuncOp>()))
321 lowerDPIFunc.lower(func);
322
323 std::atomic<bool> usedSynthesisMacro = false;
324 auto lowerModule = [&](hw::HWModuleOp module) {
325 SimConversionState state;
326 ConversionTarget target(*context);
327 target.addIllegalDialect<SimDialect>();
328 target.addLegalDialect<sv::SVDialect>();
329 target.addLegalDialect<hw::HWDialect>();
330 target.addLegalDialect<seq::SeqDialect>();
331 target.addLegalDialect<comb::CombDialect>();
332
333 RewritePatternSet patterns(context);
334 patterns.add<PlusArgsTestLowering>(context, state);
335 patterns.add<PlusArgsValueLowering>(context, state);
337 state);
339 state);
340 patterns.add<DPICallLowering>(context, state);
341 auto result = applyPartialConversion(module, target, std::move(patterns));
342
343 if (failed(result))
344 return result;
345
346 // Set the emit fragment.
347 lowerDPIFunc.addFragments(module, state.dpiCallees.takeVector());
348
349 if (state.usedSynthesisMacro)
350 usedSynthesisMacro = true;
351 return result;
352 };
353
354 if (failed(mlir::failableParallelForEach(
355 context, circuit.getOps<hw::HWModuleOp>(), lowerModule)))
356 return signalPassFailure();
357
358 if (usedSynthesisMacro) {
359 Operation *op = circuit.lookupSymbol("SYNTHESIS");
360 if (op) {
361 if (!isa<sv::MacroDeclOp>(op)) {
362 op->emitOpError("should be a macro declaration");
363 return signalPassFailure();
364 }
365 } else {
366 auto builder = ImplicitLocOpBuilder::atBlockBegin(
367 UnknownLoc::get(context), circuit.getBody());
368 builder.create<sv::MacroDeclOp>("SYNTHESIS");
369 }
370 }
371 }
372};
373} // anonymous namespace
374
375std::unique_ptr<Pass> circt::createLowerSimToSVPass() {
376 return std::make_unique<SimToSVPass>();
377}
LogicalResult matchAndRewrite(DPICallOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const final
Definition SimToSV.cpp:178
LogicalResult matchAndRewrite(PlusArgsTestOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const final
Definition SimToSV.cpp:64
LogicalResult matchAndRewrite(PlusArgsValueOp op, OpAdaptor adaptor, ConversionPatternRewriter &rewriter) const final
Definition SimToSV.cpp:89
LogicalResult matchAndRewrite(FromOp op, typename FromOp::Adaptor adaptor, ConversionPatternRewriter &rewriter) const final
Definition SimToSV.cpp:150
A namespace that is used to store existing names and generate new names in some scope within the IR.
Definition Namespace.h:30
void add(mlir::ModuleOp module)
Definition Namespace.h:48
StringRef newName(const Twine &name)
Return a unique name, derived from the input name, and add the new name to the internal namespace.
Definition Namespace.h:87
create(data_type, value)
Definition hw.py:433
create(dest, src)
Definition sv.py:98
create(value)
Definition sv.py:106
Definition sv.py:68
void setSVAttributes(mlir::Operation *op, mlir::ArrayAttr attrs)
Set the SV attributes of an operation.
The InstanceGraph op interface, see InstanceGraphInterface.td for more details.
std::unique_ptr< mlir::Pass > createLowerSimToSVPass()
Definition SimToSV.cpp:375
circt::Namespace nameSpace
Definition SimToSV.cpp:245
void lower(sim::DPIFuncOp func)
Definition SimToSV.cpp:252
void addFragments(hw::HWModuleOp module, ArrayRef< StringAttr > dpiCallees) const
Definition SimToSV.cpp:293
llvm::DenseMap< StringAttr, StringAttr > symbolToFragment
Definition SimToSV.cpp:244
LowerDPIFunc(mlir::ModuleOp module)
Definition SimToSV.cpp:246