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FIRRTLInstanceInfo.cpp
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1//===- FIRRTLInstanceInfo.cpp - Instance info analysis ----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file defines the InstanceInfo analysis. This is an analysis that
10// depends on the InstanceGraph analysis, but provides additional information
11// about FIRRTL operations. This is useful if you find yourself needing to
12// selectively iterate over parts of the design.
13//
14//===----------------------------------------------------------------------===//
15
20#include "circt/Support/Debug.h"
22#include "llvm/ADT/PostOrderIterator.h"
23#include "llvm/Support/Debug.h"
24
25#ifndef NDEBUG
26#include "llvm/ADT/DepthFirstIterator.h"
27#endif
28
29#define DEBUG_TYPE "firrtl-analysis-instanceinfo"
30
31using namespace circt;
32using namespace firrtl;
33
35
36bool InstanceInfo::LatticeValue::isConstant() const { return kind == Constant; }
37
38bool InstanceInfo::LatticeValue::isMixed() const { return kind == Mixed; }
39
42 return value;
43}
44
46 kind = Constant;
47 value = constant;
48}
49
51
53 if (kind > that.kind)
54 return;
55
56 if (kind < that.kind) {
57 kind = that.kind;
58 value = that.value;
59 return;
60 }
61
62 if (isConstant() && getConstant() != that.value)
63 kind = Mixed;
64}
65
67 LatticeValue latticeValue;
68 latticeValue.markConstant(value);
69 mergeIn(latticeValue);
70}
71
73 if (isUnknown() || isMixed())
74 return *this;
75
76 auto invert = LatticeValue();
77 invert.markConstant(!getConstant());
78 return invert;
79}
80
81InstanceInfo::InstanceInfo(Operation *op, mlir::AnalysisManager &am) {
82 auto &iGraph = am.getAnalysis<InstanceGraph>();
83
84 // Setup circuit attributes based on presence of annotations.
85 circuitAttributes.effectiveDut = iGraph.getTopLevelNode()->getModule();
86 for (auto *node : iGraph) {
87 auto moduleOp = node->getModule();
88 AnnotationSet annotations(moduleOp);
89 if (annotations.hasAnnotation(dutAnnoClass)) {
90 circuitAttributes.dut = moduleOp;
92 }
93 }
94
95 // Setup boundary conditions for any modules without users.
96 for (auto *node : iGraph) {
97 if (!node->noUses())
98 continue;
99
100 auto moduleOp = node->getModule();
101 ModuleAttributes &attributes = moduleAttributes[moduleOp];
102
103 attributes.underDut.mergeIn(isDut(moduleOp));
104 attributes.inDesign.mergeIn(isDut(moduleOp));
105 attributes.inEffectiveDesign.mergeIn(isEffectiveDut(moduleOp) || !hasDut());
106 attributes.underLayer.mergeIn(false);
107 }
108
109 // Visit modules in reverse post-order (visit parents before children) to
110 // merge parent attributes and per-instance attributes into children.
111 DenseSet<InstanceGraphNode *> visited;
112 for (auto *root : iGraph) {
113 for (auto *modIt : llvm::inverse_post_order_ext(root, visited)) {
114 visited.insert(modIt);
115 auto moduleOp = modIt->getModule();
116 ModuleAttributes &attributes = moduleAttributes[moduleOp];
117
118 AnnotationSet annotations(moduleOp);
119 auto isDut = annotations.hasAnnotation(dutAnnoClass);
120 auto isGCCompanion = annotations.hasAnnotation(companionAnnoClass);
121
122 if (isDut) {
123 attributes.underDut.markConstant(true);
124 attributes.inDesign.markConstant(true);
125 attributes.inEffectiveDesign.markConstant(true);
126 }
127
128 if (isGCCompanion) {
129 attributes.inDesign.mergeIn(false);
130 attributes.inEffectiveDesign.mergeIn(false);
131 attributes.underLayer.mergeIn(true);
132 }
133
134 // Merge in values based on the instantiations of this module.
135 for (auto *useIt : modIt->uses()) {
136 auto parentOp = useIt->getParent()->getModule();
137 auto parentAttrs = moduleAttributes.find(parentOp)->getSecond();
138
139 // Update underDut.
140 if (!isDut)
141 attributes.underDut.mergeIn(parentAttrs.underDut);
142
143 // Update underLayer.
144 bool underLayer = false;
145 if (auto instanceOp = useIt->getInstance<InstanceOp>()) {
146 if (instanceOp.getLowerToBind() || instanceOp.getDoNotPrint() ||
147 instanceOp->getParentOfType<LayerBlockOp>() ||
148 instanceOp->getParentOfType<sv::IfDefOp>())
149 underLayer = true;
150 }
151
152 if (!isGCCompanion) {
153 if (underLayer)
154 attributes.underLayer.mergeIn(true);
155 else
156 attributes.underLayer.mergeIn(parentAttrs.underLayer);
157 }
158
159 // Update inDesign and inEffectiveDesign.
160 if (underLayer) {
161 attributes.inDesign.mergeIn(false);
162 attributes.inEffectiveDesign.mergeIn(false);
163 } else if (!isDut && !isGCCompanion) {
164 attributes.inDesign.mergeIn(parentAttrs.inDesign);
165 attributes.inEffectiveDesign.mergeIn(parentAttrs.inEffectiveDesign);
166 }
167 }
168 }
169 }
170
171 LLVM_DEBUG({
172 mlir::OpPrintingFlags flags;
173 flags.skipRegions();
174 debugHeader("FIRRTL InstanceInfo Analysis")
175 << "\n"
176 << llvm::indent(2) << "circuit attributes:\n"
177 << llvm::indent(4) << "hasDut: " << (hasDut() ? "true" : "false")
178 << "\n"
179 << llvm::indent(4) << "dut: ";
180 if (auto dut = circuitAttributes.dut)
181 dut->print(llvm::dbgs(), flags);
182 else
183 llvm::dbgs() << "null";
184 llvm::dbgs() << "\n" << llvm::indent(4) << "effectiveDut: ";
185 circuitAttributes.effectiveDut->print(llvm::dbgs(), flags);
186 llvm::dbgs() << "\n" << llvm::indent(2) << "module attributes:\n";
187 visited.clear();
188 for (auto *root : iGraph) {
189 for (auto *modIt : llvm::inverse_post_order_ext(root, visited)) {
190 visited.insert(modIt);
191 auto moduleOp = modIt->getModule();
192 auto attributes = moduleAttributes[moduleOp];
193 llvm::dbgs().indent(4)
194 << "- module: " << moduleOp.getModuleName() << "\n"
195 << llvm::indent(6)
196 << "isDut: " << (isDut(moduleOp) ? "true" : "false") << "\n"
197 << llvm::indent(6) << "isEffectiveDue: "
198 << (isEffectiveDut(moduleOp) ? "true" : "false") << "\n"
199 << llvm::indent(6) << "underDut: " << attributes.underDut << "\n"
200 << llvm::indent(6) << "underLayer: " << attributes.underLayer
201 << "\n"
202 << llvm::indent(6) << "inDesign: " << attributes.inDesign << "\n"
203 << llvm::indent(6)
204 << "inEffectiveDesign: " << attributes.inEffectiveDesign << "\n";
205 }
206 }
207 });
208}
209
211InstanceInfo::getModuleAttributes(igraph::ModuleOpInterface op) {
212 return moduleAttributes.find(op)->getSecond();
213}
214
216
217bool InstanceInfo::isDut(igraph::ModuleOpInterface op) {
218 if (hasDut())
219 return op == circuitAttributes.dut;
220 return false;
221}
222
223bool InstanceInfo::isEffectiveDut(igraph::ModuleOpInterface op) {
224 if (hasDut())
225 return isDut(op);
226 return op == circuitAttributes.effectiveDut;
227}
228
229igraph::ModuleOpInterface InstanceInfo::getDut() {
230 return circuitAttributes.dut;
231}
232
233igraph::ModuleOpInterface InstanceInfo::getEffectiveDut() {
235}
236
237bool InstanceInfo::anyInstanceUnderDut(igraph::ModuleOpInterface op) {
238 auto underDut = getModuleAttributes(op).underDut;
239 return underDut.isMixed() || allInstancesUnderDut(op);
240}
241
242bool InstanceInfo::allInstancesUnderDut(igraph::ModuleOpInterface op) {
243 auto underDut = getModuleAttributes(op).underDut;
244 return underDut.isConstant() && underDut.getConstant();
245}
246
247bool InstanceInfo::anyInstanceUnderEffectiveDut(igraph::ModuleOpInterface op) {
248 return !hasDut() || anyInstanceUnderDut(op);
249}
250
251bool InstanceInfo::allInstancesUnderEffectiveDut(igraph::ModuleOpInterface op) {
252 return !hasDut() || allInstancesUnderDut(op);
253}
254
255bool InstanceInfo::anyInstanceUnderLayer(igraph::ModuleOpInterface op) {
256 auto underLayer = getModuleAttributes(op).underLayer;
257 return underLayer.isMixed() || allInstancesUnderLayer(op);
258}
259
260bool InstanceInfo::allInstancesUnderLayer(igraph::ModuleOpInterface op) {
261 auto underLayer = getModuleAttributes(op).underLayer;
262 return underLayer.isConstant() && underLayer.getConstant();
263}
264
265bool InstanceInfo::anyInstanceInDesign(igraph::ModuleOpInterface op) {
266 auto inDesign = getModuleAttributes(op).inDesign;
267 return inDesign.isMixed() || allInstancesInDesign(op);
268}
269
270bool InstanceInfo::allInstancesInDesign(igraph::ModuleOpInterface op) {
271 auto inDesign = getModuleAttributes(op).inDesign;
272 return inDesign.isConstant() && inDesign.getConstant();
273}
274
275bool InstanceInfo::anyInstanceInEffectiveDesign(igraph::ModuleOpInterface op) {
276 auto inEffectiveDesign = getModuleAttributes(op).inEffectiveDesign;
277 return inEffectiveDesign.isMixed() || allInstancesInEffectiveDesign(op);
278}
279
280bool InstanceInfo::allInstancesInEffectiveDesign(igraph::ModuleOpInterface op) {
281 auto inEffectiveDesign = getModuleAttributes(op).inEffectiveDesign;
282 return inEffectiveDesign.isConstant() && inEffectiveDesign.getConstant();
283}
assert(baseType &&"element must be base type")
static std::optional< APSInt > getConstant(Attribute operand)
Determine the value of a constant operand for the sake of constant folding.
This class provides a read-only projection over the MLIR attributes that represent a set of annotatio...
bool hasAnnotation(StringRef className) const
Return true if we have an annotation with the specified class name.
This graph tracks modules and where they are instantiated.
A lattice value to record the value of a property.
LatticeValue operator!()
Invert the lattice value.
void mergeIn(LatticeValue that)
Merge attributes from another LatticeValue into this one.
bool value
The value of the property if kind is Constant.
Kind kind
Whether or not the property holds.
bool getConstant() const
Return the value. This should only be used if the kind is Constant.
void markMixed()
Set this LatticeValue to mixed.
bool isConstant() const
Return true if the kind is Constant.
bool isUnknown() const
Return true if the kind is Unknown.
void markConstant(bool constant)
Set this LatticeValue to a constant.
bool isMixed() const
Return true if the kind is Mixed.
bool allInstancesUnderLayer(igraph::ModuleOpInterface op)
Return true if all instances of this module are under (or transitively under) layer blocks.
igraph::ModuleOpInterface getDut()
Return the design-under-test if one is defined for the circuit, otherwise return null.
bool isEffectiveDut(igraph::ModuleOpInterface op)
Return true if this module is the design-under-test and the circuit has a design-under-test.
CircuitAttributes circuitAttributes
Stores circuit-level attributes.
bool hasDut()
Return true if this circuit has a design-under-test.
bool allInstancesInEffectiveDesign(igraph::ModuleOpInterface op)
Return true if all instances of this module are within (or transitively withiin) the effective design...
bool isDut(igraph::ModuleOpInterface op)
Return true if this module is the design-under-test.
bool anyInstanceUnderDut(igraph::ModuleOpInterface op)
Return true if at least one instance of this module is under (or transitively under) the design-under...
bool anyInstanceUnderEffectiveDut(igraph::ModuleOpInterface op)
Return true if at least one instance is under (or transitively under) the effective design-under-test...
bool allInstancesUnderEffectiveDut(igraph::ModuleOpInterface op)
Return true if all instances are under (or transitively under) the effective design-under-test.
DenseMap< Operation *, ModuleAttributes > moduleAttributes
Internal mapping of operations to module attributes.
igraph::ModuleOpInterface getEffectiveDut()
Return the "effective" design-under-test.
InstanceInfo(Operation *op, mlir::AnalysisManager &am)
bool allInstancesUnderDut(igraph::ModuleOpInterface op)
Return true if all instances of this module are under (or transitively under) the design-under-test.
const ModuleAttributes & getModuleAttributes(igraph::ModuleOpInterface op)
Return the module attributes associated with a module.
bool anyInstanceInEffectiveDesign(igraph::ModuleOpInterface op)
Return true if any instance of this module is within (or transitively within) the effective design.
bool allInstancesInDesign(igraph::ModuleOpInterface op)
Return true if all instances of this module are within (or transitively withiin) the design.
bool anyInstanceUnderLayer(igraph::ModuleOpInterface op)
Return true if at least one instance of this module is under (or transitively under) a layer.
bool anyInstanceInDesign(igraph::ModuleOpInterface op)
Return true if any instance of this module is within (or transitively within) the design.
bool isConstant(Operation *op)
Return true if the specified operation has a constant value.
constexpr const char * dutAnnoClass
constexpr const char * companionAnnoClass
The InstanceGraph op interface, see InstanceGraphInterface.td for more details.
llvm::raw_ostream & debugHeader(llvm::StringRef str, int width=80)
Write a "header"-like string to the debug stream with a certain width.
Definition Debug.cpp:18
igraph::ModuleOpInterface dut
The design-under-test if one is defined.
igraph::ModuleOpInterface effectiveDut
The design-under-test if one is defined or the top module.
InstanceInfo::LatticeValue inDesign
Indicates if this module is instantiated in the design.
InstanceInfo::LatticeValue underDut
Indicates if this module is instantiated under the design-under-test.
InstanceInfo::LatticeValue inEffectiveDesign
Indicates if this modules is instantiated in the effective design.
InstanceInfo::LatticeValue underLayer
Indicates if this module is instantiated under a layer.