10#ifndef CONVERSION_SEQTOSV_FIRREGLOWERING_H
11#define CONVERSION_SEQTOSV_FIRREGLOWERING_H
21#include "mlir/IR/Attributes.h"
22#include "llvm/ADT/SmallPtrSet.h"
44 llvm::DenseMap<Operation *, llvm::SmallDenseSet<Operation *>>
reachableMuxes;
45 llvm::SmallPtrSet<Operation *, 16>
visited;
53 llvm::filter_iterator<Operation::user_iterator,
54 std::function<bool(
const Operation *)>>;
81 using PathTable = DenseMap<seq::FirRegOp, hw::HierPathOp>;
114 return cast<sv::MacroIdentAttr>(
data.getPointer());
116 llvm::PointerIntPair<Attribute, 1, Kind>
data;
136 Value rand,
unsigned &pos);
138 void createTree(OpBuilder &builder, Value reg, Value term, Value next);
139 std::optional<std::tuple<Value, Value, Value>>
143 void addToAlwaysBlock(Block *block, sv::EventControl clockEdge, Value clock,
144 const std::function<
void(OpBuilder &)> &body,
145 sv::ResetType resetStyle = {},
146 sv::EventControl resetEdge = {}, Value reset = {},
147 const std::function<void(OpBuilder &)> &resetBody = {});
150 const std::function<
void()> &trueSide,
151 const std::function<
void()> &falseSide);
160 OpBuilder builder(module.getBody());
163 constant->setLoc(builder.getFusedLoc({constant->getLoc(), loc}));
176 sv::ResetType, sv::EventControl, Value>;
Lower FirRegOp to sv.reg and sv.always.
std::unique_ptr< ReachableMuxes > reachableMuxes
bool needsRegRandomization() const
void initialize(OpBuilder &builder, RegLowerInfo reg, ArrayRef< Value > rands)
llvm::SmallDenseMap< std::pair< Value, unsigned >, Value > arrayIndexCache
void createAsyncResetInitialization(ImplicitLocOpBuilder &builder)
llvm::SmallDenseMap< IfKeyType, sv::IfOp > ifCache
static PathTable createPaths(mlir::ModuleOp top)
When a register is buried under an ifdef op, the initialization code at the footer of the HW module w...
DenseMap< seq::FirRegOp, hw::HierPathOp > PathTable
A map sending registers to their paths.
void createInitialBlock()
void addToIfBlock(OpBuilder &builder, Value cond, const std::function< void()> &trueSide, const std::function< void()> &falseSide)
std::optional< std::tuple< Value, Value, Value > > tryRestoringSubaccess(OpBuilder &builder, Value reg, Value term, hw::ArrayCreateOp nextRegValue)
llvm::SmallDenseMap< APInt, hw::ConstantOp > constantCache
void createRandomInitialization(ImplicitLocOpBuilder &builder)
void lowerUnderIfDef(sv::IfDefOp ifDefOp)
void lowerInBlock(Block *block)
void buildRegConditions(OpBuilder &b, sv::RegOp reg)
Recreate the ifdefs under which reg was defined.
const PathTable & pathTable
void lowerReg(seq::FirRegOp reg)
std::pair< Block *, Value > IfKeyType
SmallVector< Value > createRandomizationVector(OpBuilder &builder, Location loc)
std::vector< RegCondition > conditions
The ambient ifdef conditions we have encountered while lowering.
void createTree(OpBuilder &builder, Value reg, Value term, Value next)
void createPresetInitialization(ImplicitLocOpBuilder &builder)
unsigned numSubaccessRestored
hw::ConstantOp getOrCreateConstant(Location loc, const APInt &value)
void addToAlwaysBlock(Block *block, sv::EventControl clockEdge, Value clock, const std::function< void(OpBuilder &)> &body, sv::ResetType resetStyle={}, sv::EventControl resetEdge={}, Value reset={}, const std::function< void(OpBuilder &)> &resetBody={})
SmallVector< RegLowerInfo > randomInitRegs
A list of registers discovered, bucketed by initialization style.
std::tuple< Block *, sv::EventControl, Value, sv::ResetType, sv::EventControl, Value > AlwaysKeyType
llvm::MapVector< Value, SmallVector< RegLowerInfo > > asyncResets
A map from async reset signal to the registers that use it.
void initializeRegisterElements(Location loc, OpBuilder &builder, Value reg, Value rand, unsigned &pos)
DenseMap< sv::RegOp, std::vector< RegCondition > > regConditionTable
A map from RegOps to the ifdef conditions under which they are defined.
TypeConverter & typeConverter
hw::HWModuleOp bool disableRegRandomization
bool emitSeparateAlwaysBlocks
SmallVector< RegLowerInfo > presetInitRegs
llvm::SmallDenseMap< AlwaysKeyType, std::pair< sv::AlwaysOp, sv::IfOp > > alwaysBlocks
void buildReachabilityFrom(Operation *startNode)
llvm::SmallPtrSet< Operation *, 16 > visited
HWModuleOp llvm::DenseMap< Operation *, llvm::SmallDenseSet< Operation * > > reachableMuxes
bool isMuxReachableFrom(seq::FirRegOp regOp, comb::MuxOp muxOp)
ReachableMuxes(HWModuleOp m)
The InstanceGraph op interface, see InstanceGraphInterface.td for more details.
The conditions under which a register is defined.
sv::MacroIdentAttr getMacro() const
RegCondition(Kind kind, sv::MacroIdentAttr macro)
llvm::PointerIntPair< Attribute, 1, Kind > data
@ IfDefThen
The register is under an ifdef "then" branch.
@ IfDefElse
The register is under an ifdef "else" branch.
llvm::filter_iterator< Operation::user_iterator, std::function< bool(const Operation *)> > ValidUsersIterator
static std::function< bool(const Operation *op)> opAllowsReachability
OpUserInfo(Operation *op)
ValidUsersIterator userIter
bool getAndSetUnvisited()
ValidUsersIterator userEnd