CIRCT  18.0.0git
FirRegLowering.h
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1 //===- FirRegLowering.h - FirReg lowering utilities ===========--*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 // NOLINTNEXTLINE(llvm-header-guard)
10 #ifndef CONVERSION_SEQTOSV_FIRREGLOWERING_H
11 #define CONVERSION_SEQTOSV_FIRREGLOWERING_H
12 
13 #include "circt/Dialect/HW/HWOps.h"
14 #include "circt/Dialect/SV/SVOps.h"
16 #include "circt/Support/LLVM.h"
18 #include "circt/Support/SymCache.h"
19 
20 namespace circt {
21 /// Lower FirRegOp to `sv.reg` and `sv.always`.
23 public:
25  bool disableRegRandomization = false,
26  bool emitSeparateAlwaysBlocks = false)
30 
31  void lower();
32 
33  unsigned numSubaccessRestored = 0;
34 
35 private:
36  struct RegLowerInfo {
38  IntegerAttr preset;
41  int64_t randStart;
42  size_t width;
43  };
44 
45  RegLowerInfo lower(seq::FirRegOp reg);
46 
47  void initialize(OpBuilder &builder, RegLowerInfo reg, ArrayRef<Value> rands);
48  void initializeRegisterElements(Location loc, OpBuilder &builder, Value reg,
49  Value rand, unsigned &pos);
50 
51  void createTree(OpBuilder &builder, Value reg, Value term, Value next);
52  std::optional<std::tuple<Value, Value, Value>>
53  tryRestoringSubaccess(OpBuilder &builder, Value reg, Value term,
54  hw::ArrayCreateOp nextRegValue);
55 
56  void addToAlwaysBlock(Block *block, sv::EventControl clockEdge, Value clock,
57  const std::function<void(OpBuilder &)> &body,
58  ResetType resetStyle = {},
59  sv::EventControl resetEdge = {}, Value reset = {},
60  const std::function<void(OpBuilder &)> &resetBody = {});
61 
62  void addToIfBlock(OpBuilder &builder, Value cond,
63  const std::function<void()> &trueSide,
64  const std::function<void()> &falseSide);
65 
66  hw::ConstantOp getOrCreateConstant(Location loc, const APInt &value) {
67  OpBuilder builder(module.getBody());
68  auto &constant = constantCache[value];
69  if (constant) {
70  constant->setLoc(builder.getFusedLoc({constant->getLoc(), loc}));
71  return constant;
72  }
73 
74  constant = builder.create<hw::ConstantOp>(loc, value);
75  return constant;
76  }
77 
78  using AlwaysKeyType = std::tuple<Block *, sv::EventControl, Value, ResetType,
79  sv::EventControl, Value>;
82 
83  using IfKeyType = std::pair<Block *, Value>;
85 
88 
89  TypeConverter &typeConverter;
91 
94 };
95 } // namespace circt
96 
97 #endif // CONVERSION_SEQTOSV_FIRREGLOWERING_H
lowerAnnotationsNoRefTypePorts FirtoolPreserveValuesMode value
Definition: Firtool.cpp:95
Builder builder
Lower FirRegOp to sv.reg and sv.always.
void initialize(OpBuilder &builder, RegLowerInfo reg, ArrayRef< Value > rands)
llvm::SmallDenseMap< std::pair< Value, unsigned >, Value > arrayIndexCache
llvm::SmallDenseMap< IfKeyType, sv::IfOp > ifCache
hw::HWModuleOp module
RegLowerInfo lower(seq::FirRegOp reg)
void addToIfBlock(OpBuilder &builder, Value cond, const std::function< void()> &trueSide, const std::function< void()> &falseSide)
std::optional< std::tuple< Value, Value, Value > > tryRestoringSubaccess(OpBuilder &builder, Value reg, Value term, hw::ArrayCreateOp nextRegValue)
llvm::SmallDenseMap< APInt, hw::ConstantOp > constantCache
std::tuple< Block *, sv::EventControl, Value, ResetType, sv::EventControl, Value > AlwaysKeyType
std::pair< Block *, Value > IfKeyType
void createTree(OpBuilder &builder, Value reg, Value term, Value next)
hw::ConstantOp getOrCreateConstant(Location loc, const APInt &value)
void initializeRegisterElements(Location loc, OpBuilder &builder, Value reg, Value rand, unsigned &pos)
void addToAlwaysBlock(Block *block, sv::EventControl clockEdge, Value clock, const std::function< void(OpBuilder &)> &body, ResetType resetStyle={}, sv::EventControl resetEdge={}, Value reset={}, const std::function< void(OpBuilder &)> &resetBody={})
TypeConverter & typeConverter
FirRegLowering(TypeConverter &typeConverter, hw::HWModuleOp module, bool disableRegRandomization=false, bool emitSeparateAlwaysBlocks=false)
llvm::SmallDenseMap< AlwaysKeyType, std::pair< sv::AlwaysOp, sv::IfOp > > alwaysBlocks
Definition: sv.py:68
This file defines an intermediate representation for circuits acting as an abstraction for constraint...
Definition: DebugAnalysis.h:21
def reg(value, clock, reset=None, reset_value=None, name=None, sym_name=None)
Definition: seq.py:20