10 #ifndef CONVERSION_SEQTOSV_FIRREGLOWERING_H
11 #define CONVERSION_SEQTOSV_FIRREGLOWERING_H
49 Value rand,
unsigned &pos);
52 std::optional<std::tuple<Value, Value, Value>>
57 const std::function<
void(OpBuilder &)> &body,
58 ResetType resetStyle = {},
59 sv::EventControl resetEdge = {}, Value reset = {},
60 const std::function<void(OpBuilder &)> &resetBody = {});
63 const std::function<
void()> &trueSide,
64 const std::function<
void()> &falseSide);
70 constant->setLoc(
builder.getFusedLoc({constant->getLoc(), loc}));
78 using AlwaysKeyType = std::tuple<Block *, sv::EventControl, Value, ResetType,
79 sv::EventControl, Value>;
Lower FirRegOp to sv.reg and sv.always.
void initialize(OpBuilder &builder, RegLowerInfo reg, ArrayRef< Value > rands)
llvm::SmallDenseMap< std::pair< Value, unsigned >, Value > arrayIndexCache
llvm::SmallDenseMap< IfKeyType, sv::IfOp > ifCache
RegLowerInfo lower(seq::FirRegOp reg)
void addToIfBlock(OpBuilder &builder, Value cond, const std::function< void()> &trueSide, const std::function< void()> &falseSide)
std::optional< std::tuple< Value, Value, Value > > tryRestoringSubaccess(OpBuilder &builder, Value reg, Value term, hw::ArrayCreateOp nextRegValue)
llvm::SmallDenseMap< APInt, hw::ConstantOp > constantCache
std::tuple< Block *, sv::EventControl, Value, ResetType, sv::EventControl, Value > AlwaysKeyType
std::pair< Block *, Value > IfKeyType
bool disableRegRandomization
void createTree(OpBuilder &builder, Value reg, Value term, Value next)
unsigned numSubaccessRestored
hw::ConstantOp getOrCreateConstant(Location loc, const APInt &value)
void initializeRegisterElements(Location loc, OpBuilder &builder, Value reg, Value rand, unsigned &pos)
void addToAlwaysBlock(Block *block, sv::EventControl clockEdge, Value clock, const std::function< void(OpBuilder &)> &body, ResetType resetStyle={}, sv::EventControl resetEdge={}, Value reset={}, const std::function< void(OpBuilder &)> &resetBody={})
TypeConverter & typeConverter
FirRegLowering(TypeConverter &typeConverter, hw::HWModuleOp module, bool disableRegRandomization=false, bool emitSeparateAlwaysBlocks=false)
bool emitSeparateAlwaysBlocks
llvm::SmallDenseMap< AlwaysKeyType, std::pair< sv::AlwaysOp, sv::IfOp > > alwaysBlocks
This file defines an intermediate representation for circuits acting as an abstraction for constraint...
def reg(value, clock, reset=None, reset_value=None, name=None, sym_name=None)