73 operands = [input, clk]
76 results.append(data_type)
77 operand_segment_sizes = [1, 1]
78 if isinstance(op, CompRegOp):
79 if clockEnable
is not None:
80 raise Exception(
"Clock enable not supported on compreg")
81 elif isinstance(op, CompRegClockEnabledOp):
82 if clockEnable
is None:
83 raise Exception(
"Clock enable required on compreg.ce")
84 operands.append(clockEnable)
85 operand_segment_sizes.append(1)
87 assert False,
"Class not recognized"
88 if reset
is not None and reset_value
is not None:
89 operands.append(reset)
90 operands.append(reset_value)
91 operand_segment_sizes += [1, 1]
93 operand_segment_sizes += [0, 0]
94 operands += [
None,
None]
96 if power_on_value
is not None:
97 if isinstance(power_on_value.type, seq.ImmutableType):
100 if power_on_value.owner
is None:
101 assert False,
"Initial value must not be port"
103 init = InitialOp([seq.ImmutableType.get(power_on_value.type)], [])
104 init.body.blocks.append()
105 with InsertionPoint(init.body.blocks[0]):
106 cloned_constant = power_on_value.owner.clone()
107 seq.YieldOp(cloned_constant)
109 power_on_value = init.results[0]
111 assert False,
"Non-constant initial value not supported"
112 operands.append(power_on_value)
113 operand_segment_sizes.append(1)
115 operands.append(
None)
116 operand_segment_sizes.append(0)
118 attributes[
"name"] = StringAttr.get(
"")
120 attributes[
"name"] = StringAttr.get(name)
121 if sym_name
is not None:
122 attributes[
"inner_sym"] = hw.InnerSymAttr.get(StringAttr.get(sym_name))
124 op._ODS_OPERAND_SEGMENTS = operand_segment_sizes
129 attributes=attributes,