7 from ..dialects._ods_common
import _cext
as _ods_cext
8 from ..ir
import IntegerType, OpView, StringAttr
9 from ..support
import BackedgeBuilder, NamedValueOpView
10 from ._seq_ops_gen
import *
11 from ._seq_ops_gen
import _Dialect
12 from .seq
import CompRegOp
20 def reg(value, clock, reset=None, reset_value=None, name=None, sym_name=None):
22 from ..ir
import IntegerAttr
23 value_type = value.type
26 zero = IntegerAttr.get(value_type, 0)
28 return CompRegOp.create(value_type,
32 reset_value=reset_value,
34 sym_name=sym_name).data.value
36 return CompRegOp.create(value_type,
40 sym_name=sym_name).data.value
49 if arg_name ==
"input":
50 operand_type = data_type
52 operand_type = IntegerType.get_signless(1)
53 return BackedgeBuilder.create(operand_type, arg_name, self)
71 operands = [input, clk]
74 results.append(data_type)
75 operand_segment_sizes = [1, 1]
76 if isinstance(self, CompRegOp):
77 if clockEnable
is not None:
78 raise Exception(
"Clock enable not supported on compreg")
79 elif isinstance(self, CompRegClockEnabledOp):
80 if clockEnable
is None:
81 raise Exception(
"Clock enable required on compreg.ce")
82 operands.append(clockEnable)
83 operand_segment_sizes.append(1)
85 assert False,
"Class not recognized"
86 if reset
is not None and reset_value
is not None:
87 operands.append(reset)
88 operands.append(reset_value)
89 operand_segment_sizes += [1, 1]
91 operand_segment_sizes += [0, 0]
92 operands += [
None,
None]
94 if power_on_value
is not None:
95 operands.append(power_on_value)
96 operand_segment_sizes.append(1)
99 operand_segment_sizes.append(0)
101 attributes[
"name"] = StringAttr.get(
"")
103 attributes[
"name"] = StringAttr.get(name)
104 if sym_name
is not None:
105 attributes[
"inner_sym"] = hw.InnerSymAttr.get(StringAttr.get(sym_name))
112 attributes=attributes,
124 return [
"input",
"clk"]
127 @_ods_cext.register_operation(_Dialect, replace=True)
142 reset_value=reset_value,
145 needs_result_type=
True)
151 return [
"input",
"clk",
"clockEnable"]
154 @_ods_cext.register_operation(_Dialect, replace=True)
169 reset_value=reset_value,
172 needs_result_type=
True)
def create(cls, result_type, reset=None, reset_value=None, name=None, sym_name=None, **kwargs)
def create_initial_value(self, index, data_type, arg_name)
def __init__(self, data_type, input, clk, clockEnable=None, *reset=None, reset_value=None, power_on_value=None, name=None, sym_name=None, loc=None, ip=None)
def create(cls, result_type, reset=None, reset_value=None, name=None, sym_name=None, **kwargs)
def reg(value, clock, reset=None, reset_value=None, name=None, sym_name=None)