#include "circt/Dialect/FIRRTL/FIRRTLInstanceGraph.h"#include "circt/Dialect/FIRRTL/FIRRTLOps.h"#include "llvm/ADT/MapVector.h"
Include dependency graph for GatedClockConversion.h:
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Go to the source code of this file.
Classes | |
| struct | circt::firrtl::ClockEdge |
| class | circt::firrtl::GatedClockConversion |
| Sink gated-clock enables into ops across module boundaries. More... | |
| class | circt::firrtl::GatedClockConversion::MatRef |
| A reference to a clock/enable value that can also name values which do not exist yet (a planned port, a planned wire). More... | |
| struct | circt::firrtl::GatedClockConversion::EnableNode |
Enable accumulation DAG node: value(id) = parent == kNoEnable ? term : (value(parent) & term) Nodes are shared by every consumer of a pair, so a cascade of gates emits one and per gate no matter how many roots it feeds. More... | |
| struct | circt::firrtl::GatedClockConversion::ClockPairPlan |
| (baseClk, enable) pair planned for a clock value. More... | |
| struct | circt::firrtl::GatedClockConversion::RootRewrite |
Root rewrite applied by applyPlan(): clock the op by baseClk and sink enableId into it. More... | |
| struct | circt::firrtl::GatedClockConversion::PortPairPlan |
| (baseClock, enable) port pair to append to a module. More... | |
| struct | circt::firrtl::GatedClockConversion::InstanceDrive |
| Caller-side connects driving a planned input port pair. More... | |
| struct | circt::firrtl::GatedClockConversion::WirePairPlan |
Temporary (base clock, enable) carrier wires at the top of mod, standing in for a wire/node alias of a gated clock. More... | |
Namespaces | |
| namespace | circt |
| The InstanceGraph op interface, see InstanceGraphInterface.td for more details. | |
| namespace | circt::firrtl |
Enumerations | |
| enum class | circt::firrtl::EdgeKind { circt::firrtl::Alias , circt::firrtl::Gate , circt::firrtl::InstanceIn , circt::firrtl::InstanceOut } |
