Here is a list of all file members with links to the files they belong to:

- i -

• ifOpLegalityCallback() : AffineToLoopSchedule.cpp
• ignoreOp() : ScheduleLinearPipeline.cpp
• Impl : RpcServer.cpp
• ImplBinOpCellInterface : CalyxOps.cpp
• ImplBinPipeOpCellInterface() : CalyxOps.cpp
• ImplUnaryOpCellInterface : CalyxOps.cpp
• improveNamehint() : HWArithToHW.cpp
• inCycle() : Buffers.cpp
• indentIncrement : ExportChiselInterface.cpp
• INDEX_WIDTH : HandshakeExecutableOps.cpp
• indexToMemAddr() : LowerExtmemToHW.cpp
• inferAndLikeReturnTypes() : LTLOps.cpp
• inferMuxReturnType() : FIRRTLOps.cpp
• inferReturnTypesOfStructExtractOp() : LLHDOps.cpp
• inlineBody() : LowerVectorizations.cpp
• inlineGroups() : RemoveGroups.cpp
• inlineInputOnly() : SVExtractTestCode.cpp
• InnerRefMap : LowerLayers.cpp
• InnerRefToNewNameMap : ModuleInliner.cpp
• InOut : HW.h
• Input : HW.h
• insertBuffer() : Buffers.cpp
• insertFork() : DCMaterialization.cpp
• insertPorts() : FIRRTLOps.cpp
• insertResetMux() : InferResets.cpp
• insertSink() : DCMaterialization.cpp , Materialization.cpp
• instanceNameForLayer() : LowerLayers.cpp
• instantiateCosimEndpointOps() : ESIServices.cpp
• instantiateSystemVerilogMemory() : ESIServices.cpp
• intersection() : EarlyCodeMotionPass.cpp
• invalidateOutputs() : FIRRTLReductions.cpp
• isAggregate() : IMConstProp.cpp
• isAllocOp() : CFToHandshake.cpp
• isalpha : FIRLexer.cpp
• isAlways() : ArcFolds.cpp
• isAncestor() : AdvancedLayerSink.cpp
• isAnnoInteresting() : ExtractInstances.cpp
• isArcBreakingOp() : ConvertToArcs.cpp
• isAssertOp() : SVExtractTestCode.cpp
• isAssumeOp() : SVExtractTestCode.cpp
• isBarrier() : AdvancedLayerSink.cpp
• isBeneficialToConvert() : MuxToControlFlow.cpp
• isBound() : SVExtractTestCode.cpp
• isCombinational() : CalyxOps.cpp
• isConstAllOnes() : SeqOps.cpp
• isConstantLike() : MergeConnections.cpp
• isConstantOne() : FIRRTLFolds.cpp
• isConstantZero() : FIRRTLFolds.cpp
• isConstClock() : SeqOps.cpp
• isConstFieldDriven() : FIRRTLOps.cpp
• isConstTrue() : InferStateProperties.cpp
• isConstZero() : InferStateProperties.cpp , SeqOps.cpp
• isControlCheckTypeAndOperand() : HandshakeOps.cpp
• isControlOp() : Analysis.cpp
• isControlOperand() : Analysis.cpp
• isCoverOp() : SVExtractTestCode.cpp
• isDCType() : KanagawaConvertHandshakeToDC.cpp , DCToHW.cpp
• isDCTyped() : DCMaterialization.cpp
• isDCTypedOp() : KanagawaConvertHandshakeToDC.cpp
• isDeclaration() : IMDeadCodeElim.cpp
• isDefinedByOneConstantOp() : FIRRTLFolds.cpp
• isDeletableDeclaration() : IMDeadCodeElim.cpp
• isDeletableWireOrRegOrNode() : IMConstProp.cpp
• isdigit : FIRLexer.cpp
• isDuplicatableExpression() : ExportVerilog.cpp
• isDuplicatableNullaryExpression() : ExportVerilog.cpp
• isEmittedInline() : FIREmitter.cpp
• isExpressionEmittedInlineIntoProceduralDeclaration() : ExportVerilog.cpp
• isExpressionUnableToInline() : ExportVerilog.cpp
• isFlowSensitiveOp() : FIRRTLReductions.cpp
• isInDesign() : SVExtractTestCode.cpp
• isLayerCompatibleWith() : FIRRTLOps.cpp
• isLayerSetCompatibleWith() : FIRRTLOps.cpp
• isLegalModLikeOp() : FlattenIO.cpp
• isLegalOp() : DCToHW.cpp , HWArithToHW.cpp , SeqToSV.cpp
• isLegalType() : SeqToSV.cpp
• isLimited() : SimplexSchedulers.cpp
• isLiveOut() : CFToHandshake.cpp
• isMemoryOp() : CFToHandshake.cpp
• isMovableDeclaration() : PrepareForEmission.cpp
• isNameBetter() : Naming.cpp
• isNodeLike() : IMConstProp.cpp
• isNotSubAccess() : LowerTypes.cpp
• isOkToBitSelectFrom() : ExportVerilog.cpp
• isOneDimVectorType() : LowerTypes.cpp
• isOutlinable() : Dedup.cpp
• isParamAttrWithParamRef() : HWAttributes.cpp
• IsPassiveBitMask : FIRRTLTypes.cpp
• isPort() : CalyxOps.cpp
• isPortDisabled() : FIRRTLFolds.cpp
• isPortUnused() : FIRRTLFolds.cpp
• isPreservableAggregateType() : LowerTypes.cpp
• isReadyToExecute() : HandshakeExecutableOps.cpp
• isSameIntTypeKind() : FIRRTLOps.cpp
• isSelfDriven() : KanagawaCleanSelfdrivers.cpp
• isSelfWrite() : PrettifyVerilog.cpp
• isSignednessAttr() : HWArithToHW.cpp
• isSignednessType() : HWArithToHW.cpp
• isStaticControl() : CalyxOps.cpp
• isStructType() : FlattenIO.cpp
• isSupportedModuleOp() : ArcOps.cpp
• isTypeAllowedForDPI() : FIRRTLOps.cpp
• isTypeEmpty() : FIRRTLFolds.cpp
• isUInt1() : FIRRTLFolds.cpp
• isUnbufferedChannel() : Buffers.cpp
• isUselessVec() : InferResets.cpp
• isValidDest() : AdvancedLayerSink.cpp
• isValidMemrefType() : CFToHandshake.cpp
• isValidToProceedTraversal() : MuxToControlFlow.cpp
• isValidVerilogCharacter() : SVDialect.cpp
• isValidVerilogCharacterFirst() : SVDialect.cpp
• isVerilogUnaryOperator() : PrettifyVerilog.cpp
• isWireOrReg() : IMConstProp.cpp
• isZeroBitFIRRTLType() : LowerToHW.cpp
• isZeroExtension() : ExportVerilog.cpp