#include "../PassDetail.h"
#include "ExportVerilogInternals.h"
#include "circt/Conversion/ExportVerilog.h"
#include "circt/Dialect/Comb/CombOps.h"
#include "circt/Dialect/Debug/DebugDialect.h"
#include "circt/Dialect/LTL/LTLDialect.h"
#include "circt/Dialect/Verif/VerifDialect.h"
#include "mlir/IR/ImplicitLocOpBuilder.h"
#include "llvm/ADT/DenseSet.h"
#include "llvm/ADT/SmallPtrSet.h"
#include "llvm/ADT/TypeSwitch.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"

Include dependency graph for PrepareForEmission.cpp:

Classes
struct	EmittedExpressionState

class	EmittedExpressionStateManager
	This class handles information about AST structures of each expressions. More...

struct	WireLowering

Macros
#define	DEBUG_TYPE "prepare-for-emission"

Functions
static bool	shouldSpillWire (Operation &op, const LoweringOptions &options)

static StringAttr	getArgName (Operation *op, size_t idx)

static void	spillWiresForInstanceInputs (HWInstanceLike op)

static StringAttr	getResName (Operation *op, size_t idx)

static void	lowerInstanceResults (HWInstanceLike op)

static void	lowerUsersToTemporaryWire (Operation &op, bool emitWireAtBlockBegin=false)
	Emit an explicit wire or logic to assign operation's result. More...

static void	lowerAlwaysInlineOperation (Operation *op, const LoweringOptions &options)

static std::pair< Block *, Block::iterator >	findLogicOpInsertionPoint (Operation *op)

static Value	lowerFullyAssociativeOp (Operation &op, OperandRange operands, SmallVector< Operation * > &newOps)
	Lower a variadic fully-associative operation into an expression tree. More...

static Operation *	rewriteAddWithNegativeConstant (comb::AddOp add, hw::ConstantOp rhsCst)
	Transform "a + -cst" ==> "a - cst" for prettier output. More...

static Operation *	lowerStructExplodeOp (hw::StructExplodeOp op)

static Operation *	findParentInNonProceduralRegion (Operation *op)
	Given an operation in a procedural region, scan up the region tree to find the first operation in a graph region (typically an always or initial op). More...

static bool	rewriteSideEffectingExpr (Operation *op)
	This function is invoked on side effecting Verilog expressions when we're in 'disallowLocalVariables' mode for old Verilog clients. More...

static bool	hoistNonSideEffectExpr (Operation *op)
	This function is called for non-side-effecting Verilog expressions when we're in 'disallowLocalVariables' mode for old Verilog clients. More...

static bool	isMovableDeclaration (Operation *op)
	Check whether an op is a declaration that can be moved. More...

static bool	reuseExistingInOut (Operation *op, const LoweringOptions &options)
	If exactly one use of this op is an assign, replace the other uses with a read from the assigned wire or reg. More...

static void	prettifyAfterLegalization (Block &block, EmittedExpressionStateManager &expressionStateManager)
	After the legalization, we are able to know accurate verilog AST structures. More...

static void	buildWireLowerings (Block &block, SmallVectorImpl< WireLowering > &wireLowerings)
	Determine the insertion location of declaration and assignment ops for `hw::WireOp`s in a block. More...

static void	applyWireLowerings (Block &block, ArrayRef< WireLowering > wireLowerings)
	Materialize the SV wire declaration and assignment operations in the locations previously determined by a call to `buildWireLowerings`. More...

static LogicalResult	legalizeHWModule (Block &block, const LoweringOptions &options)
	For each module we emit, do a prepass over the structure, pre-lowering and otherwise rewriting operations we don't want to emit. More...

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE "prepare-for-emission"

Definition at line 34 of file PrepareForEmission.cpp.

Function Documentation

◆ applyWireLowerings()

static void applyWireLowerings	(	Block &	block,
		ArrayRef< WireLowering >	wireLowerings
	)

static

Materialize the SV wire declaration and assignment operations in the locations previously determined by a call to buildWireLowerings.

This replaces all hw::WireOps with their appropriate SV counterpart.

Definition at line 784 of file PrepareForEmission.cpp.

References builder.

Referenced by legalizeHWModule().

◆ buildWireLowerings()

static void buildWireLowerings	(	Block &	block,
		SmallVectorImpl< WireLowering > &	wireLowerings
	)

static

Determine the insertion location of declaration and assignment ops for hw::WireOps in a block.

This function tries to place the declaration point as late as possible, right before the very first use of the wire. It also tries to place the assign point as early as possible, right after the assigned value becomes available.

Definition at line 755 of file PrepareForEmission.cpp.

Referenced by legalizeHWModule().

◆ findLogicOpInsertionPoint()

static std::pair<Block *, Block::iterator> findLogicOpInsertionPoint ( Operation * op )

static

Definition at line 314 of file PrepareForEmission.cpp.

Referenced by legalizeHWModule().

◆ findParentInNonProceduralRegion()

static Operation* findParentInNonProceduralRegion ( Operation * op )

static

Given an operation in a procedural region, scan up the region tree to find the first operation in a graph region (typically an always or initial op).

By looking for a graph region, we will stop at graph-region #ifdef's that may enclose this operation.

Definition at line 401 of file PrepareForEmission.cpp.

References assert().

Referenced by hoistNonSideEffectExpr(), legalizeHWModule(), and rewriteSideEffectingExpr().

◆ getArgName()

static StringAttr getArgName	(	Operation *	op,
		size_t	idx
	)

static

Definition at line 69 of file PrepareForEmission.cpp.

Referenced by spillWiresForInstanceInputs().

◆ getResName()

static StringAttr getResName	(	Operation *	op,
		size_t	idx
	)

static

Definition at line 106 of file PrepareForEmission.cpp.

Referenced by lowerInstanceResults().

◆ hoistNonSideEffectExpr()

static bool hoistNonSideEffectExpr ( Operation * op )

static

This function is called for non-side-effecting Verilog expressions when we're in 'disallowLocalVariables' mode for old Verilog clients.

It hoists non-constant expressions out to the top level so they don't turn into local variable declarations.

Definition at line 451 of file PrepareForEmission.cpp.

References findParentInNonProceduralRegion(), and circt::ExportVerilog::isExpressionAlwaysInline().

Referenced by legalizeHWModule().

◆ isMovableDeclaration()

static bool isMovableDeclaration ( Operation * op )

static

Check whether an op is a declaration that can be moved.

Definition at line 504 of file PrepareForEmission.cpp.

Referenced by legalizeHWModule().

◆ legalizeHWModule()

static LogicalResult legalizeHWModule	(	Block &	block,
		const LoweringOptions &	options
	)

static

For each module we emit, do a prepass over the structure, pre-lowering and otherwise rewriting operations we don't want to emit.

Definition at line 836 of file PrepareForEmission.cpp.

References circt::sv::addSVAttributes(), applyWireLowerings(), assert(), builder, buildWireLowerings(), circt::LoweringOptions::disallowExpressionInliningInPorts, circt::LoweringOptions::disallowLocalVariables, circt::LoweringOptions::disallowPackedStructAssignments, findLogicOpInsertionPoint(), findParentInNonProceduralRegion(), circt::calyx::direction::get(), hoistNonSideEffectExpr(), circt::ExportVerilog::isConstantExpression(), circt::ExportVerilog::isExpressionAlwaysInline(), isMovableDeclaration(), circt::ExportVerilog::isVerilogExpression(), lowerAlwaysInlineOperation(), lowerFullyAssociativeOp(), lowerInstanceResults(), lowerStructExplodeOp(), lowerUsersToTemporaryWire(), circt::LoweringOptions::mitigateVivadoArrayIndexConstPropBug, reuseExistingInOut(), rewriteAddWithNegativeConstant(), rewriteSideEffectingExpr(), shouldSpillWire(), and spillWiresForInstanceInputs().

Referenced by circt::ExportVerilog::prepareHWModule().

◆ lowerAlwaysInlineOperation()

static void lowerAlwaysInlineOperation	(	Operation *	op,
		const LoweringOptions &	options
	)

static

Definition at line 248 of file PrepareForEmission.cpp.

References assert(), circt::ExportVerilog::isExpressionAlwaysInline(), lowerUsersToTemporaryWire(), and shouldSpillWire().

Referenced by legalizeHWModule(), and reuseExistingInOut().

◆ lowerFullyAssociativeOp()

static Value lowerFullyAssociativeOp	(	Operation &	op,
		OperandRange	operands,
		SmallVector< Operation * > &	newOps
	)

static

Lower a variadic fully-associative operation into an expression tree.

This enables long-line splitting to work with them. NOLINTNEXTLINE(misc-no-recursion)

Definition at line 324 of file PrepareForEmission.cpp.

References assert().

Referenced by legalizeHWModule().

◆ lowerInstanceResults()

static void lowerInstanceResults ( HWInstanceLike op )

static

Definition at line 115 of file PrepareForEmission.cpp.

References builder, Python.support::connect(), getResName(), and circt::ExportVerilog::isZeroBitType().

Referenced by legalizeHWModule().

◆ lowerStructExplodeOp()

static Operation* lowerStructExplodeOp ( hw::StructExplodeOp op )

static

Definition at line 380 of file PrepareForEmission.cpp.

References builder.

Referenced by legalizeHWModule().

◆ lowerUsersToTemporaryWire()

static void lowerUsersToTemporaryWire	(	Operation &	op,
		bool	emitWireAtBlockBegin = `false`
	)

static

Emit an explicit wire or logic to assign operation's result.

This function is used to create a temporary to legalize a verilog expression or to resolve use-before-def in a graph region. If emitWireAtBlockBegin is true, a temporary wire will be created at the beginning of the block. Otherwise, a wire is created just after op's position so that we can inline the assignment into its wire declaration.

Definition at line 168 of file PrepareForEmission.cpp.

References builder, Python.support::connect(), and circt::ExportVerilog::inferStructuralNameForTemporary().

Referenced by legalizeHWModule(), lowerAlwaysInlineOperation(), and prettifyAfterLegalization().

◆ prettifyAfterLegalization()

static void prettifyAfterLegalization	(	Block &	block,
		EmittedExpressionStateManager &	expressionStateManager
	)

static

After the legalization, we are able to know accurate verilog AST structures.

So this function walks and prettifies verilog IR with a heuristic method specified by options.wireSpillingHeuristic based on the structures.

Definition at line 720 of file PrepareForEmission.cpp.

References circt::ExportVerilog::isVerilogExpression(), lowerUsersToTemporaryWire(), and EmittedExpressionStateManager::shouldSpillWireBasedOnState().

Referenced by circt::ExportVerilog::prepareHWModule().

◆ reuseExistingInOut()

static bool reuseExistingInOut	(	Operation *	op,
		const LoweringOptions &	options
	)

static

If exactly one use of this op is an assign, replace the other uses with a read from the assigned wire or reg.

This assumes the preconditions for doing so are met: op must be an expression in a non-procedural region.

Definition at line 617 of file PrepareForEmission.cpp.

References builder, circt::ExportVerilog::isExpressionAlwaysInline(), and lowerAlwaysInlineOperation().

Referenced by legalizeHWModule().

◆ rewriteAddWithNegativeConstant()

static Operation* rewriteAddWithNegativeConstant	(	comb::AddOp	add,
		hw::ConstantOp	rhsCst
	)

static

Transform "a + -cst" ==> "a - cst" for prettier output.

This returns the first operation emitted.

Definition at line 363 of file PrepareForEmission.cpp.

References builder.

Referenced by legalizeHWModule().

◆ rewriteSideEffectingExpr()

static bool rewriteSideEffectingExpr ( Operation * op )

static

This function is invoked on side effecting Verilog expressions when we're in 'disallowLocalVariables' mode for old Verilog clients.

This ensures that any side effecting expressions are only used by a single BPAssign to a sv.reg or sv.logic operation. This ensures that the verilog emitter doesn't have to worry about spilling them.

This returns true if the op was rewritten, false otherwise.

Definition at line 417 of file PrepareForEmission.cpp.

References assert(), builder, findParentInNonProceduralRegion(), and seq::reg().

Referenced by legalizeHWModule().

◆ shouldSpillWire()

static bool shouldSpillWire	(	Operation &	op,
		const LoweringOptions &	options
	)

static

Definition at line 61 of file PrepareForEmission.cpp.

References circt::ExportVerilog::isExpressionEmittedInline(), and circt::ExportVerilog::isVerilogExpression().

Referenced by legalizeHWModule(), and lowerAlwaysInlineOperation().

◆ spillWiresForInstanceInputs()

static void spillWiresForInstanceInputs ( HWInstanceLike op )

static

Definition at line 78 of file PrepareForEmission.cpp.

References builder, Python.support::connect(), getArgName(), and circt::ExportVerilog::isSimpleReadOrPort().

Referenced by legalizeHWModule().

Classes

Macros

Functions

Macro Definition Documentation

◆ DEBUG_TYPE

Function Documentation

◆ applyWireLowerings()

◆ buildWireLowerings()

◆ findLogicOpInsertionPoint()

◆ findParentInNonProceduralRegion()

◆ getArgName()

◆ getResName()

◆ hoistNonSideEffectExpr()

◆ isMovableDeclaration()

◆ legalizeHWModule()

◆ lowerAlwaysInlineOperation()

◆ lowerFullyAssociativeOp()

◆ lowerInstanceResults()

◆ lowerStructExplodeOp()

◆ lowerUsersToTemporaryWire()

◆ prettifyAfterLegalization()

◆ reuseExistingInOut()

◆ rewriteAddWithNegativeConstant()

◆ rewriteSideEffectingExpr()

◆ shouldSpillWire()

◆ spillWiresForInstanceInputs()