CIRCT
18.0.0git
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#include "circt/Conversion/ExportVerilog.h"
#include "../PassDetail.h"
#include "ExportVerilogInternals.h"
#include "circt/Dialect/Comb/CombDialect.h"
#include "circt/Dialect/Comb/CombVisitors.h"
#include "circt/Dialect/HW/HWAttributes.h"
#include "circt/Dialect/HW/HWOps.h"
#include "circt/Dialect/HW/HWTypes.h"
#include "circt/Dialect/HW/HWVisitors.h"
#include "circt/Dialect/LTL/LTLVisitors.h"
#include "circt/Dialect/OM/OMOps.h"
#include "circt/Dialect/SV/SVAttributes.h"
#include "circt/Dialect/SV/SVOps.h"
#include "circt/Dialect/SV/SVVisitors.h"
#include "circt/Dialect/Verif/VerifVisitors.h"
#include "circt/Support/LLVM.h"
#include "circt/Support/LoweringOptions.h"
#include "circt/Support/Path.h"
#include "circt/Support/PrettyPrinter.h"
#include "circt/Support/PrettyPrinterHelpers.h"
#include "circt/Support/Version.h"
#include "mlir/IR/BuiltinOps.h"
#include "mlir/IR/ImplicitLocOpBuilder.h"
#include "mlir/IR/Location.h"
#include "mlir/IR/Threading.h"
#include "mlir/Interfaces/FunctionImplementation.h"
#include "mlir/Pass/PassManager.h"
#include "mlir/Support/FileUtilities.h"
#include "llvm/ADT/MapVector.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/StringSet.h"
#include "llvm/ADT/TypeSwitch.h"
#include "llvm/Support/FileSystem.h"
#include "llvm/Support/FormattedStream.h"
#include "llvm/Support/Path.h"
#include "llvm/Support/SaveAndRestore.h"
#include "llvm/Support/ToolOutputFile.h"
#include "llvm/Support/raw_ostream.h"
Go to the source code of this file.
Classes | |
class | LocationEmitter |
struct | LocationEmitter::Impl |
Macros | |
#define | DEBUG_TYPE "export-verilog" |
Enumerations | |
enum class | BlockStatementCount { Zero , One , TwoOrMore } |
Functions | |
static TypedAttr | getInt32Attr (MLIRContext *ctx, uint32_t value) |
static TypedAttr | getIntAttr (MLIRContext *ctx, Type t, const APInt &value) |
static bool | isDuplicatableNullaryExpression (Operation *op) |
Return true for nullary operations that are better emitted multiple times as inline expression (when they have multiple uses) rather than having a temporary wire. More... | |
static bool | isDuplicatableExpression (Operation *op) |
template<typename PPS > | |
static void | emitZeroWidthIndexingValue (PPS &os) |
Emits a known-safe token that is legal when indexing into singleton arrays. More... | |
static StringRef | getPortVerilogName (Operation *module, PortInfo port) |
static StringRef | getPortVerilogName (Operation *module, size_t portArgNum) |
Return the verilog name of the port for the module. More... | |
static StringRef | getInputPortVerilogName (Operation *module, size_t portArgNum) |
Return the verilog name of the port for the module. More... | |
static void | getTypeDims (SmallVectorImpl< Attribute > &dims, Type type, Location loc) |
Push this type's dimension into a vector. More... | |
static bool | haveMatchingDims (Type a, Type b, Location loc) |
True iff 'a' and 'b' have the same wire dims. More... | |
static Type | stripUnpackedTypes (Type type) |
Given a set of known nested types (those supported by this pass), strip off leading unpacked types. More... | |
static bool | hasStructType (Type type) |
Return true if type has a struct type as a subtype. More... | |
static StringRef | getVerilogDeclWord (Operation *op, const LoweringOptions &options) |
Return the word (e.g. "reg") in Verilog to declare the specified thing. More... | |
static int | compareLocs (Location lhs, Location rhs) |
static int | compareLocsImpl (mlir::NameLoc lhs, mlir::NameLoc rhs) |
static int | compareLocsImpl (mlir::FileLineColLoc lhs, mlir::FileLineColLoc rhs) |
static int | compareLocsImpl (mlir::CallSiteLoc lhs, mlir::CallSiteLoc rhs) |
template<typename TTargetLoc > | |
FailureOr< int > | dispatchCompareLocations (Location lhs, Location rhs) |
static void | collectAndUniqueLocations (Location loc, SmallPtrSetImpl< Attribute > &locationSet) |
Pull apart any fused locations into the location set, such that they are uniqued. More... | |
template<typename TVector > | |
static void | sortLocationVector (TVector &vec) |
static bool | isOkToBitSelectFrom (Value v) |
Most expressions are invalid to bit-select from in Verilog, but some things are ok. More... | |
static bool | isExpressionUnableToInline (Operation *op, const LoweringOptions &options) |
Return true if we are unable to ever inline the specified operation. More... | |
static BlockStatementCount | countStatements (Block &block) |
Compute how many statements are within this block, for begin/end markers. More... | |
static IfOp | findNestedElseIf (Block *elseBlock) |
Find a nested IfOp in an else block that can be printed as else if instead of nesting it into a new begin - end block. More... | |
template<typename PPS > | |
static void | emitSVAttributesImpl (PPS &ps, ArrayAttr attrs, bool mayBreak) |
Emit SystemVerilog attributes. More... | |
StringRef | getVerilogValueName (Value val) |
Retrieve value's verilog name from IR. More... | |
static void | emitDim (Attribute width, raw_ostream &os, Location loc, ModuleEmitter &emitter, bool downTo) |
Emit a single dimension. More... | |
static void | emitDims (ArrayRef< Attribute > dims, raw_ostream &os, Location loc, ModuleEmitter &emitter) |
Emit a list of packed dimensions. More... | |
static bool | printPackedTypeImpl (Type type, raw_ostream &os, Location loc, SmallVectorImpl< Attribute > &dims, bool implicitIntType, bool singleBitDefaultType, ModuleEmitter &emitter, Type optionalAliasType={}) |
Output the basic type that consists of packed and primitive types. More... | |
static Value | isZeroExtension (Value value) |
If the specified extension is a zero extended version of another value, return the shorter value, otherwise return null. More... | |
static ValueRange | getNonOverlappingConcatSubrange (Value value) |
For a value concat(..., delay(const(true), 1, 0)) , return ... . More... | |
static bool | isExpressionEmittedInlineIntoProceduralDeclaration (Operation *op, StmtEmitter &stmtEmitter) |
Given an operation corresponding to a VerilogExpression, determine whether it is safe to emit inline into a 'localparam' or 'automatic logic' varaible initializer in a procedural region. More... | |
template<class AssignTy > | |
static AssignTy | getSingleAssignAndCheckUsers (Operation *op) |
static bool | checkDominanceOfUsers (Operation *op1, Operation *op2) |
Return true if op1 dominates users of op2 . More... | |
static void | emitOperation (VerilogEmitterState &state, Operation *op) |
static LogicalResult | exportVerilogImpl (ModuleOp module, llvm::raw_ostream &os) |
static std::unique_ptr< llvm::ToolOutputFile > | createOutputFile (StringRef fileName, StringRef dirname, SharedEmitterState &emitter) |
static void | createSplitOutputFile (StringAttr fileName, FileInfo &file, StringRef dirname, SharedEmitterState &emitter) |
static LogicalResult | exportSplitVerilogImpl (ModuleOp module, StringRef dirname) |
Variables | |
StringRef | circtHeader = "circt_header.svh" |
StringRef | circtHeaderInclude = "`include \"circt_header.svh\"\n" |
#define DEBUG_TYPE "export-verilog" |
Definition at line 66 of file ExportVerilog.cpp.
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Enumerator | |
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Zero | |
One | |
TwoOrMore |
Definition at line 836 of file ExportVerilog.cpp.
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Return true if op1
dominates users of op2
.
TODO: Use MLIR DominanceInfo.
Definition at line 5350 of file ExportVerilog.cpp.
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Pull apart any fused locations into the location set, such that they are uniqued.
Any other location type will be added as-is.
Definition at line 507 of file ExportVerilog.cpp.
Referenced by LocationEmitter::Impl::emitLocationInfo(), and LocationEmitter::LocationEmitter().
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Definition at line 479 of file ExportVerilog.cpp.
Referenced by compareLocsImpl().
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Definition at line 440 of file ExportVerilog.cpp.
References compareLocs().
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Definition at line 431 of file ExportVerilog.cpp.
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Definition at line 424 of file ExportVerilog.cpp.
References compareLocs().
Referenced by dispatchCompareLocations().
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Compute how many statements are within this block, for begin/end markers.
Definition at line 839 of file ExportVerilog.cpp.
References circt::ExportVerilog::isVerilogExpression().
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Definition at line 6446 of file ExportVerilog.cpp.
References circt::appendPossiblyAbsolutePath(), circt::ExportVerilog::SharedEmitterState::designOp, and circt::ExportVerilog::SharedEmitterState::encounteredError.
Referenced by createSplitOutputFile(), and exportSplitVerilogImpl().
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Definition at line 6472 of file ExportVerilog.cpp.
References circt::ExportVerilog::SharedEmitterState::collectOpsForFile(), createOutputFile(), circt::ExportVerilog::SharedEmitterState::emitOps(), circt::LoweringOptions::emitReplicatedOpsToHeader, circt::calyx::direction::get(), and circt::ExportVerilog::SharedEmitterState::options.
FailureOr<int> dispatchCompareLocations | ( | Location | lhs, |
Location | rhs | ||
) |
Definition at line 452 of file ExportVerilog.cpp.
References compareLocsImpl().
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Emit a single dimension.
Definition at line 1548 of file ExportVerilog.cpp.
References circt::calyx::direction::get(), getIntAttr(), and width.
Referenced by emitDims().
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Emit a list of packed dimensions.
Definition at line 1592 of file ExportVerilog.cpp.
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Definition at line 6225 of file ExportVerilog.cpp.
Referenced by circt::ExportVerilog::SharedEmitterState::emitOps().
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Emit SystemVerilog attributes.
Definition at line 937 of file ExportVerilog.cpp.
References assert().
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Emits a known-safe token that is legal when indexing into singleton arrays.
Definition at line 216 of file ExportVerilog.cpp.
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Definition at line 6494 of file ExportVerilog.cpp.
References append(), circtHeader, createOutputFile(), circt::LoweringOptions::emitReplicatedOpsToHeader, circt::ExportVerilog::SharedEmitterState::encounteredError, circt::ExportVerilog::SharedEmitterState::fileLists, circt::ExportVerilog::SharedEmitterState::files, circt::ExportVerilog::SharedEmitterState::gatherFiles(), circt::calyx::direction::get(), circt::ExportVerilog::legalizeGlobalNames(), and circt::ExportVerilog::SharedEmitterState::options.
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Definition at line 6341 of file ExportVerilog.cpp.
References circt::ExportVerilog::SharedEmitterState::collectOpsForFile(), circt::ExportVerilog::SharedEmitterState::emitOps(), circt::LoweringOptions::emitReplicatedOpsToHeader, circt::ExportVerilog::SharedEmitterState::encounteredError, circt::ExportVerilog::SharedEmitterState::fileLists, circt::ExportVerilog::SharedEmitterState::files, circt::ExportVerilog::SharedEmitterState::gatherFiles(), circt::calyx::direction::get(), circt::ExportVerilog::legalizeGlobalNames(), circt::ExportVerilog::SharedEmitterState::options, and circt::ExportVerilog::SharedEmitterState::rootFile.
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Find a nested IfOp in an else block that can be printed as else if
instead of nesting it into a new begin
- end
block.
The block must contain a single IfOp and optionally expressions which can be hoisted out.
Definition at line 916 of file ExportVerilog.cpp.
References hasSVAttributes(), and circt::ExportVerilog::isVerilogExpression().
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Return the verilog name of the port for the module.
Definition at line 235 of file ExportVerilog.cpp.
References getPortVerilogName().
Referenced by getVerilogValueName().
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For a value concat(..., delay(const(true), 1, 0))
, return ...
.
This is useful for emitting (seq ##1 true) |-> prop
as seq |=> prop
.
Definition at line 3544 of file ExportVerilog.cpp.
References value.
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Definition at line 220 of file ExportVerilog.cpp.
Referenced by getInputPortVerilogName(), getPortVerilogName(), and circt::ExportVerilog::inferStructuralNameForTemporary().
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Return the verilog name of the port for the module.
Definition at line 229 of file ExportVerilog.cpp.
References getPortVerilogName().
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Definition at line 5330 of file ExportVerilog.cpp.
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Push this type's dimension into a vector.
Definition at line 261 of file ExportVerilog.cpp.
References getInt32Attr().
Referenced by haveMatchingDims().
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Return the word (e.g. "reg") in Verilog to declare the specified thing.
Definition at line 353 of file ExportVerilog.cpp.
References assert(), circt::LoweringOptions::disallowLocalVariables, elementType, hasStructType(), and circt::esi::innerType().
StringRef getVerilogValueName | ( | Value | val | ) |
Retrieve value's verilog name from IR.
The name must already have been added in pre-pass and passed through "hw.verilogName" attr.
Definition at line 992 of file ExportVerilog.cpp.
References assert(), getInputPortVerilogName(), and circt::ExportVerilog::getSymOpName().
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Return true if type has a struct type as a subtype.
Definition at line 342 of file ExportVerilog.cpp.
Referenced by getVerilogDeclWord().
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True iff 'a' and 'b' have the same wire dims.
Definition at line 291 of file ExportVerilog.cpp.
References getTypeDims().
Referenced by isExpressionUnableToInline().
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Definition at line 157 of file ExportVerilog.cpp.
References isDuplicatableNullaryExpression().
Referenced by circt::ExportVerilog::isExpressionEmittedInline().
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Return true for nullary operations that are better emitted multiple times as inline expression (when they have multiple uses) rather than having a temporary wire.
This can only handle nullary expressions, because we don't want to replicate subtrees arbitrarily.
Definition at line 130 of file ExportVerilog.cpp.
References circt::ExportVerilog::isConstantExpression().
Referenced by isDuplicatableExpression().
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Given an operation corresponding to a VerilogExpression, determine whether it is safe to emit inline into a 'localparam' or 'automatic logic' varaible initializer in a procedural region.
We can't emit exprs inline when they refer to something else that can't be emitted inline, when they're in a general #ifdef region,
Definition at line 5248 of file ExportVerilog.cpp.
References circt::ExportVerilog::isExpressionEmittedInline(), and circt::ExportVerilog::isVerilogExpression().
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Return true if we are unable to ever inline the specified operation.
This happens because not all Verilog expressions are composable, notably you can only use bit selects like x[4:6] on simple expressions, you cannot use expressions in the sensitivity list of always blocks, etc.
Definition at line 778 of file ExportVerilog.cpp.
References circt::LoweringOptions::allowExprInEventControl, haveMatchingDims(), and isOkToBitSelectFrom().
Referenced by circt::ExportVerilog::isExpressionEmittedInline().
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Most expressions are invalid to bit-select from in Verilog, but some things are ok.
Return true if it is ok to inline bitselect from the result of this expression. It is conservatively correct to return false.
Definition at line 751 of file ExportVerilog.cpp.
Referenced by isExpressionUnableToInline().
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If the specified extension is a zero extended version of another value, return the shorter value, otherwise return null.
Definition at line 2465 of file ExportVerilog.cpp.
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Output the basic type that consists of packed and primitive types.
This is those to the left of the name in verilog. implicitIntType controls whether to print a base type for (logic) for inteters or whether the caller will have handled this (with logic, wire, reg, etc). optionalAliasType can be provided to perform any necessary alias-aware printing of 'type'.
Returns true when anything was printed out.
Definition at line 1615 of file ExportVerilog.cpp.
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Definition at line 519 of file ExportVerilog.cpp.
Referenced by LocationEmitter::Impl::emitLocationSetInfoImpl().
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Given a set of known nested types (those supported by this pass), strip off leading unpacked types.
This strips off portions of the type that are printed to the right of the name in verilog.
Definition at line 330 of file ExportVerilog.cpp.
StringRef circtHeader = "circt_header.svh" |
Definition at line 68 of file ExportVerilog.cpp.
Referenced by exportSplitVerilogImpl().
StringRef circtHeaderInclude = "`include \"circt_header.svh\"\n" |
Definition at line 69 of file ExportVerilog.cpp.
Referenced by circt::ExportVerilog::SharedEmitterState::collectOpsForFile().