ExportVerilog.cpp File Reference

#include "circt/Conversion/ExportVerilog.h"
#include "ExportVerilogInternals.h"
#include "circt/Dialect/Comb/CombDialect.h"
#include "circt/Dialect/Comb/CombVisitors.h"
#include "circt/Dialect/Debug/DebugDialect.h"
#include "circt/Dialect/Emit/EmitOps.h"
#include "circt/Dialect/HW/HWAttributes.h"
#include "circt/Dialect/HW/HWOps.h"
#include "circt/Dialect/HW/HWTypes.h"
#include "circt/Dialect/HW/HWVisitors.h"
#include "circt/Dialect/LTL/LTLVisitors.h"
#include "circt/Dialect/OM/OMOps.h"
#include "circt/Dialect/SV/SVAttributes.h"
#include "circt/Dialect/SV/SVOps.h"
#include "circt/Dialect/SV/SVVisitors.h"
#include "circt/Dialect/Verif/VerifVisitors.h"
#include "circt/Support/LLVM.h"
#include "circt/Support/LoweringOptions.h"
#include "circt/Support/Path.h"
#include "circt/Support/PrettyPrinter.h"
#include "circt/Support/PrettyPrinterHelpers.h"
#include "circt/Support/Version.h"
#include "mlir/IR/BuiltinOps.h"
#include "mlir/IR/ImplicitLocOpBuilder.h"
#include "mlir/IR/Location.h"
#include "mlir/IR/Threading.h"
#include "mlir/Interfaces/FunctionImplementation.h"
#include "mlir/Pass/PassManager.h"
#include "mlir/Support/FileUtilities.h"
#include "llvm/ADT/MapVector.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/StringSet.h"
#include "llvm/ADT/TypeSwitch.h"
#include "llvm/Support/FileSystem.h"
#include "llvm/Support/FormattedStream.h"
#include "llvm/Support/Path.h"
#include "llvm/Support/SaveAndRestore.h"
#include "llvm/Support/ToolOutputFile.h"
#include "llvm/Support/raw_ostream.h"
#include "circt/Conversion/Passes.h.inc"

Include dependency graph for ExportVerilog.cpp:

Go to the source code of this file.

Classes
class	LocationEmitter
struct	LocationEmitter::Impl
class	FileEmitter

Namespaces
namespace	circt
	The InstanceGraph op interface, see InstanceGraphInterface.td for more details.

Macros
#define	GEN_PASS_DEF_EXPORTSPLITVERILOG
#define	GEN_PASS_DEF_EXPORTVERILOG
#define	DEBUG_TYPE   "export-verilog"

Enumerations
enum class	BlockStatementCount { Zero , One , TwoOrMore }

Functions
static TypedAttr	getInt32Attr (MLIRContext *ctx, uint32_t value)
static TypedAttr	getIntAttr (MLIRContext *ctx, Type t, const APInt &value)
static bool	isDuplicatableNullaryExpression (Operation *op)
	Return true for nullary operations that are better emitted multiple times as inline expression (when they have multiple uses) rather than having a temporary wire.
static bool	isDuplicatableExpression (Operation *op)
template<typename PPS >
static void	emitZeroWidthIndexingValue (PPS &os)
	Emits a known-safe token that is legal when indexing into singleton arrays.
static StringRef	getPortVerilogName (Operation *module, size_t portArgNum)
	Return the verilog name of the port for the module.
static StringRef	getInputPortVerilogName (Operation *module, size_t portArgNum)
	Return the verilog name of the port for the module.
static void	getTypeDims (SmallVectorImpl< Attribute > &dims, Type type, Location loc)
	Push this type's dimension into a vector.
static bool	haveMatchingDims (Type a, Type b, Location loc)
	True iff 'a' and 'b' have the same wire dims.
static Type	stripUnpackedTypes (Type type)
	Given a set of known nested types (those supported by this pass), strip off leading unpacked types.
static bool	hasLeadingUnpackedType (Type type)
	Return true if the type has a leading unpacked type.
static bool	hasStructType (Type type)
	Return true if type has a struct type as a subtype.
static int	compareLocs (Location lhs, Location rhs)
static int	compareLocsImpl (mlir::NameLoc lhs, mlir::NameLoc rhs)
static int	compareLocsImpl (mlir::FileLineColLoc lhs, mlir::FileLineColLoc rhs)
static int	compareLocsImpl (mlir::CallSiteLoc lhs, mlir::CallSiteLoc rhs)
template<typename TTargetLoc >
FailureOr< int >	dispatchCompareLocations (Location lhs, Location rhs)
static void	collectAndUniqueLocations (Location loc, SmallPtrSetImpl< Attribute > &locationSet)
	Pull apart any fused locations into the location set, such that they are uniqued.
template<typename TVector >
static void	sortLocationVector (TVector &vec)
static bool	isOkToBitSelectFrom (Value v)
	Most expressions are invalid to bit-select from in Verilog, but some things are ok.
static bool	isExpressionUnableToInline (Operation *op, const LoweringOptions &options)
	Return true if we are unable to ever inline the specified operation.
static BlockStatementCount	countStatements (Block &block)
	Compute how many statements are within this block, for begin/end markers.
static IfOp	findNestedElseIf (Block *elseBlock)
	Find a nested IfOp in an else block that can be printed as else if instead of nesting it into a new begin - end block.
template<typename PPS >
static void	emitSVAttributesImpl (PPS &ps, ArrayAttr attrs, bool mayBreak)
	Emit SystemVerilog attributes.
StringRef	getVerilogValueName (Value val)
	Retrieve value's verilog name from IR.
static StringRef	getVerilogDeclWord (Operation *op, const ModuleEmitter &emitter)
	Return the word (e.g.
static void	emitDim (Attribute width, raw_ostream &os, Location loc, ModuleEmitter &emitter, bool downTo)
	Emit a single dimension.
static void	emitDims (ArrayRef< Attribute > dims, raw_ostream &os, Location loc, ModuleEmitter &emitter)
	Emit a list of packed dimensions.
static StringRef	getTwoStateIntegerAtomType (size_t width)
	Return a 2-state integer atom type name if the width matches.
static bool	printPackedTypeImpl (Type type, raw_ostream &os, Location loc, SmallVectorImpl< Attribute > &dims, bool implicitIntType, bool singleBitDefaultType, ModuleEmitter &emitter, Type optionalAliasType={}, bool emitAsTwoStateType=false)
	Output the basic type that consists of packed and primitive types.
static Value	isZeroExtension (Value value)
	If the specified extension is a zero extended version of another value, return the shorter value, otherwise return null.
static ValueRange	getNonOverlappingConcatSubrange (Value value)
	For a value concat(..., delay(const(true), 1, 0)), return ....
template<typename PPS >
void	emitFunctionSignature (ModuleEmitter &emitter, PPS &ps, FuncOp op, bool isAutomatic=false, bool emitAsTwoStateType=false)
static bool	isExpressionEmittedInlineIntoProceduralDeclaration (Operation *op, StmtEmitter &stmtEmitter)
	Given an operation corresponding to a VerilogExpression, determine whether it is safe to emit inline into a 'localparam' or 'automatic logic' varaible initializer in a procedural region.
template<class AssignTy >
static AssignTy	getSingleAssignAndCheckUsers (Operation *op)
static bool	checkDominanceOfUsers (Operation *op1, Operation *op2)
	Return true if op1 dominates users of op2.
static void	emitOperation (VerilogEmitterState &state, Operation *op)
static LogicalResult	exportVerilogImpl (ModuleOp module, llvm::raw_ostream &os)
static std::unique_ptr< llvm::ToolOutputFile >	createOutputFile (StringRef fileName, StringRef dirname, SharedEmitterState &emitter)
static void	createSplitOutputFile (StringAttr fileName, FileInfo &file, StringRef dirname, SharedEmitterState &emitter)
static LogicalResult	exportSplitVerilogImpl (ModuleOp module, StringRef dirname)

Variables
StringRef	circtHeader = "circt_header.svh"
StringRef	circtHeaderInclude = "`include \"circt_header.svh\"\n"

Macro Definition Documentation

DEBUG_TYPE

#define DEBUG_TYPE   "export-verilog"

Definition at line 72 of file ExportVerilog.cpp.

GEN_PASS_DEF_EXPORTSPLITVERILOG

#define GEN_PASS_DEF_EXPORTSPLITVERILOG

Definition at line 59 of file ExportVerilog.cpp.

GEN_PASS_DEF_EXPORTVERILOG

#define GEN_PASS_DEF_EXPORTVERILOG

Definition at line 60 of file ExportVerilog.cpp.

Enumeration Type Documentation

BlockStatementCount

enum class BlockStatementCount

strong

Enumerator
Zero
One
TwoOrMore

Definition at line 819 of file ExportVerilog.cpp.

Function Documentation

checkDominanceOfUsers()

static bool checkDominanceOfUsers ( Operation *  op1, Operation *  op2  )

static

Return true if op1 dominates users of op2.

TODO: Use MLIR DominanceInfo.

Definition at line 5882 of file ExportVerilog.cpp.

collectAndUniqueLocations()

static void collectAndUniqueLocations ( Location  loc, SmallPtrSetImpl< Attribute > &  locationSet  )

static

Pull apart any fused locations into the location set, such that they are uniqued.

Any other location type will be added as-is.

Definition at line 459 of file ExportVerilog.cpp.

References collectAndUniqueLocations().

Referenced by collectAndUniqueLocations(), LocationEmitter::Impl::emitLocationInfo(), and LocationEmitter::LocationEmitter().

compareLocs()

static int compareLocs ( Location  lhs, Location  rhs  )

static

Definition at line 431 of file ExportVerilog.cpp.

Referenced by compareLocsImpl(), and compareLocsImpl().

compareLocsImpl() [1/3]

static int compareLocsImpl ( mlir::CallSiteLoc  lhs, mlir::CallSiteLoc  rhs  )

static

Definition at line 392 of file ExportVerilog.cpp.

References compareLocs().

compareLocsImpl() [2/3]

static int compareLocsImpl ( mlir::FileLineColLoc  lhs, mlir::FileLineColLoc  rhs  )

static

Definition at line 383 of file ExportVerilog.cpp.

compareLocsImpl() [3/3]

static int compareLocsImpl ( mlir::NameLoc  lhs, mlir::NameLoc  rhs  )

static

Definition at line 376 of file ExportVerilog.cpp.

References compareLocs().

Referenced by dispatchCompareLocations().

countStatements()

static BlockStatementCount countStatements ( Block &  block )

static

Compute how many statements are within this block, for begin/end markers.

Definition at line 822 of file ExportVerilog.cpp.

References circt::ExportVerilog::isVerilogExpression(), One, TwoOrMore, and Zero.

createOutputFile()

static std::unique_ptr< llvm::ToolOutputFile > createOutputFile ( StringRef  fileName, StringRef  dirname, SharedEmitterState &  emitter  )

static

Definition at line 7163 of file ExportVerilog.cpp.

References circt::appendPossiblyAbsolutePath(), circt::ExportVerilog::SharedEmitterState::designOp, and circt::ExportVerilog::SharedEmitterState::encounteredError.

Referenced by createSplitOutputFile(), and exportSplitVerilogImpl().

createSplitOutputFile()

static void createSplitOutputFile ( StringAttr  fileName, FileInfo &  file, StringRef  dirname, SharedEmitterState &  emitter  )

static

Definition at line 7189 of file ExportVerilog.cpp.

References circt::ExportVerilog::SharedEmitterState::collectOpsForFile(), createOutputFile(), circt::ExportVerilog::SharedEmitterState::emitOps(), circt::LoweringOptions::emitReplicatedOpsToHeader, and circt::ExportVerilog::SharedEmitterState::options.

dispatchCompareLocations()

template<typename TTargetLoc >

FailureOr< int > dispatchCompareLocations	(	Location	lhs,
		Location	rhs
	)

Definition at line 404 of file ExportVerilog.cpp.

References compareLocsImpl().

emitDim()

static void emitDim ( Attribute  width, raw_ostream &  os, Location  loc, ModuleEmitter &  emitter, bool  downTo  )

static

Emit a single dimension.

Definition at line 1608 of file ExportVerilog.cpp.

References getIntAttr().

Referenced by emitDims().

emitDims()

static void emitDims ( ArrayRef< Attribute >  dims, raw_ostream &  os, Location  loc, ModuleEmitter &  emitter  )

static

Emit a list of packed dimensions.

Definition at line 1652 of file ExportVerilog.cpp.

References emitDim().

emitFunctionSignature()

template<typename PPS >

void emitFunctionSignature	(	ModuleEmitter &	emitter,
		PPS &	ps,
		FuncOp	op,
		bool	isAutomatic = false,
		bool	emitAsTwoStateType = false
	)

Definition at line 4474 of file ExportVerilog.cpp.

References circt::ExportVerilog::getSymOpName().

emitOperation()

static void emitOperation ( VerilogEmitterState &  state, Operation *  op  )

static

Definition at line 6932 of file ExportVerilog.cpp.

References FileEmitter::emit().

Referenced by circt::ExportVerilog::SharedEmitterState::emitOps().

emitSVAttributesImpl()

template<typename PPS >

static void emitSVAttributesImpl ( PPS &  ps, ArrayAttr  attrs, bool  mayBreak  )

static

Emit SystemVerilog attributes.

Definition at line 920 of file ExportVerilog.cpp.

References assert().

emitZeroWidthIndexingValue()

template<typename PPS >

static void emitZeroWidthIndexingValue ( PPS &  os )

static

Emits a known-safe token that is legal when indexing into singleton arrays.

Definition at line 222 of file ExportVerilog.cpp.

exportSplitVerilogImpl()

static LogicalResult exportSplitVerilogImpl ( ModuleOp  module, StringRef  dirname  )

static

Definition at line 7211 of file ExportVerilog.cpp.

References circtHeader, createOutputFile(), circt::LoweringOptions::emitReplicatedOpsToHeader, circt::ExportVerilog::SharedEmitterState::encounteredError, circt::ExportVerilog::SharedEmitterState::fileLists, circt::ExportVerilog::SharedEmitterState::files, circt::ExportVerilog::SharedEmitterState::gatherFiles(), circt::ExportVerilog::legalizeGlobalNames(), and circt::ExportVerilog::SharedEmitterState::options.

exportVerilogImpl()

static LogicalResult exportVerilogImpl ( ModuleOp  module, llvm::raw_ostream &  os  )

static

Definition at line 7053 of file ExportVerilog.cpp.

References circt::ExportVerilog::SharedEmitterState::collectOpsForFile(), circt::ExportVerilog::SharedEmitterState::emitOps(), circt::LoweringOptions::emitReplicatedOpsToHeader, circt::ExportVerilog::SharedEmitterState::encounteredError, circt::ExportVerilog::SharedEmitterState::fileLists, circt::ExportVerilog::SharedEmitterState::files, circt::ExportVerilog::SharedEmitterState::gatherFiles(), circt::ExportVerilog::legalizeGlobalNames(), circt::ExportVerilog::SharedEmitterState::options, and circt::ExportVerilog::SharedEmitterState::rootFile.

findNestedElseIf()

static IfOp findNestedElseIf ( Block *  elseBlock )

static

Find a nested IfOp in an else block that can be printed as else if instead of nesting it into a new begin - end block.

The block must contain a single IfOp and optionally expressions which can be hoisted out.

Definition at line 899 of file ExportVerilog.cpp.

References hasSVAttributes(), and circt::ExportVerilog::isVerilogExpression().

getInputPortVerilogName()

static StringRef getInputPortVerilogName ( Operation *  module, size_t  portArgNum  )

static

Return the verilog name of the port for the module.

Definition at line 233 of file ExportVerilog.cpp.

Referenced by getVerilogValueName().

getInt32Attr()

static TypedAttr getInt32Attr ( MLIRContext *  ctx, uint32_t  value  )

static

Definition at line 122 of file ExportVerilog.cpp.

Referenced by getTypeDims().

getIntAttr()

static TypedAttr getIntAttr ( MLIRContext *  ctx, Type  t, const APInt &  value  )

static

Definition at line 126 of file ExportVerilog.cpp.

Referenced by emitDim(), and foldMod().

getNonOverlappingConcatSubrange()

static ValueRange getNonOverlappingConcatSubrange ( Value  value )

static

For a value concat(..., delay(const(true), 1, 0)), return ....

This is useful for emitting (seq ##1 true) |-> prop as seq |=> prop.

Definition at line 3832 of file ExportVerilog.cpp.

getPortVerilogName()

static StringRef getPortVerilogName ( Operation *  module, size_t  portArgNum  )

static

Return the verilog name of the port for the module.

Definition at line 227 of file ExportVerilog.cpp.

Referenced by circt::ExportVerilog::inferStructuralNameForTemporary().

getSingleAssignAndCheckUsers()

template<class AssignTy >

static AssignTy getSingleAssignAndCheckUsers ( Operation *  op )

static

Definition at line 5862 of file ExportVerilog.cpp.

getTwoStateIntegerAtomType()

static StringRef getTwoStateIntegerAtomType ( size_t  width )

static

Return a 2-state integer atom type name if the width matches.

See Spec 6.8 Variable declarations.

Definition at line 1668 of file ExportVerilog.cpp.

getTypeDims()

static void getTypeDims ( SmallVectorImpl< Attribute > &  dims, Type  type, Location  loc  )

static

Push this type's dimension into a vector.

Definition at line 266 of file ExportVerilog.cpp.

References getInt32Attr(), and getTypeDims().

Referenced by getTypeDims(), and haveMatchingDims().

getVerilogDeclWord()

static StringRef getVerilogDeclWord ( Operation *  op, const ModuleEmitter &  emitter  )

static

Return the word (e.g.

"reg") in Verilog to declare the specified thing. If stripAutomatic is true, "automatic" is not used even for a declaration in a non-procedural region.

Definition at line 1534 of file ExportVerilog.cpp.

References assert(), elementType, and hasStructType().

getVerilogValueName()

StringRef getVerilogValueName

(

Value

val

)

Retrieve value's verilog name from IR.

The name must already have been added in pre-pass and passed through "hw.verilogName" attr.

Definition at line 975 of file ExportVerilog.cpp.

References assert(), getInputPortVerilogName(), and circt::ExportVerilog::getSymOpName().

hasLeadingUnpackedType()

static bool hasLeadingUnpackedType ( Type  type )

static

Return true if the type has a leading unpacked type.

Definition at line 350 of file ExportVerilog.cpp.

References assert(), elementType, and stripUnpackedTypes().

hasStructType()

static bool hasStructType ( Type  type )

static

Return true if type has a struct type as a subtype.

Definition at line 357 of file ExportVerilog.cpp.

References hasStructType().

Referenced by getVerilogDeclWord(), and hasStructType().

haveMatchingDims()

static bool haveMatchingDims ( Type  a, Type  b, Location  loc  )

static

True iff 'a' and 'b' have the same wire dims.

Definition at line 299 of file ExportVerilog.cpp.

References getTypeDims().

Referenced by isExpressionUnableToInline().

isDuplicatableExpression()

static bool isDuplicatableExpression ( Operation *  op )

static

Definition at line 163 of file ExportVerilog.cpp.

References isDuplicatableNullaryExpression().

Referenced by circt::ExportVerilog::isExpressionEmittedInline().

isDuplicatableNullaryExpression()

static bool isDuplicatableNullaryExpression ( Operation *  op )

static

Return true for nullary operations that are better emitted multiple times as inline expression (when they have multiple uses) rather than having a temporary wire.

This can only handle nullary expressions, because we don't want to replicate subtrees arbitrarily.

Definition at line 136 of file ExportVerilog.cpp.

References circt::ExportVerilog::isConstantExpression().

Referenced by isDuplicatableExpression().

isExpressionEmittedInlineIntoProceduralDeclaration()

static bool isExpressionEmittedInlineIntoProceduralDeclaration ( Operation *  op, StmtEmitter &  stmtEmitter  )

static

Given an operation corresponding to a VerilogExpression, determine whether it is safe to emit inline into a 'localparam' or 'automatic logic' varaible initializer in a procedural region.

We can't emit exprs inline when they refer to something else that can't be emitted inline, when they're in a general #ifdef region,

Definition at line 5780 of file ExportVerilog.cpp.

References circt::ExportVerilog::isExpressionEmittedInline(), and circt::ExportVerilog::isVerilogExpression().

isExpressionUnableToInline()

static bool isExpressionUnableToInline ( Operation *  op, const LoweringOptions &  options  )

static

Return true if we are unable to ever inline the specified operation.

This happens because not all Verilog expressions are composable, notably you can only use bit selects like x[4:6] on simple expressions, you cannot use expressions in the sensitivity list of always blocks, etc.

Definition at line 730 of file ExportVerilog.cpp.

References circt::LoweringOptions::allowExprInEventControl, haveMatchingDims(), and isOkToBitSelectFrom().

Referenced by circt::ExportVerilog::isExpressionEmittedInline().

isOkToBitSelectFrom()

static bool isOkToBitSelectFrom ( Value  v )

static

Most expressions are invalid to bit-select from in Verilog, but some things are ok.

Return true if it is ok to inline bitselect from the result of this expression. It is conservatively correct to return false.

Definition at line 703 of file ExportVerilog.cpp.

Referenced by isExpressionUnableToInline().

isZeroExtension()

static Value isZeroExtension ( Value  value )

static

If the specified extension is a zero extended version of another value, return the shorter value, otherwise return null.

Definition at line 2578 of file ExportVerilog.cpp.

References concat().

printPackedTypeImpl()

static bool printPackedTypeImpl ( Type  type, raw_ostream &  os, Location  loc, SmallVectorImpl< Attribute > &  dims, bool  implicitIntType, bool  singleBitDefaultType, ModuleEmitter &  emitter, Type  optionalAliasType = {}, bool  emitAsTwoStateType = false  )

static

Output the basic type that consists of packed and primitive types.

This is those to the left of the name in verilog. implicitIntType controls whether to print a base type for (logic) for inteters or whether the caller will have handled this (with logic, wire, reg, etc). optionalAliasType can be provided to perform any necessary alias-aware printing of 'type'.

Returns true when anything was printed out.

Definition at line 1692 of file ExportVerilog.cpp.

sortLocationVector()

template<typename TVector >

static void sortLocationVector ( TVector &  vec )

static

Definition at line 471 of file ExportVerilog.cpp.

Referenced by LocationEmitter::Impl::emitLocationSetInfoImpl().

stripUnpackedTypes()

static Type stripUnpackedTypes ( Type  type )

static

Given a set of known nested types (those supported by this pass), strip off leading unpacked types.

This strips off portions of the type that are printed to the right of the name in verilog.

Definition at line 338 of file ExportVerilog.cpp.

References stripUnpackedTypes().

Referenced by hasLeadingUnpackedType(), and stripUnpackedTypes().

Variable Documentation

circtHeader

StringRef circtHeader = "circt_header.svh"

Definition at line 74 of file ExportVerilog.cpp.

Referenced by exportSplitVerilogImpl().

circtHeaderInclude

StringRef circtHeaderInclude = "`include \"circt_header.svh\"\n"

Definition at line 75 of file ExportVerilog.cpp.

Referenced by circt::ExportVerilog::SharedEmitterState::collectOpsForFile().