#include "circt/Conversion/ExportVerilog.h"
#include "ExportVerilogInternals.h"
#include "circt/Dialect/Comb/CombDialect.h"
#include "circt/Dialect/Comb/CombVisitors.h"
#include "circt/Dialect/Debug/DebugDialect.h"
#include "circt/Dialect/Emit/EmitOps.h"
#include "circt/Dialect/HW/HWAttributes.h"
#include "circt/Dialect/HW/HWOps.h"
#include "circt/Dialect/HW/HWTypes.h"
#include "circt/Dialect/HW/HWVisitors.h"
#include "circt/Dialect/LTL/LTLVisitors.h"
#include "circt/Dialect/OM/OMOps.h"
#include "circt/Dialect/SV/SVAttributes.h"
#include "circt/Dialect/SV/SVOps.h"
#include "circt/Dialect/SV/SVTypes.h"
#include "circt/Dialect/SV/SVVisitors.h"
#include "circt/Dialect/Verif/VerifVisitors.h"
#include "circt/Support/LLVM.h"
#include "circt/Support/LoweringOptions.h"
#include "circt/Support/Path.h"
#include "circt/Support/PrettyPrinter.h"
#include "circt/Support/PrettyPrinterHelpers.h"
#include "circt/Support/ProceduralRegionTrait.h"
#include "circt/Support/Version.h"
#include "mlir/IR/BuiltinOps.h"
#include "mlir/IR/ImplicitLocOpBuilder.h"
#include "mlir/IR/Location.h"
#include "mlir/IR/Threading.h"
#include "mlir/Interfaces/FunctionImplementation.h"
#include "mlir/Pass/PassManager.h"
#include "mlir/Support/FileUtilities.h"
#include "llvm/ADT/MapVector.h"
#include "llvm/ADT/STLExtras.h"
#include "llvm/ADT/StringSet.h"
#include "llvm/ADT/TypeSwitch.h"
#include "llvm/Support/FileSystem.h"
#include "llvm/Support/FormattedStream.h"
#include "llvm/Support/Path.h"
#include "llvm/Support/SaveAndRestore.h"
#include "llvm/Support/ToolOutputFile.h"
#include "llvm/Support/raw_ostream.h"
#include "circt/Conversion/Passes.h.inc"

Include dependency graph for ExportVerilog.cpp:

Classes
class	LocationEmitter
struct	LocationEmitter::Impl
class	FileEmitter

Namespaces
namespace	circt
	The InstanceGraph op interface, see InstanceGraphInterface.td for more details.

Macros
#define	GEN_PASS_DEF_EXPORTSPLITVERILOG
#define	GEN_PASS_DEF_EXPORTVERILOG
#define	DEBUG_TYPE "export-verilog"

Enumerations
enum class	BlockStatementCount { Zero , One , TwoOrMore }

Functions
static TypedAttr	getInt32Attr (MLIRContext *ctx, uint32_t value)
static TypedAttr	getIntAttr (MLIRContext *ctx, Type t, const APInt &value)
static bool	isDuplicatableNullaryExpression (Operation *op)
	Return true for nullary operations that are better emitted multiple times as inline expression (when they have multiple uses) rather than having a temporary wire.
static bool	isDuplicatableExpression (Operation *op)
template<typename PPS>
static void	emitZeroWidthIndexingValue (PPS &os)
	Emits a known-safe token that is legal when indexing into singleton arrays.
static StringRef	getPortVerilogName (Operation *module, size_t portArgNum)
	Return the verilog name of the port for the module.
static StringRef	getInputPortVerilogName (Operation *module, size_t portArgNum)
	Return the verilog name of the port for the module.
static void	getTypeDims (SmallVectorImpl< Attribute > &dims, Type type, Location loc, llvm::function_ref< mlir::InFlightDiagnostic(Location)> errorHandler)
	Push this type's dimension into a vector.
static bool	haveMatchingDims (Type a, Type b, Location loc, llvm::function_ref< mlir::InFlightDiagnostic(Location)> errorHandler)
	True iff 'a' and 'b' have the same wire dims.
static Type	stripUnpackedTypes (Type type)
	Given a set of known nested types (those supported by this pass), strip off leading unpacked types.
static bool	hasLeadingUnpackedType (Type type)
	Return true if the type has a leading unpacked type.
static bool	hasStructType (Type type)
	Return true if the element type is emitted as a type name or a keyword (struct, union, enum or typedef), so that no "logic" prefix is allowed.
static int	compareLocs (Location lhs, Location rhs)
static int	compareLocsImpl (mlir::NameLoc lhs, mlir::NameLoc rhs)
static int	compareLocsImpl (mlir::FileLineColLoc lhs, mlir::FileLineColLoc rhs)
static int	compareLocsImpl (mlir::CallSiteLoc lhs, mlir::CallSiteLoc rhs)
template<typename TTargetLoc>
FailureOr< int >	dispatchCompareLocations (Location lhs, Location rhs)
static void	collectAndUniqueLocations (Location loc, SmallPtrSetImpl< Attribute > &locationSet)
	Pull apart any fused locations into the location set, such that they are uniqued.
template<typename TVector>
static void	sortLocationVector (TVector &vec)
static bool	isOkToBitSelectFrom (Value v)
	Most expressions are invalid to bit-select from in Verilog, but some things are ok.
static bool	isExpressionUnableToInline (Operation *op, const LoweringOptions &options)
	Return true if we are unable to ever inline the specified operation.
static BlockStatementCount	countStatements (Block &block)
	Compute how many statements are within this block, for begin/end markers.
static IfOp	findNestedElseIf (Block *elseBlock)
	Find a nested IfOp in an else block that can be printed as else if instead of nesting it into a new begin - end block.
template<typename PPS>
static void	emitSVAttributesImpl (PPS &ps, ArrayAttr attrs, bool mayBreak)
	Emit SystemVerilog attributes.
StringRef	getVerilogValueName (Value val)
	Retrieve value's verilog name from IR.
static bool	hasExplicitDataType (Type type)
	Returns true if type prints its own SystemVerilog data_type, so its declaration must not be prefixed with logic or reg.
static StringRef	getVerilogDeclWord (Operation *op, const ModuleEmitter &emitter)
	Return the word (e.g.
static void	emitDim (Attribute width, raw_ostream &os, Location loc, ModuleEmitter &emitter, bool downTo)
	Emit a single dimension.
static void	emitDims (ArrayRef< Attribute > dims, raw_ostream &os, Location loc, ModuleEmitter &emitter)
	Emit a list of packed dimensions.
static StringRef	getTwoStateIntegerAtomType (size_t width)
	Return a 2-state integer atom type name if the width matches.
static bool	printPackedTypeImpl (Type type, raw_ostream &os, Location loc, SmallVectorImpl< Attribute > &dims, bool implicitIntType, bool singleBitDefaultType, ModuleEmitter &emitter, Type optionalAliasType={}, bool emitAsTwoStateType=false)
	Output the basic type that consists of packed and primitive types.
static Value	isZeroExtension (Value value)
	If the specified extension is a zero extended version of another value, return the shorter value, otherwise return null.
static ValueRange	getNonOverlappingConcatSubrange (Value value)
	For a value concat(..., delay(const(true), 1, 0)), return ....
template<typename PPS>
void	emitFunctionSignature (ModuleEmitter &emitter, PPS &ps, FuncOp op, bool isAutomatic=false, bool emitAsTwoStateType=false)
static bool	isExpressionEmittedInlineIntoProceduralDeclaration (Operation *op, StmtEmitter &stmtEmitter)
	Given an operation corresponding to a VerilogExpression, determine whether it is safe to emit inline into a 'localparam' or 'automatic logic' varaible initializer in a procedural region.
template<class AssignTy>
static AssignTy	getSingleAssignAndCheckUsers (Operation *op)
static bool	checkDominanceOfUsers (Operation op1, Operation op2)
	Return true if op1 dominates users of op2.
static void	emitOperation (VerilogEmitterState &state, Operation *op)
static LogicalResult	exportVerilogImpl (ModuleOp module, llvm::raw_ostream &os)
static std::unique_ptr< llvm::ToolOutputFile >	createOutputFile (StringRef fileName, StringRef dirname, SharedEmitterState &emitter)
static void	createSplitOutputFile (StringAttr fileName, FileInfo &file, StringRef dirname, SharedEmitterState &emitter)
static LogicalResult	exportSplitVerilogImpl (ModuleOp module, StringRef dirname)

Variables
StringRef	circtHeader = "circt_header.svh"
StringRef	circtHeaderInclude = "`include \"circt_header.svh\"\n"

Macro Definition Documentation

◆ DEBUG_TYPE

#define DEBUG_TYPE "export-verilog"

Definition at line 74 of file ExportVerilog.cpp.

◆ GEN_PASS_DEF_EXPORTSPLITVERILOG

#define GEN_PASS_DEF_EXPORTSPLITVERILOG

Definition at line 61 of file ExportVerilog.cpp.

◆ GEN_PASS_DEF_EXPORTVERILOG

#define GEN_PASS_DEF_EXPORTVERILOG

Definition at line 62 of file ExportVerilog.cpp.

Enumeration Type Documentation

◆ BlockStatementCount

enum class BlockStatementCount

strong

Enumerator
Zero
One
TwoOrMore

Definition at line 844 of file ExportVerilog.cpp.

Function Documentation

◆ checkDominanceOfUsers()

bool checkDominanceOfUsers	(	Operation *	op1,
		Operation *	op2 )

static

Return true if op1 dominates users of op2.

TODO: Use MLIR DominanceInfo.

Definition at line 6279 of file ExportVerilog.cpp.

◆ collectAndUniqueLocations()

void collectAndUniqueLocations	(	Location	loc,
		SmallPtrSetImpl< Attribute > &	locationSet )

static

Pull apart any fused locations into the location set, such that they are uniqued.

Any other location type will be added as-is.

Definition at line 481 of file ExportVerilog.cpp.

References collectAndUniqueLocations().

Referenced by collectAndUniqueLocations(), LocationEmitter::Impl::emitLocationInfo(), and LocationEmitter::LocationEmitter().

◆ compareLocs()

int compareLocs	(	Location	lhs,
		Location	rhs )

static

Definition at line 453 of file ExportVerilog.cpp.

References dispatchCompareLocations().

Referenced by compareLocsImpl(), and compareLocsImpl().

◆ compareLocsImpl() [1/3]

int compareLocsImpl	(	mlir::CallSiteLoc	lhs,
		mlir::CallSiteLoc	rhs )

static

Definition at line 414 of file ExportVerilog.cpp.

References compareLocs().

◆ compareLocsImpl() [2/3]

int compareLocsImpl	(	mlir::FileLineColLoc	lhs,
		mlir::FileLineColLoc	rhs )

static

Definition at line 405 of file ExportVerilog.cpp.

◆ compareLocsImpl() [3/3]

int compareLocsImpl	(	mlir::NameLoc	lhs,
		mlir::NameLoc	rhs )

static

Definition at line 398 of file ExportVerilog.cpp.

References compareLocs().

Referenced by dispatchCompareLocations().

◆ countStatements()

BlockStatementCount countStatements ( Block & block )

static

Compute how many statements are within this block, for begin/end markers.

Definition at line 847 of file ExportVerilog.cpp.

References circt::ExportVerilog::isVerilogExpression(), One, TwoOrMore, and Zero.

◆ createOutputFile()

std::unique_ptr< llvm::ToolOutputFile > createOutputFile	(	StringRef	fileName,
		StringRef	dirname,
		SharedEmitterState &	emitter )

static

Definition at line 7661 of file ExportVerilog.cpp.

References circt::appendPossiblyAbsolutePath(), circt::ExportVerilog::SharedEmitterState::designOp, and circt::ExportVerilog::SharedEmitterState::encounteredError.

◆ createSplitOutputFile()

void createSplitOutputFile	(	StringAttr	fileName,
		FileInfo &	file,
		StringRef	dirname,
		SharedEmitterState &	emitter )

static

Definition at line 7687 of file ExportVerilog.cpp.

References circt::ExportVerilog::SharedEmitterState::collectOpsForFile(), circt::createOutputFile(), circt::ExportVerilog::SharedEmitterState::emitOps(), circt::LoweringOptions::emitReplicatedOpsToHeader, and circt::ExportVerilog::SharedEmitterState::options.

◆ dispatchCompareLocations()

template<typename TTargetLoc>

FailureOr< int > dispatchCompareLocations	(	Location	lhs,
		Location	rhs )

Definition at line 426 of file ExportVerilog.cpp.

References compareLocsImpl(), and failure().

Referenced by compareLocs().

◆ emitDim()

void emitDim	(	Attribute	width,
		raw_ostream &	os,
		Location	loc,
		ModuleEmitter &	emitter,
		bool	downTo )

static

Emit a single dimension.

Definition at line 1672 of file ExportVerilog.cpp.

References getIntAttr().

Referenced by emitDims().

◆ emitDims()

void emitDims	(	ArrayRef< Attribute >	dims,
		raw_ostream &	os,
		Location	loc,
		ModuleEmitter &	emitter )

static

Emit a list of packed dimensions.

Definition at line 1716 of file ExportVerilog.cpp.

References emitDim().

◆ emitFunctionSignature()

template<typename PPS>

void emitFunctionSignature	(	ModuleEmitter &	emitter,
		PPS &	ps,
		FuncOp	op,
		bool	isAutomatic = false,
		bool	emitAsTwoStateType = false )

Definition at line 4759 of file ExportVerilog.cpp.

References circt::ExportVerilog::getSymOpName().

◆ emitOperation()

void emitOperation	(	VerilogEmitterState &	state,
		Operation *	op )

static

Definition at line 7426 of file ExportVerilog.cpp.

References FileEmitter::emit().

Referenced by circt::ExportVerilog::SharedEmitterState::emitOps().

◆ emitSVAttributesImpl()

template<typename PPS>

void emitSVAttributesImpl	(	PPS &	ps,
		ArrayAttr	attrs,
		bool	mayBreak )

static

Emit SystemVerilog attributes.

Definition at line 946 of file ExportVerilog.cpp.

References assert(), and attrs.

◆ emitZeroWidthIndexingValue()

template<typename PPS>

void emitZeroWidthIndexingValue ( PPS & os )

static

Emits a known-safe token that is legal when indexing into singleton arrays.

Definition at line 231 of file ExportVerilog.cpp.

◆ exportSplitVerilogImpl()

LogicalResult exportSplitVerilogImpl	(	ModuleOp	module,
		StringRef	dirname )

static

Definition at line 7709 of file ExportVerilog.cpp.

References circtHeader, circt::createOutputFile(), circt::LoweringOptions::emitReplicatedOpsToHeader, circt::ExportVerilog::SharedEmitterState::encounteredError, failure(), circt::ExportVerilog::SharedEmitterState::fileLists, circt::ExportVerilog::SharedEmitterState::files, circt::ExportVerilog::SharedEmitterState::gatherFiles(), circt::ExportVerilog::legalizeGlobalNames(), and circt::ExportVerilog::SharedEmitterState::options.

◆ exportVerilogImpl()

LogicalResult exportVerilogImpl	(	ModuleOp	module,
		llvm::raw_ostream &	os )

static

Definition at line 7554 of file ExportVerilog.cpp.

◆ findNestedElseIf()

IfOp findNestedElseIf ( Block * elseBlock )

static

Find a nested IfOp in an else block that can be printed as else if instead of nesting it into a new begin - end block.

The block must contain a single IfOp and optionally expressions which can be hoisted out.

Definition at line 925 of file ExportVerilog.cpp.

References hasSVAttributes(), and circt::ExportVerilog::isVerilogExpression().

◆ getInputPortVerilogName()

StringRef getInputPortVerilogName	(	Operation *	module,
		size_t	portArgNum )

static

Return the verilog name of the port for the module.

Definition at line 242 of file ExportVerilog.cpp.

References attrs.

Referenced by getVerilogValueName().

◆ getInt32Attr()

TypedAttr getInt32Attr	(	MLIRContext *	ctx,
		uint32_t	value )

static

Definition at line 124 of file ExportVerilog.cpp.

Referenced by getTypeDims().

◆ getIntAttr()

TypedAttr getIntAttr	(	MLIRContext *	ctx,
		Type	t,
		const APInt &	value )

static

Definition at line 128 of file ExportVerilog.cpp.

Referenced by emitDim(), and foldMod().

◆ getNonOverlappingConcatSubrange()

ValueRange getNonOverlappingConcatSubrange ( Value value )

static

For a value concat(..., delay(const(true), 1, 0)), return ....

This is useful for emitting (seq ##1 true) |-> prop as seq |=> prop.

Definition at line 4034 of file ExportVerilog.cpp.

◆ getPortVerilogName()

StringRef getPortVerilogName	(	Operation *	module,
		size_t	portArgNum )

static

Return the verilog name of the port for the module.

Definition at line 236 of file ExportVerilog.cpp.

Referenced by circt::ExportVerilog::inferStructuralNameForTemporary().

◆ getSingleAssignAndCheckUsers()

template<class AssignTy>

AssignTy getSingleAssignAndCheckUsers ( Operation * op )

static

Definition at line 6259 of file ExportVerilog.cpp.

◆ getTwoStateIntegerAtomType()

StringRef getTwoStateIntegerAtomType ( size_t width )

static

Return a 2-state integer atom type name if the width matches.

See Spec 6.8 Variable declarations.

Definition at line 1733 of file ExportVerilog.cpp.

◆ getTypeDims()

void getTypeDims	(	SmallVectorImpl< Attribute > &	dims,
		Type	type,
		Location	loc,
		llvm::function_ref< mlir::InFlightDiagnostic(Location)>	errorHandler )

static

Push this type's dimension into a vector.

Definition at line 275 of file ExportVerilog.cpp.

References getInt32Attr(), and getTypeDims().

Referenced by getTypeDims(), and haveMatchingDims().

◆ getVerilogDeclWord()

StringRef getVerilogDeclWord	(	Operation *	op,
		const ModuleEmitter &	emitter )

static

Return the word (e.g.

"reg") in Verilog to declare the specified thing. If stripAutomatic is true, "automatic" is not used even for a declaration in a non-procedural region.

Definition at line 1582 of file ExportVerilog.cpp.

References assert(), elementType, hasExplicitDataType(), hasStructType(), circt::LoweringOptions::Logic, circt::LoweringOptions::Reg, and circt::LoweringOptions::VarLogic.

◆ getVerilogValueName()

StringRef getVerilogValueName ( Value val )

Retrieve value's verilog name from IR.

The name must already have been added in pre-pass and passed through "hw.verilogName" attr.

Definition at line 1001 of file ExportVerilog.cpp.

References assert(), getInputPortVerilogName(), and circt::ExportVerilog::getSymOpName().

◆ hasExplicitDataType()

bool hasExplicitDataType ( Type type )

static

Returns true if type prints its own SystemVerilog data_type, so its declaration must not be prefixed with logic or reg.

Integer types are the exception: they print only a packed range like [3:0], so the declaration must supply logic or reg. Packed and unpacked arrays inherit this property from their elememt type. See SV Spec 6.8.

Definition at line 1571 of file ExportVerilog.cpp.

References hasExplicitDataType().

Referenced by getVerilogDeclWord(), and hasExplicitDataType().

◆ hasLeadingUnpackedType()

bool hasLeadingUnpackedType ( Type type )

static

Return true if the type has a leading unpacked type.

Definition at line 369 of file ExportVerilog.cpp.

References assert(), elementType, and stripUnpackedTypes().

◆ hasStructType()

bool hasStructType ( Type type )

static

Return true if the element type is emitted as a type name or a keyword (struct, union, enum or typedef), so that no "logic" prefix is allowed.

Definition at line 377 of file ExportVerilog.cpp.

References hasStructType().

Referenced by getVerilogDeclWord(), and hasStructType().

◆ haveMatchingDims()

bool haveMatchingDims	(	Type	a,
		Type	b,
		Location	loc,
		llvm::function_ref< mlir::InFlightDiagnostic(Location)>	errorHandler )

static

True iff 'a' and 'b' have the same wire dims.

Definition at line 312 of file ExportVerilog.cpp.

References getTypeDims().

Referenced by isExpressionUnableToInline().

◆ isDuplicatableExpression()

bool isDuplicatableExpression ( Operation * op )

static

Definition at line 165 of file ExportVerilog.cpp.

References isDuplicatableNullaryExpression().

Referenced by circt::ExportVerilog::isExpressionEmittedInline().

◆ isDuplicatableNullaryExpression()

bool isDuplicatableNullaryExpression ( Operation * op )

static

Return true for nullary operations that are better emitted multiple times as inline expression (when they have multiple uses) rather than having a temporary wire.

This can only handle nullary expressions, because we don't want to replicate subtrees arbitrarily.

Definition at line 138 of file ExportVerilog.cpp.

References circt::ExportVerilog::isConstantExpression().

Referenced by isDuplicatableExpression().

◆ isExpressionEmittedInlineIntoProceduralDeclaration()

bool isExpressionEmittedInlineIntoProceduralDeclaration	(	Operation *	op,
		StmtEmitter &	stmtEmitter )

static

Given an operation corresponding to a VerilogExpression, determine whether it is safe to emit inline into a 'localparam' or 'automatic logic' varaible initializer in a procedural region.

We can't emit exprs inline when they refer to something else that can't be emitted inline, when they're in a general #ifdef region,

Definition at line 6177 of file ExportVerilog.cpp.

References circt::ExportVerilog::isExpressionEmittedInline(), and circt::ExportVerilog::isVerilogExpression().

◆ isExpressionUnableToInline()

bool isExpressionUnableToInline	(	Operation *	op,
		const LoweringOptions &	options )

static

Return true if we are unable to ever inline the specified operation.

This happens because not all Verilog expressions are composable, notably you can only use bit selects like x[4:6] on simple expressions, you cannot use expressions in the sensitivity list of always blocks, etc.

Definition at line 752 of file ExportVerilog.cpp.

References circt::LoweringOptions::allowExprInEventControl, haveMatchingDims(), and isOkToBitSelectFrom().

Referenced by circt::ExportVerilog::isExpressionEmittedInline().

◆ isOkToBitSelectFrom()

bool isOkToBitSelectFrom ( Value v )

static

Most expressions are invalid to bit-select from in Verilog, but some things are ok.

Return true if it is ok to inline bitselect from the result of this expression. It is conservatively correct to return false.

Definition at line 725 of file ExportVerilog.cpp.

Referenced by isExpressionUnableToInline().

◆ isZeroExtension()

Value isZeroExtension ( Value value )

static

If the specified extension is a zero extended version of another value, return the shorter value, otherwise return null.

Definition at line 2673 of file ExportVerilog.cpp.

References concat().

◆ printPackedTypeImpl()

bool printPackedTypeImpl	(	Type	type,
		raw_ostream &	os,
		Location	loc,
		SmallVectorImpl< Attribute > &	dims,
		bool	implicitIntType,
		bool	singleBitDefaultType,
		ModuleEmitter &	emitter,
		Type	optionalAliasType = {},
		bool	emitAsTwoStateType = false )

static

Output the basic type that consists of packed and primitive types.

This is those to the left of the name in verilog. implicitIntType controls whether to print a base type for (logic) for inteters or whether the caller will have handled this (with logic, wire, reg, etc). optionalAliasType can be provided to perform any necessary alias-aware printing of 'type'.

Returns true when anything was printed out.

Definition at line 1757 of file ExportVerilog.cpp.

◆ sortLocationVector()

template<typename TVector>

void sortLocationVector ( TVector & vec )

static

Definition at line 493 of file ExportVerilog.cpp.

Referenced by LocationEmitter::Impl::emitLocationSetInfoImpl().

◆ stripUnpackedTypes()

Type stripUnpackedTypes ( Type type )

static

Given a set of known nested types (those supported by this pass), strip off leading unpacked types.

This strips off portions of the type that are printed to the right of the name in verilog.

Definition at line 357 of file ExportVerilog.cpp.

References stripUnpackedTypes().

Referenced by hasLeadingUnpackedType(), and stripUnpackedTypes().

Variable Documentation

◆ circtHeader

StringRef circtHeader = "circt_header.svh"

Definition at line 76 of file ExportVerilog.cpp.

Referenced by exportSplitVerilogImpl().

◆ circtHeaderInclude

StringRef circtHeaderInclude = "`include \"circt_header.svh\"\n"

Definition at line 77 of file ExportVerilog.cpp.

Referenced by circt::ExportVerilog::SharedEmitterState::collectOpsForFile().

Classes

Namespaces

Macros

Enumerations

Functions

Variables

Macro Definition Documentation

◆ DEBUG_TYPE

◆ GEN_PASS_DEF_EXPORTSPLITVERILOG

◆ GEN_PASS_DEF_EXPORTVERILOG

Enumeration Type Documentation

◆ BlockStatementCount

Function Documentation

◆ checkDominanceOfUsers()

◆ collectAndUniqueLocations()

◆ compareLocs()

◆ compareLocsImpl() [1/3]

◆ compareLocsImpl() [2/3]

◆ compareLocsImpl() [3/3]

◆ countStatements()

◆ createOutputFile()

◆ createSplitOutputFile()

◆ dispatchCompareLocations()

◆ emitDim()

◆ emitDims()

◆ emitFunctionSignature()

◆ emitOperation()

◆ emitSVAttributesImpl()

◆ emitZeroWidthIndexingValue()

◆ exportSplitVerilogImpl()

◆ exportVerilogImpl()

◆ findNestedElseIf()

◆ getInputPortVerilogName()

◆ getInt32Attr()

◆ getIntAttr()

◆ getNonOverlappingConcatSubrange()

◆ getPortVerilogName()

◆ getSingleAssignAndCheckUsers()

◆ getTwoStateIntegerAtomType()

◆ getTypeDims()

◆ getVerilogDeclWord()

◆ getVerilogValueName()

◆ hasExplicitDataType()

◆ hasLeadingUnpackedType()

◆ hasStructType()

◆ haveMatchingDims()

◆ isDuplicatableExpression()

◆ isDuplicatableNullaryExpression()

◆ isExpressionEmittedInlineIntoProceduralDeclaration()

◆ isExpressionUnableToInline()

◆ isOkToBitSelectFrom()

◆ isZeroExtension()

◆ printPackedTypeImpl()

◆ sortLocationVector()

◆ stripUnpackedTypes()

Variable Documentation

◆ circtHeader

◆ circtHeaderInclude