21#include "mlir/IR/Builders.h"
22#include "mlir/Pass/Pass.h"
23#include "llvm/Support/Debug.h"
25#define DEBUG_TYPE "synth-generic-lut-mapper"
32#define GEN_PASS_DEF_GENERICLUTMAPPER
33#include "circt/Dialect/Synth/Transforms/SynthPasses.h.inc"
51 const Cut &cut)
const override {
62 llvm::FailureOr<Operation *>
rewrite(mlir::OpBuilder &rewriter,
64 const Cut &cut)
const override {
70 const auto &truthTable = *truthTableOpt;
72 llvm::dbgs() <<
"Rewriting cut with " << cut.
getInputSize()
74 <<
" operations to a generic LUT with " <<
k <<
" inputs.\n";
75 cut.
dump(llvm::dbgs(), network);
76 llvm::dbgs() <<
"Truth table details:\n";
77 truthTable.dump(llvm::dbgs());
80 SmallVector<bool> lutTable;
82 for (uint32_t i = 0; i < truthTable.table.getBitWidth(); ++i)
83 lutTable.push_back(truthTable.table[i]);
86 SmallVector<Value> lutInputs;
87 lutInputs.reserve(cut.
inputs.size());
88 for (
auto i : llvm::reverse(cut.
inputs))
89 lutInputs.push_back(network.getValue(i));
91 auto *rootOp = network.getGate(cut.
getRootIndex()).getOperation();
92 assert(rootOp &&
"cut root must be a valid operation");
95 auto truthTableOp = comb::TruthTableOp::create(rewriter, rootOp->getLoc(),
99 return truthTableOp.getOperation();
112 :
public impl::GenericLutMapperBase<GenericLUTMapperPass> {
116 auto module = getOperation();
126 SmallVector<std::unique_ptr<CutRewritePattern>, 4>
patterns;
128 std::make_unique<GenericLUT>(module->getContext(), maxLutSize));
137 if (failed(rewriter.
run(module)))
138 return signalPassFailure();
assert(baseType &&"element must be base type")
Cut enumeration engine for combinational logic networks.
const LogicNetwork & getLogicNetwork() const
Get the logic network (read-only).
Manages a collection of rewriting patterns for combinational logic optimization.
Main cut-based rewriting algorithm for combinational logic optimization.
LogicalResult run(Operation *topOp)
Execute the complete cut-based rewriting algorithm.
Represents a cut in the combinational logic network.
void dump(llvm::raw_ostream &os, const LogicNetwork &network) const
unsigned getOutputSize(const LogicNetwork &network) const
Get the number of outputs from root operation.
const std::optional< BinaryTruthTable > & getTruthTable() const
Get the truth table for this cut.
uint32_t getRootIndex() const
Get the root index in the LogicNetwork.
llvm::SmallVector< uint32_t, 6 > inputs
External inputs to this cut (cut boundary).
unsigned getInputSize() const
Get the number of inputs to this cut.
The InstanceGraph op interface, see InstanceGraphInterface.td for more details.
void runOnOperation() override
A generic K-input LUT pattern that can implement any boolean function with up to K inputs using a loo...
std::optional< MatchResult > match(CutEnumerator &enumerator, const Cut &cut) const override
Check if a cut matches this pattern and compute area/delay metrics.
unsigned getNumOutputs() const override
Get the number of outputs this pattern produces.
SmallVector< DelayType, 8 > cachedDelays
StringRef getPatternName() const override
Get the name of this pattern. Used for debugging.
llvm::FailureOr< Operation * > rewrite(mlir::OpBuilder &rewriter, CutEnumerator &enumerator, const Cut &cut) const override
Return a new operation that replaces the matched cut.
GenericLUT(mlir::MLIRContext *context, unsigned k)
Base class for cut rewriting patterns used in combinational logic optimization.
mlir::MLIRContext * context
Configuration options for the cut-based rewriting algorithm.
unsigned maxCutInputSize
Maximum number of inputs allowed for any cut.
unsigned maxCutSizePerRoot
Maximum number of cuts to maintain per logic node.
bool allowNoMatch
Fail if there is a root operation that has no matching pattern.
bool attachDebugTiming
Put arrival times to rewritten operations.
OptimizationStrategy strategy
Optimization strategy (area vs. timing).
Result of matching a cut against a pattern.