19#include "mlir/Conversion/LLVMCommon/ConversionTarget.h"
20#include "mlir/Conversion/LLVMCommon/Pattern.h"
21#include "mlir/Dialect/Arith/IR/Arith.h"
22#include "mlir/Dialect/ControlFlow/IR/ControlFlowOps.h"
23#include "mlir/Dialect/Func/IR/FuncOps.h"
24#include "mlir/Dialect/Math/IR/Math.h"
25#include "mlir/Dialect/MemRef/IR/MemRef.h"
26#include "mlir/Dialect/SCF/IR/SCF.h"
27#include "mlir/IR/AsmState.h"
28#include "mlir/IR/Matchers.h"
29#include "mlir/Pass/Pass.h"
30#include "mlir/Support/LogicalResult.h"
31#include "mlir/Transforms/GreedyPatternRewriteDriver.h"
32#include "llvm/ADT/TypeSwitch.h"
33#include "llvm/Support/LogicalResult.h"
34#include "llvm/Support/raw_os_ostream.h"
35#include "llvm/Support/raw_ostream.h"
45#define GEN_PASS_DEF_SCFTOCALYX
46#include "circt/Conversion/Passes.h.inc"
51using namespace mlir::arith;
52using namespace mlir::cf;
55class ComponentLoweringStateInterface;
83 std::optional<int64_t>
getBound()
override {
return std::nullopt; }
145 Operation *operation = op.getOperation();
146 auto [it, succeeded] =
condReg.insert(std::make_pair(operation, regOp));
148 "A condition register was already set for this scf::IfOp!");
152 auto it =
condReg.find(op.getOperation());
159 Operation *operation = op.getOperation();
161 "A then group was already set for this scf::IfOp!\n");
166 auto it =
thenGroup.find(op.getOperation());
168 "No then group was set for this scf::IfOp!\n");
173 Operation *operation = op.getOperation();
175 "An else group was already set for this scf::IfOp!\n");
180 auto it =
elseGroup.find(op.getOperation());
182 "No else group was set for this scf::IfOp!\n");
188 "A register was already registered for the given yield result.\n");
189 assert(idx < op->getNumOperands());
199 auto it = regs.find(idx);
200 assert(it != regs.end() &&
"resultReg not found");
206 DenseMap<Operation *, calyx::RegisterOp>
condReg;
209 DenseMap<Operation *, DenseMap<unsigned, calyx::RegisterOp>>
resultRegs;
219 OpBuilder &builder,
ScfWhileOp op, calyx::ComponentOp componentOp,
220 Twine uniqueSuffix, MutableArrayRef<OpOperand> ops) {
227 const DenseMap<unsigned, calyx::RegisterOp> &
238 SmallVector<calyx::GroupOp> groups) {
250 OpBuilder &builder,
ScfForOp op, calyx::ComponentOp componentOp,
251 Twine uniqueSuffix, MutableArrayRef<OpOperand> ops) {
280 auto cellOp = dyn_cast<calyx::CellInterface>(op);
281 assert(cellOp && !cellOp.isCombinational());
282 auto [it, succeeded] =
resultRegs.insert(std::make_pair(op, reg));
284 "A register was already set for this sequential operation!");
290 "No register was set for this sequential operation!");
324 DenseMap<mlir::func::FuncOp, calyx::ComponentOp> &map,
326 mlir::Pass::Option<std::string> &writeJsonOpt)
329 using FuncOpPartialLoweringPattern::FuncOpPartialLoweringPattern;
333 PatternRewriter &rewriter)
const override {
336 bool opBuiltSuccessfully =
true;
337 funcOp.walk([&](Operation *_op) {
338 opBuiltSuccessfully &=
339 TypeSwitch<mlir::Operation *, bool>(_op)
340 .template Case<arith::ConstantOp, ReturnOp, BranchOpInterface,
342 scf::YieldOp, scf::WhileOp, scf::ForOp, scf::IfOp,
343 scf::ParallelOp, scf::ReduceOp,
344 scf::ExecuteRegionOp,
346 memref::AllocOp, memref::AllocaOp, memref::LoadOp,
347 memref::StoreOp, memref::GetGlobalOp,
349 AddIOp, SubIOp, CmpIOp, ShLIOp, ShRUIOp, ShRSIOp,
350 AndIOp, XOrIOp, OrIOp, ExtUIOp, ExtSIOp, TruncIOp,
351 MulIOp, DivUIOp, DivSIOp, RemUIOp, RemSIOp,
353 AddFOp, SubFOp, MulFOp, CmpFOp, FPToSIOp, SIToFPOp,
354 DivFOp, math::SqrtOp,
356 SelectOp, IndexCastOp, BitcastOp, CallOp>(
357 [&](
auto op) {
return buildOp(rewriter, op).succeeded(); })
358 .
template Case<FuncOp, scf::ConditionOp>([&](
auto) {
362 .Default([&](
auto op) {
363 op->emitError() <<
"Unhandled operation during BuildOpGroups()";
367 return opBuiltSuccessfully ? WalkResult::advance()
368 : WalkResult::interrupt();
372 auto &extMemData = getState<ComponentLoweringState>().getExtMemData();
373 if (extMemData.getAsObject()->empty())
376 if (
auto fileLoc = dyn_cast<mlir::FileLineColLoc>(funcOp->getLoc())) {
377 std::string filename = fileLoc.getFilename().str();
378 std::filesystem::path path(filename);
379 std::string jsonFileName =
writeJson.getValue() +
".json";
380 auto outFileName = path.parent_path().append(jsonFileName);
381 std::ofstream outFile(outFileName);
383 if (!outFile.is_open()) {
384 llvm::errs() <<
"Unable to open file: " << outFileName.string()
388 llvm::raw_os_ostream llvmOut(outFile);
389 llvm::json::OStream jsonOS(llvmOut, 2);
390 jsonOS.value(extMemData);
396 return success(opBuiltSuccessfully);
402 LogicalResult
buildOp(PatternRewriter &rewriter, scf::YieldOp yieldOp)
const;
403 LogicalResult
buildOp(PatternRewriter &rewriter,
404 BranchOpInterface brOp)
const;
405 LogicalResult
buildOp(PatternRewriter &rewriter,
406 arith::ConstantOp constOp)
const;
407 LogicalResult
buildOp(PatternRewriter &rewriter, SelectOp op)
const;
408 LogicalResult
buildOp(PatternRewriter &rewriter, AddIOp op)
const;
409 LogicalResult
buildOp(PatternRewriter &rewriter, SubIOp op)
const;
410 LogicalResult
buildOp(PatternRewriter &rewriter, MulIOp op)
const;
411 LogicalResult
buildOp(PatternRewriter &rewriter, DivUIOp op)
const;
412 LogicalResult
buildOp(PatternRewriter &rewriter, DivSIOp op)
const;
413 LogicalResult
buildOp(PatternRewriter &rewriter, RemUIOp op)
const;
414 LogicalResult
buildOp(PatternRewriter &rewriter, RemSIOp op)
const;
415 LogicalResult
buildOp(PatternRewriter &rewriter, AddFOp op)
const;
416 LogicalResult
buildOp(PatternRewriter &rewriter, SubFOp op)
const;
417 LogicalResult
buildOp(PatternRewriter &rewriter, MulFOp op)
const;
418 LogicalResult
buildOp(PatternRewriter &rewriter, CmpFOp op)
const;
419 LogicalResult
buildOp(PatternRewriter &rewriter, FPToSIOp op)
const;
420 LogicalResult
buildOp(PatternRewriter &rewriter, SIToFPOp op)
const;
421 LogicalResult
buildOp(PatternRewriter &rewriter, DivFOp op)
const;
422 LogicalResult
buildOp(PatternRewriter &rewriter, math::SqrtOp op)
const;
423 LogicalResult
buildOp(PatternRewriter &rewriter, ShRUIOp op)
const;
424 LogicalResult
buildOp(PatternRewriter &rewriter, ShRSIOp op)
const;
425 LogicalResult
buildOp(PatternRewriter &rewriter, ShLIOp op)
const;
426 LogicalResult
buildOp(PatternRewriter &rewriter, AndIOp op)
const;
427 LogicalResult
buildOp(PatternRewriter &rewriter, OrIOp op)
const;
428 LogicalResult
buildOp(PatternRewriter &rewriter, XOrIOp op)
const;
429 LogicalResult
buildOp(PatternRewriter &rewriter, CmpIOp op)
const;
430 LogicalResult
buildOp(PatternRewriter &rewriter, TruncIOp op)
const;
431 LogicalResult
buildOp(PatternRewriter &rewriter, ExtUIOp op)
const;
432 LogicalResult
buildOp(PatternRewriter &rewriter, ExtSIOp op)
const;
433 LogicalResult
buildOp(PatternRewriter &rewriter, ReturnOp op)
const;
434 LogicalResult
buildOp(PatternRewriter &rewriter, IndexCastOp op)
const;
435 LogicalResult
buildOp(PatternRewriter &rewriter, BitcastOp op)
const;
436 LogicalResult
buildOp(PatternRewriter &rewriter, memref::AllocOp op)
const;
437 LogicalResult
buildOp(PatternRewriter &rewriter, memref::AllocaOp op)
const;
438 LogicalResult
buildOp(PatternRewriter &rewriter,
439 memref::GetGlobalOp op)
const;
440 LogicalResult
buildOp(PatternRewriter &rewriter, memref::LoadOp op)
const;
441 LogicalResult
buildOp(PatternRewriter &rewriter, memref::StoreOp op)
const;
442 LogicalResult
buildOp(PatternRewriter &rewriter, scf::WhileOp whileOp)
const;
443 LogicalResult
buildOp(PatternRewriter &rewriter, scf::ForOp forOp)
const;
444 LogicalResult
buildOp(PatternRewriter &rewriter, scf::IfOp ifOp)
const;
445 LogicalResult
buildOp(PatternRewriter &rewriter,
446 scf::ReduceOp reduceOp)
const;
447 LogicalResult
buildOp(PatternRewriter &rewriter,
448 scf::ParallelOp parallelOp)
const;
449 LogicalResult
buildOp(PatternRewriter &rewriter,
450 scf::ExecuteRegionOp executeRegionOp)
const;
451 LogicalResult
buildOp(PatternRewriter &rewriter, CallOp callOp)
const;
456 template <
typename TCalyxLibOp>
457 void setupCmpIOp(PatternRewriter &rewriter, CmpIOp cmpIOp, Operation *group,
458 calyx::RegisterOp &condReg, calyx::RegisterOp &resReg,
459 TCalyxLibOp calyxOp)
const {
463 StringRef opName = cmpIOp.getOperationName().split(
".").second;
464 Type width = cmpIOp.getResult().getType();
466 condReg = createRegister(
468 width.getIntOrFloatBitWidth(),
469 getState<ComponentLoweringState>().getUniqueName(opName));
471 for (
auto *user : cmpIOp->getUsers()) {
472 if (
auto ifOp = dyn_cast<scf::IfOp>(user))
473 getState<ComponentLoweringState>().setCondReg(ifOp, condReg);
477 lhsIsSeqOp != rhsIsSeqOp &&
478 "unexpected sequential operation on both sides; please open an issue");
482 cast<calyx::RegisterOp>(lhsIsSeqOp ? cmpIOp.getLhs().getDefiningOp()
483 : cmpIOp.getRhs().getDefiningOp());
485 auto groupOp = cast<calyx::GroupOp>(group);
486 getState<ComponentLoweringState>().addBlockScheduleable(cmpIOp->getBlock(),
489 rewriter.setInsertionPointToEnd(groupOp.getBodyBlock());
490 auto loc = cmpIOp.getLoc();
492 (isa<calyx::EqLibOp, calyx::NeqLibOp, calyx::SleLibOp, calyx::SltLibOp,
493 calyx::LeLibOp, calyx::LtLibOp, calyx::GeLibOp, calyx::GtLibOp,
494 calyx::SgeLibOp, calyx::SgtLibOp>(calyxOp.getOperation())) &&
495 "Must be a Calyx comparison library operation.");
496 int64_t outputIndex = 2;
497 rewriter.create<calyx::AssignOp>(loc, condReg.getIn(),
498 calyxOp.getResult(outputIndex));
499 rewriter.create<calyx::AssignOp>(
500 loc, condReg.getWriteEn(),
501 createConstant(loc, rewriter,
502 getState<ComponentLoweringState>().getComponentOp(), 1,
504 rewriter.create<calyx::GroupDoneOp>(loc, condReg.getDone());
506 getState<ComponentLoweringState>().addSeqGuardCmpLibOp(cmpIOp);
457 void setupCmpIOp(PatternRewriter &rewriter, CmpIOp cmpIOp, Operation *group, {
…}
509 template <
typename CmpILibOp>
511 bool isIfOpGuard = std::any_of(op->getUsers().begin(), op->getUsers().end(),
512 [](
auto op) { return isa<scf::IfOp>(op); });
517 return buildLibraryOp<calyx::GroupOp, CmpILibOp>(rewriter, op);
518 return buildLibraryOp<calyx::CombGroupOp, CmpILibOp>(rewriter, op);
523 template <
typename TGroupOp,
typename TCalyxLibOp,
typename TSrcOp>
525 TypeRange srcTypes, TypeRange dstTypes)
const {
526 SmallVector<Type> types;
527 for (Type srcType : srcTypes)
529 for (Type dstType : dstTypes)
533 getState<ComponentLoweringState>().getNewLibraryOpInstance<TCalyxLibOp>(
534 rewriter, op.getLoc(), types);
536 auto directions = calyxOp.portDirections();
537 SmallVector<Value, 4> opInputPorts;
538 SmallVector<Value, 4> opOutputPorts;
539 for (
auto dir : enumerate(directions)) {
541 opInputPorts.push_back(calyxOp.getResult(dir.index()));
543 opOutputPorts.push_back(calyxOp.getResult(dir.index()));
546 opInputPorts.size() == op->getNumOperands() &&
547 opOutputPorts.size() == op->getNumResults() &&
548 "Expected an equal number of in/out ports in the Calyx library op with "
549 "respect to the number of operands/results of the source operation.");
552 auto group = createGroupForOp<TGroupOp>(rewriter, op);
554 bool isSeqCondCheck = isa<calyx::GroupOp>(group);
555 calyx::RegisterOp condReg =
nullptr, resReg =
nullptr;
556 if (isa<CmpIOp>(op) && isSeqCondCheck) {
557 auto cmpIOp = cast<CmpIOp>(op);
558 setupCmpIOp(rewriter, cmpIOp, group, condReg, resReg, calyxOp);
561 rewriter.setInsertionPointToEnd(group.getBodyBlock());
563 for (
auto dstOp : enumerate(opInputPorts)) {
566 : op->getOperand(dstOp.index());
567 rewriter.create<calyx::AssignOp>(op.getLoc(), dstOp.value(), srcOp);
571 for (
auto res : enumerate(opOutputPorts)) {
572 getState<ComponentLoweringState>().registerEvaluatingGroup(res.value(),
574 auto dstOp = isSeqCondCheck ? condReg.getOut() : res.value();
575 op->getResult(res.index()).replaceAllUsesWith(dstOp);
583 template <
typename TGroupOp,
typename TCalyxLibOp,
typename TSrcOp>
585 return buildLibraryOp<TGroupOp, TCalyxLibOp, TSrcOp>(
586 rewriter, op, op.getOperandTypes(), op->getResultTypes());
590 template <
typename TGroupOp>
592 Block *block = op->getBlock();
593 auto groupName = getState<ComponentLoweringState>().getUniqueName(
595 return calyx::createGroup<TGroupOp>(
596 rewriter, getState<ComponentLoweringState>().getComponentOp(),
597 op->getLoc(), groupName);
602 template <
typename TOpType,
typename TSrcOp>
604 TOpType opPipe, Value out)
const {
605 StringRef opName = TSrcOp::getOperationName().split(
".").second;
606 Location loc = op.getLoc();
607 Type width = op.getResult().getType();
608 auto reg = createRegister(
609 op.getLoc(), rewriter,
getComponent(), width.getIntOrFloatBitWidth(),
610 getState<ComponentLoweringState>().getUniqueName(opName));
613 auto group = createGroupForOp<calyx::GroupOp>(rewriter, op);
614 OpBuilder builder(group->getRegion(0));
615 getState<ComponentLoweringState>().addBlockScheduleable(op->getBlock(),
618 rewriter.setInsertionPointToEnd(group.getBodyBlock());
619 if constexpr (std::is_same_v<TSrcOp, math::SqrtOp>)
622 rewriter.create<calyx::AssignOp>(loc, opPipe.getLeft(), op.getOperand());
624 rewriter.create<calyx::AssignOp>(loc, opPipe.getLeft(), op.getLhs());
625 rewriter.create<calyx::AssignOp>(loc, opPipe.getRight(), op.getRhs());
628 rewriter.create<calyx::AssignOp>(loc, reg.getIn(), out);
630 rewriter.create<calyx::AssignOp>(loc, reg.getWriteEn(), opPipe.getDone());
635 rewriter.create<calyx::AssignOp>(
636 loc, opPipe.getGo(), c1,
639 rewriter.create<calyx::GroupDoneOp>(loc, reg.getDone());
643 op.getResult().replaceAllUsesWith(reg.getOut());
645 if (isa<calyx::AddFOpIEEE754>(opPipe)) {
646 auto opFOp = cast<calyx::AddFOpIEEE754>(opPipe);
648 if (isa<arith::AddFOp>(op)) {
649 subOp = createConstant(loc, rewriter,
getComponent(), 1,
652 subOp = createConstant(loc, rewriter,
getComponent(), 1,
655 rewriter.create<calyx::AssignOp>(loc, opFOp.getSubOp(), subOp);
656 }
else if (
auto opFOp =
657 dyn_cast<calyx::DivSqrtOpIEEE754>(opPipe.getOperation())) {
658 bool isSqrt = !isa<arith::DivFOp>(op);
660 createConstant(loc, rewriter,
getComponent(), 1, isSqrt);
661 rewriter.create<calyx::AssignOp>(loc, opFOp.getSqrtOp(), sqrtOp);
665 getState<ComponentLoweringState>().registerEvaluatingGroup(out, group);
666 getState<ComponentLoweringState>().registerEvaluatingGroup(opPipe.getLeft(),
668 getState<ComponentLoweringState>().registerEvaluatingGroup(
669 opPipe.getRight(), group);
671 getState<ComponentLoweringState>().setSeqResReg(out.getDefiningOp(), reg);
676 template <
typename TCalyxLibOp,
typename TSrcOp>
678 unsigned inputWidth,
unsigned outputWidth,
679 StringRef signedPort)
const {
680 Location loc = op.getLoc();
681 IntegerType one = rewriter.getI1Type(),
682 inWidth = rewriter.getIntegerType(inputWidth),
683 outWidth = rewriter.getIntegerType(outputWidth);
685 getState<ComponentLoweringState>().getNewLibraryOpInstance<TCalyxLibOp>(
686 rewriter, loc, {one, one, one, inWidth, one, outWidth, one});
688 StringRef opName = op.getOperationName().split(
".").second;
690 auto reg = createRegister(
691 loc, rewriter,
getComponent(), outWidth.getIntOrFloatBitWidth(),
692 getState<ComponentLoweringState>().getUniqueName(opName));
694 auto group = createGroupForOp<calyx::GroupOp>(rewriter, op);
695 OpBuilder builder(group->getRegion(0));
696 getState<ComponentLoweringState>().addBlockScheduleable(op->getBlock(),
699 rewriter.setInsertionPointToEnd(group.getBodyBlock());
700 rewriter.create<calyx::AssignOp>(loc, calyxOp.getIn(), op.getIn());
701 if (isa<calyx::FpToIntOpIEEE754>(calyxOp)) {
702 rewriter.create<calyx::AssignOp>(
703 loc, cast<calyx::FpToIntOpIEEE754>(calyxOp).getSignedOut(), c1);
704 }
else if (isa<calyx::IntToFpOpIEEE754>(calyxOp)) {
705 rewriter.create<calyx::AssignOp>(
706 loc, cast<calyx::IntToFpOpIEEE754>(calyxOp).getSignedIn(), c1);
708 op.getResult().replaceAllUsesWith(reg.getOut());
710 rewriter.create<calyx::AssignOp>(loc, reg.getIn(), calyxOp.getOut());
711 rewriter.create<calyx::AssignOp>(loc, reg.getWriteEn(), c1);
713 rewriter.create<calyx::AssignOp>(
714 loc, calyxOp.getGo(), c1,
716 rewriter.create<calyx::GroupDoneOp>(loc, reg.getDone());
724 calyx::GroupInterface group,
726 Operation::operand_range addressValues)
const {
727 IRRewriter::InsertionGuard guard(rewriter);
728 rewriter.setInsertionPointToEnd(group.getBody());
729 auto addrPorts = memoryInterface.
addrPorts();
730 if (addressValues.empty()) {
732 addrPorts.size() == 1 &&
733 "We expected a 1 dimensional memory of size 1 because there were no "
734 "address assignment values");
736 rewriter.create<calyx::AssignOp>(
740 assert(addrPorts.size() == addressValues.size() &&
741 "Mismatch between number of address ports of the provided memory "
742 "and address assignment values");
743 for (
auto address : enumerate(addressValues))
744 rewriter.create<calyx::AssignOp>(loc, addrPorts[address.index()],
750 Value signal,
bool invert,
751 StringRef nameSuffix,
752 calyx::CompareFOpIEEE754 calyxCmpFOp,
753 calyx::GroupOp group)
const {
754 Location loc = calyxCmpFOp.getLoc();
755 IntegerType one = rewriter.getI1Type();
757 OpBuilder builder(group->getRegion(0));
758 auto reg = createRegister(
759 loc, rewriter, component, 1,
760 getState<ComponentLoweringState>().getUniqueName(nameSuffix));
761 rewriter.create<calyx::AssignOp>(loc, reg.getWriteEn(),
762 calyxCmpFOp.getDone());
764 auto notLibOp = getState<ComponentLoweringState>()
765 .getNewLibraryOpInstance<calyx::NotLibOp>(
766 rewriter, loc, {one, one});
767 rewriter.create<calyx::AssignOp>(loc, notLibOp.getIn(), signal);
768 rewriter.create<calyx::AssignOp>(loc, reg.getIn(), notLibOp.getOut());
769 getState<ComponentLoweringState>().registerEvaluatingGroup(
770 notLibOp.getOut(), group);
772 rewriter.create<calyx::AssignOp>(loc, reg.getIn(), signal);
778 memref::LoadOp loadOp)
const {
779 Value memref = loadOp.getMemref();
780 auto memoryInterface =
781 getState<ComponentLoweringState>().getMemoryInterface(memref);
782 auto group = createGroupForOp<calyx::GroupOp>(rewriter, loadOp);
784 loadOp.getIndices());
786 rewriter.setInsertionPointToEnd(group.getBodyBlock());
791 createConstant(loadOp.getLoc(), rewriter,
getComponent(), 1, 1);
792 if (memoryInterface.readEnOpt().has_value()) {
795 rewriter.create<calyx::AssignOp>(loadOp.getLoc(), memoryInterface.readEn(),
797 regWriteEn = memoryInterface.done();
804 rewriter.create<calyx::GroupDoneOp>(loadOp.getLoc(),
805 memoryInterface.done());
815 res = loadOp.getResult();
817 }
else if (memoryInterface.contentEnOpt().has_value()) {
822 rewriter.create<calyx::AssignOp>(loadOp.getLoc(),
823 memoryInterface.contentEn(), oneI1);
824 rewriter.create<calyx::AssignOp>(loadOp.getLoc(), memoryInterface.writeEn(),
826 regWriteEn = memoryInterface.done();
833 rewriter.create<calyx::GroupDoneOp>(loadOp.getLoc(),
834 memoryInterface.done());
844 res = loadOp.getResult();
856 auto reg = createRegister(
858 loadOp.getMemRefType().getElementTypeBitWidth(),
859 getState<ComponentLoweringState>().getUniqueName(
"load"));
860 rewriter.setInsertionPointToEnd(group.getBodyBlock());
861 rewriter.create<calyx::AssignOp>(loadOp.getLoc(), reg.getIn(),
862 memoryInterface.readData());
863 rewriter.create<calyx::AssignOp>(loadOp.getLoc(), reg.getWriteEn(),
865 rewriter.create<calyx::GroupDoneOp>(loadOp.getLoc(), reg.getDone());
866 loadOp.getResult().replaceAllUsesWith(reg.getOut());
870 getState<ComponentLoweringState>().registerEvaluatingGroup(res, group);
871 getState<ComponentLoweringState>().addBlockScheduleable(loadOp->getBlock(),
877 memref::StoreOp storeOp)
const {
878 auto memoryInterface = getState<ComponentLoweringState>().getMemoryInterface(
879 storeOp.getMemref());
880 auto group = createGroupForOp<calyx::GroupOp>(rewriter, storeOp);
884 getState<ComponentLoweringState>().addBlockScheduleable(storeOp->getBlock(),
887 storeOp.getIndices());
888 rewriter.setInsertionPointToEnd(group.getBodyBlock());
889 rewriter.create<calyx::AssignOp>(
890 storeOp.getLoc(), memoryInterface.writeData(), storeOp.getValueToStore());
891 rewriter.create<calyx::AssignOp>(
892 storeOp.getLoc(), memoryInterface.writeEn(),
893 createConstant(storeOp.getLoc(), rewriter,
getComponent(), 1, 1));
894 if (memoryInterface.contentEnOpt().has_value()) {
896 rewriter.create<calyx::AssignOp>(
897 storeOp.getLoc(), memoryInterface.contentEn(),
898 createConstant(storeOp.getLoc(), rewriter,
getComponent(), 1, 1));
900 rewriter.create<calyx::GroupDoneOp>(storeOp.getLoc(), memoryInterface.done());
907 Location loc = mul.getLoc();
908 Type width = mul.getResult().getType(), one = rewriter.getI1Type();
910 getState<ComponentLoweringState>()
911 .getNewLibraryOpInstance<calyx::MultPipeLibOp>(
912 rewriter, loc, {one, one, one, width, width, width, one});
913 return buildLibraryBinaryPipeOp<calyx::MultPipeLibOp>(
914 rewriter, mul, mulPipe,
920 Location loc = div.getLoc();
921 Type width = div.getResult().getType(), one = rewriter.getI1Type();
923 getState<ComponentLoweringState>()
924 .getNewLibraryOpInstance<calyx::DivUPipeLibOp>(
925 rewriter, loc, {one, one, one, width, width, width, one});
926 return buildLibraryBinaryPipeOp<calyx::DivUPipeLibOp>(
927 rewriter, div, divPipe,
933 Location loc = div.getLoc();
934 Type width = div.getResult().getType(), one = rewriter.getI1Type();
936 getState<ComponentLoweringState>()
937 .getNewLibraryOpInstance<calyx::DivSPipeLibOp>(
938 rewriter, loc, {one, one, one, width, width, width, one});
939 return buildLibraryBinaryPipeOp<calyx::DivSPipeLibOp>(
940 rewriter, div, divPipe,
946 Location loc = rem.getLoc();
947 Type width = rem.getResult().getType(), one = rewriter.getI1Type();
949 getState<ComponentLoweringState>()
950 .getNewLibraryOpInstance<calyx::RemUPipeLibOp>(
951 rewriter, loc, {one, one, one, width, width, width, one});
952 return buildLibraryBinaryPipeOp<calyx::RemUPipeLibOp>(
953 rewriter, rem, remPipe,
959 Location loc = rem.getLoc();
960 Type width = rem.getResult().getType(), one = rewriter.getI1Type();
962 getState<ComponentLoweringState>()
963 .getNewLibraryOpInstance<calyx::RemSPipeLibOp>(
964 rewriter, loc, {one, one, one, width, width, width, one});
965 return buildLibraryBinaryPipeOp<calyx::RemSPipeLibOp>(
966 rewriter, rem, remPipe,
972 Location loc = addf.getLoc();
973 IntegerType one = rewriter.getI1Type(), three = rewriter.getIntegerType(3),
974 five = rewriter.getIntegerType(5),
975 width = rewriter.getIntegerType(
976 addf.getType().getIntOrFloatBitWidth());
978 getState<ComponentLoweringState>()
979 .getNewLibraryOpInstance<calyx::AddFOpIEEE754>(
981 {one, one, one, one, one, width, width, three, width, five, one});
982 return buildLibraryBinaryPipeOp<calyx::AddFOpIEEE754>(rewriter, addf, addFOp,
988 Location loc = subf.getLoc();
989 IntegerType one = rewriter.getI1Type(), three = rewriter.getIntegerType(3),
990 five = rewriter.getIntegerType(5),
991 width = rewriter.getIntegerType(
992 subf.getType().getIntOrFloatBitWidth());
994 getState<ComponentLoweringState>()
995 .getNewLibraryOpInstance<calyx::AddFOpIEEE754>(
997 {one, one, one, one, one, width, width, three, width, five, one});
998 return buildLibraryBinaryPipeOp<calyx::AddFOpIEEE754>(rewriter, subf, subFOp,
1003 MulFOp mulf)
const {
1004 Location loc = mulf.getLoc();
1005 IntegerType one = rewriter.getI1Type(), three = rewriter.getIntegerType(3),
1006 five = rewriter.getIntegerType(5),
1007 width = rewriter.getIntegerType(
1008 mulf.getType().getIntOrFloatBitWidth());
1010 getState<ComponentLoweringState>()
1011 .getNewLibraryOpInstance<calyx::MulFOpIEEE754>(
1013 {one, one, one, one, width, width, three, width, five, one});
1014 return buildLibraryBinaryPipeOp<calyx::MulFOpIEEE754>(rewriter, mulf, mulFOp,
1019 CmpFOp cmpf)
const {
1020 Location loc = cmpf.getLoc();
1021 IntegerType one = rewriter.getI1Type(), five = rewriter.getIntegerType(5),
1022 width = rewriter.getIntegerType(
1023 cmpf.getLhs().getType().getIntOrFloatBitWidth());
1024 auto calyxCmpFOp = getState<ComponentLoweringState>()
1025 .getNewLibraryOpInstance<calyx::CompareFOpIEEE754>(
1027 {one, one, one, width, width, one, one, one, one,
1034 using CombLogic = PredicateInfo::CombLogic;
1035 using Port = PredicateInfo::InputPorts::Port;
1037 if (info.logic == CombLogic::None) {
1038 if (cmpf.getPredicate() == CmpFPredicate::AlwaysTrue) {
1039 cmpf.getResult().replaceAllUsesWith(c1);
1043 if (cmpf.getPredicate() == CmpFPredicate::AlwaysFalse) {
1044 cmpf.getResult().replaceAllUsesWith(c0);
1050 StringRef opName = cmpf.getOperationName().split(
".").second;
1053 getState<ComponentLoweringState>().getUniqueName(opName));
1056 auto group = createGroupForOp<calyx::GroupOp>(rewriter, cmpf);
1057 OpBuilder builder(group->getRegion(0));
1058 getState<ComponentLoweringState>().addBlockScheduleable(cmpf->getBlock(),
1061 rewriter.setInsertionPointToEnd(group.getBodyBlock());
1062 rewriter.create<calyx::AssignOp>(loc, calyxCmpFOp.getLeft(), cmpf.getLhs());
1063 rewriter.create<calyx::AssignOp>(loc, calyxCmpFOp.getRight(), cmpf.getRhs());
1065 bool signalingFlag =
false;
1066 switch (cmpf.getPredicate()) {
1067 case CmpFPredicate::UGT:
1068 case CmpFPredicate::UGE:
1069 case CmpFPredicate::ULT:
1070 case CmpFPredicate::ULE:
1071 case CmpFPredicate::OGT:
1072 case CmpFPredicate::OGE:
1073 case CmpFPredicate::OLT:
1074 case CmpFPredicate::OLE:
1075 signalingFlag =
true;
1077 case CmpFPredicate::UEQ:
1078 case CmpFPredicate::UNE:
1079 case CmpFPredicate::OEQ:
1080 case CmpFPredicate::ONE:
1081 case CmpFPredicate::UNO:
1082 case CmpFPredicate::ORD:
1083 case CmpFPredicate::AlwaysTrue:
1084 case CmpFPredicate::AlwaysFalse:
1085 signalingFlag =
false;
1091 rewriter.create<calyx::AssignOp>(loc, calyxCmpFOp.getSignaling(),
1092 signalingFlag ? c1 : c0);
1095 SmallVector<calyx::RegisterOp> inputRegs;
1096 for (
const auto &input : info.inputPorts) {
1098 switch (input.port) {
1100 signal = calyxCmpFOp.getEq();
1104 signal = calyxCmpFOp.getGt();
1108 signal = calyxCmpFOp.getLt();
1111 case Port::Unordered: {
1112 signal = calyxCmpFOp.getUnordered();
1116 std::string nameSuffix =
1117 (input.port == PredicateInfo::InputPorts::Port::Unordered)
1121 nameSuffix, calyxCmpFOp, group);
1122 inputRegs.push_back(signalReg);
1126 Value outputValue, doneValue;
1127 switch (info.logic) {
1128 case CombLogic::None: {
1130 outputValue = inputRegs[0].getOut();
1131 doneValue = inputRegs[0].getDone();
1134 case CombLogic::And: {
1135 auto outputLibOp = getState<ComponentLoweringState>()
1136 .getNewLibraryOpInstance<calyx::AndLibOp>(
1137 rewriter, loc, {one, one, one});
1138 rewriter.create<calyx::AssignOp>(loc, outputLibOp.getLeft(),
1139 inputRegs[0].getOut());
1140 rewriter.create<calyx::AssignOp>(loc, outputLibOp.getRight(),
1141 inputRegs[1].getOut());
1143 outputValue = outputLibOp.getOut();
1146 case CombLogic::Or: {
1147 auto outputLibOp = getState<ComponentLoweringState>()
1148 .getNewLibraryOpInstance<calyx::OrLibOp>(
1149 rewriter, loc, {one, one, one});
1150 rewriter.create<calyx::AssignOp>(loc, outputLibOp.getLeft(),
1151 inputRegs[0].getOut());
1152 rewriter.create<calyx::AssignOp>(loc, outputLibOp.getRight(),
1153 inputRegs[1].getOut());
1155 outputValue = outputLibOp.getOut();
1160 if (info.logic != CombLogic::None) {
1161 auto doneLibOp = getState<ComponentLoweringState>()
1162 .getNewLibraryOpInstance<calyx::AndLibOp>(
1163 rewriter, loc, {one, one, one});
1164 rewriter.create<calyx::AssignOp>(loc, doneLibOp.getLeft(),
1165 inputRegs[0].getDone());
1166 rewriter.create<calyx::AssignOp>(loc, doneLibOp.getRight(),
1167 inputRegs[1].getDone());
1168 doneValue = doneLibOp.getOut();
1172 rewriter.create<calyx::AssignOp>(loc, reg.getIn(), outputValue);
1173 rewriter.create<calyx::AssignOp>(loc, reg.getWriteEn(), doneValue);
1176 rewriter.create<calyx::AssignOp>(
1177 loc, calyxCmpFOp.getGo(), c1,
1179 rewriter.create<calyx::GroupDoneOp>(loc, reg.getDone());
1181 cmpf.getResult().replaceAllUsesWith(reg.getOut());
1184 getState<ComponentLoweringState>().registerEvaluatingGroup(outputValue,
1186 getState<ComponentLoweringState>().registerEvaluatingGroup(doneValue, group);
1187 getState<ComponentLoweringState>().registerEvaluatingGroup(
1188 calyxCmpFOp.getLeft(), group);
1189 getState<ComponentLoweringState>().registerEvaluatingGroup(
1190 calyxCmpFOp.getRight(), group);
1196 FPToSIOp fptosi)
const {
1197 return buildFpIntTypeCastOp<calyx::FpToIntOpIEEE754>(
1198 rewriter, fptosi, fptosi.getIn().getType().getIntOrFloatBitWidth(),
1199 fptosi.getOut().getType().getIntOrFloatBitWidth(),
"signedOut");
1203 SIToFPOp sitofp)
const {
1204 return buildFpIntTypeCastOp<calyx::IntToFpOpIEEE754>(
1205 rewriter, sitofp, sitofp.getIn().getType().getIntOrFloatBitWidth(),
1206 sitofp.getOut().getType().getIntOrFloatBitWidth(),
"signedIn");
1210 DivFOp divf)
const {
1211 Location loc = divf.getLoc();
1212 IntegerType one = rewriter.getI1Type(), three = rewriter.getIntegerType(3),
1213 five = rewriter.getIntegerType(5),
1214 width = rewriter.getIntegerType(
1215 divf.getType().getIntOrFloatBitWidth());
1216 auto divFOp = getState<ComponentLoweringState>()
1217 .getNewLibraryOpInstance<calyx::DivSqrtOpIEEE754>(
1221 width, three, width,
1223 return buildLibraryBinaryPipeOp<calyx::DivSqrtOpIEEE754>(
1224 rewriter, divf, divFOp, divFOp.getOut());
1228 math::SqrtOp sqrt)
const {
1229 Location loc = sqrt.getLoc();
1230 IntegerType one = rewriter.getI1Type(), three = rewriter.getIntegerType(3),
1231 five = rewriter.getIntegerType(5),
1232 width = rewriter.getIntegerType(
1233 sqrt.getType().getIntOrFloatBitWidth());
1234 auto sqrtOp = getState<ComponentLoweringState>()
1235 .getNewLibraryOpInstance<calyx::DivSqrtOpIEEE754>(
1239 width, three, width,
1241 return buildLibraryBinaryPipeOp<calyx::DivSqrtOpIEEE754>(
1242 rewriter, sqrt, sqrtOp, sqrtOp.getOut());
1245template <
typename TAllocOp>
1247 PatternRewriter &rewriter, TAllocOp allocOp) {
1248 rewriter.setInsertionPointToStart(
1250 MemRefType memtype = allocOp.getType();
1251 SmallVector<int64_t> addrSizes;
1252 SmallVector<int64_t> sizes;
1253 for (int64_t dim : memtype.getShape()) {
1254 sizes.push_back(dim);
1259 if (sizes.empty() && addrSizes.empty()) {
1261 addrSizes.push_back(1);
1263 auto memoryOp = rewriter.create<calyx::SeqMemoryOp>(
1265 memtype.getElementType().getIntOrFloatBitWidth(), sizes, addrSizes);
1269 memoryOp->setAttr(
"external",
1270 IntegerAttr::get(rewriter.getI1Type(), llvm::APInt(1, 1)));
1274 unsigned elmTyBitWidth = memtype.getElementTypeBitWidth();
1275 assert(elmTyBitWidth <= 64 &&
"element bitwidth should not exceed 64");
1276 bool isFloat = !memtype.getElementType().isInteger();
1278 auto shape = allocOp.getType().getShape();
1280 std::reduce(shape.begin(), shape.end(), 1, std::multiplies<int>());
1287 if (!(shape.size() <= 1 || totalSize <= 1)) {
1288 allocOp.emitError(
"input memory dimension must be empty or one.");
1292 std::vector<uint64_t> flattenedVals(totalSize, 0);
1293 if (isa<memref::GetGlobalOp>(allocOp)) {
1294 auto getGlobalOp = cast<memref::GetGlobalOp>(allocOp);
1295 auto *symbolTableOp =
1296 getGlobalOp->template getParentWithTrait<mlir::OpTrait::SymbolTable>();
1297 auto globalOp = dyn_cast_or_null<memref::GlobalOp>(
1298 SymbolTable::lookupSymbolIn(symbolTableOp, getGlobalOp.getNameAttr()));
1300 auto cstAttr = llvm::dyn_cast_or_null<DenseElementsAttr>(
1301 globalOp.getConstantInitValue());
1303 for (
auto attr : cstAttr.template getValues<Attribute>()) {
1304 assert((isa<mlir::FloatAttr, mlir::IntegerAttr>(attr)) &&
1305 "memory attributes must be float or int");
1306 if (
auto fltAttr = dyn_cast<mlir::FloatAttr>(attr)) {
1307 flattenedVals[sizeCount++] =
1308 bit_cast<uint64_t>(fltAttr.getValueAsDouble());
1310 auto intAttr = dyn_cast<mlir::IntegerAttr>(attr);
1311 APInt value = intAttr.getValue();
1312 flattenedVals[sizeCount++] = *value.getRawData();
1316 rewriter.eraseOp(globalOp);
1319 llvm::json::Array result;
1320 result.reserve(std::max(
static_cast<int>(shape.size()), 1));
1322 Type elemType = memtype.getElementType();
1324 !elemType.isSignlessInteger() && !elemType.isUnsignedInteger();
1325 for (uint64_t bitValue : flattenedVals) {
1326 llvm::json::Value value = 0;
1330 value = bit_cast<double>(bitValue);
1332 APInt apInt(elmTyBitWidth, bitValue, isSigned,
1337 value =
static_cast<int64_t
>(apInt.getSExtValue());
1339 value = apInt.getZExtValue();
1341 result.push_back(std::move(value));
1344 componentState.
setDataField(memoryOp.getName(), result);
1345 std::string numType =
1346 memtype.getElementType().isInteger() ?
"bitnum" :
"ieee754_float";
1347 componentState.
setFormat(memoryOp.getName(), numType, isSigned,
1354 memref::AllocOp allocOp)
const {
1355 return buildAllocOp(getState<ComponentLoweringState>(), rewriter, allocOp);
1359 memref::AllocaOp allocOp)
const {
1360 return buildAllocOp(getState<ComponentLoweringState>(), rewriter, allocOp);
1364 memref::GetGlobalOp getGlobalOp)
const {
1365 return buildAllocOp(getState<ComponentLoweringState>(), rewriter,
1370 scf::YieldOp yieldOp)
const {
1371 if (yieldOp.getOperands().empty()) {
1372 if (
auto forOp = dyn_cast<scf::ForOp>(yieldOp->getParentOp())) {
1376 auto inductionReg = getState<ComponentLoweringState>().getForLoopIterReg(
1379 Type regWidth = inductionReg.getOut().getType();
1381 SmallVector<Type> types(3, regWidth);
1382 auto addOp = getState<ComponentLoweringState>()
1383 .getNewLibraryOpInstance<calyx::AddLibOp>(
1384 rewriter, forOp.getLoc(), types);
1386 auto directions = addOp.portDirections();
1388 SmallVector<Value, 2> opInputPorts;
1390 for (
auto dir : enumerate(directions)) {
1391 switch (dir.value()) {
1393 opInputPorts.push_back(addOp.getResult(dir.index()));
1397 opOutputPort = addOp.getResult(dir.index());
1405 getState<ComponentLoweringState>().getComponentOp();
1406 SmallVector<StringRef, 4> groupIdentifier = {
1407 "incr", getState<ComponentLoweringState>().getUniqueName(forOp),
1408 "induction",
"var"};
1409 auto groupOp = calyx::createGroup<calyx::GroupOp>(
1411 llvm::join(groupIdentifier,
"_"));
1412 rewriter.setInsertionPointToEnd(groupOp.getBodyBlock());
1415 Value leftOp = opInputPorts.front();
1416 rewriter.create<calyx::AssignOp>(forOp.getLoc(), leftOp,
1417 inductionReg.getOut());
1419 Value rightOp = opInputPorts.back();
1420 rewriter.create<calyx::AssignOp>(
1421 forOp.getLoc(), rightOp,
1422 createConstant(forOp->getLoc(), rewriter,
componentOp,
1423 regWidth.getIntOrFloatBitWidth(),
1424 forOp.getConstantStep().value().getSExtValue()));
1426 buildAssignmentsForRegisterWrite(rewriter, groupOp,
componentOp,
1427 inductionReg, opOutputPort);
1429 getState<ComponentLoweringState>().setForLoopLatchGroup(forOpInterface,
1431 getState<ComponentLoweringState>().registerEvaluatingGroup(opOutputPort,
1435 if (
auto ifOp = dyn_cast<scf::IfOp>(yieldOp->getParentOp()))
1438 if (
auto executeRegionOp =
1439 dyn_cast<scf::ExecuteRegionOp>(yieldOp->getParentOp()))
1442 return yieldOp.getOperation()->emitError()
1443 <<
"Unsupported empty yieldOp outside ForOp or IfOp.";
1446 if (dyn_cast<scf::ForOp>(yieldOp->getParentOp())) {
1447 return yieldOp.getOperation()->emitError()
1448 <<
"Currently do not support non-empty yield operations inside for "
1449 "loops. Run --scf-for-to-while before running --scf-to-calyx.";
1452 if (
auto whileOp = dyn_cast<scf::WhileOp>(yieldOp->getParentOp())) {
1456 getState<ComponentLoweringState>().buildWhileLoopIterArgAssignments(
1457 rewriter, whileOpInterface,
1458 getState<ComponentLoweringState>().getComponentOp(),
1459 getState<ComponentLoweringState>().getUniqueName(whileOp) +
1461 yieldOp->getOpOperands());
1462 getState<ComponentLoweringState>().setWhileLoopLatchGroup(whileOpInterface,
1467 if (
auto ifOp = dyn_cast<scf::IfOp>(yieldOp->getParentOp())) {
1468 auto resultRegs = getState<ComponentLoweringState>().getResultRegs(ifOp);
1470 if (yieldOp->getParentRegion() == &ifOp.getThenRegion()) {
1471 auto thenGroup = getState<ComponentLoweringState>().getThenGroup(ifOp);
1472 for (
auto op : enumerate(yieldOp.getOperands())) {
1474 getState<ComponentLoweringState>().getResultRegs(ifOp, op.index());
1475 buildAssignmentsForRegisterWrite(
1476 rewriter, thenGroup,
1477 getState<ComponentLoweringState>().getComponentOp(), resultReg,
1479 getState<ComponentLoweringState>().registerEvaluatingGroup(
1480 ifOp.getResult(op.index()), thenGroup);
1484 if (!ifOp.getElseRegion().empty() &&
1485 (yieldOp->getParentRegion() == &ifOp.getElseRegion())) {
1486 auto elseGroup = getState<ComponentLoweringState>().getElseGroup(ifOp);
1487 for (
auto op : enumerate(yieldOp.getOperands())) {
1489 getState<ComponentLoweringState>().getResultRegs(ifOp, op.index());
1490 buildAssignmentsForRegisterWrite(
1491 rewriter, elseGroup,
1492 getState<ComponentLoweringState>().getComponentOp(), resultReg,
1494 getState<ComponentLoweringState>().registerEvaluatingGroup(
1495 ifOp.getResult(op.index()), elseGroup);
1503 BranchOpInterface brOp)
const {
1508 Block *srcBlock = brOp->getBlock();
1509 for (
auto succBlock : enumerate(brOp->getSuccessors())) {
1510 auto succOperands = brOp.getSuccessorOperands(succBlock.index());
1511 if (succOperands.empty())
1516 auto groupOp = calyx::createGroup<calyx::GroupOp>(rewriter,
getComponent(),
1517 brOp.getLoc(), groupName);
1519 auto dstBlockArgRegs =
1520 getState<ComponentLoweringState>().getBlockArgRegs(succBlock.value());
1522 for (
auto arg : enumerate(succOperands.getForwardedOperands())) {
1523 auto reg = dstBlockArgRegs[arg.index()];
1526 getState<ComponentLoweringState>().getComponentOp(), reg,
1531 getState<ComponentLoweringState>().addBlockArgGroup(
1532 srcBlock, succBlock.value(), groupOp);
1540 ReturnOp retOp)
const {
1541 if (retOp.getNumOperands() == 0)
1544 std::string groupName =
1545 getState<ComponentLoweringState>().getUniqueName(
"ret_assign");
1546 auto groupOp = calyx::createGroup<calyx::GroupOp>(rewriter,
getComponent(),
1547 retOp.getLoc(), groupName);
1548 for (
auto op : enumerate(retOp.getOperands())) {
1549 auto reg = getState<ComponentLoweringState>().getReturnReg(op.index());
1551 rewriter, groupOp, getState<ComponentLoweringState>().getComponentOp(),
1555 getState<ComponentLoweringState>().addBlockScheduleable(retOp->getBlock(),
1561 arith::ConstantOp constOp)
const {
1562 if (isa<IntegerType>(constOp.getType())) {
1571 std::string name = getState<ComponentLoweringState>().getUniqueName(
"cst");
1572 auto floatAttr = cast<FloatAttr>(constOp.getValueAttr());
1574 rewriter.getIntegerType(floatAttr.getType().getIntOrFloatBitWidth());
1575 auto calyxConstOp = rewriter.create<calyx::ConstantOp>(
1576 constOp.getLoc(), name, floatAttr, intType);
1579 rewriter.replaceAllUsesWith(constOp, calyxConstOp.getOut());
1587 return buildLibraryOp<calyx::CombGroupOp, calyx::AddLibOp>(rewriter, op);
1591 return buildLibraryOp<calyx::CombGroupOp, calyx::SubLibOp>(rewriter, op);
1595 return buildLibraryOp<calyx::CombGroupOp, calyx::RshLibOp>(rewriter, op);
1599 return buildLibraryOp<calyx::CombGroupOp, calyx::SrshLibOp>(rewriter, op);
1603 return buildLibraryOp<calyx::CombGroupOp, calyx::LshLibOp>(rewriter, op);
1607 return buildLibraryOp<calyx::CombGroupOp, calyx::AndLibOp>(rewriter, op);
1611 return buildLibraryOp<calyx::CombGroupOp, calyx::OrLibOp>(rewriter, op);
1615 return buildLibraryOp<calyx::CombGroupOp, calyx::XorLibOp>(rewriter, op);
1618 SelectOp op)
const {
1619 return buildLibraryOp<calyx::CombGroupOp, calyx::MuxLibOp>(rewriter, op);
1624 switch (op.getPredicate()) {
1625 case CmpIPredicate::eq:
1626 return buildCmpIOpHelper<calyx::EqLibOp>(rewriter, op);
1627 case CmpIPredicate::ne:
1628 return buildCmpIOpHelper<calyx::NeqLibOp>(rewriter, op);
1629 case CmpIPredicate::uge:
1630 return buildCmpIOpHelper<calyx::GeLibOp>(rewriter, op);
1631 case CmpIPredicate::ult:
1632 return buildCmpIOpHelper<calyx::LtLibOp>(rewriter, op);
1633 case CmpIPredicate::ugt:
1634 return buildCmpIOpHelper<calyx::GtLibOp>(rewriter, op);
1635 case CmpIPredicate::ule:
1636 return buildCmpIOpHelper<calyx::LeLibOp>(rewriter, op);
1637 case CmpIPredicate::sge:
1638 return buildCmpIOpHelper<calyx::SgeLibOp>(rewriter, op);
1639 case CmpIPredicate::slt:
1640 return buildCmpIOpHelper<calyx::SltLibOp>(rewriter, op);
1641 case CmpIPredicate::sgt:
1642 return buildCmpIOpHelper<calyx::SgtLibOp>(rewriter, op);
1643 case CmpIPredicate::sle:
1644 return buildCmpIOpHelper<calyx::SleLibOp>(rewriter, op);
1646 llvm_unreachable(
"unsupported comparison predicate");
1650 TruncIOp op)
const {
1651 return buildLibraryOp<calyx::CombGroupOp, calyx::SliceLibOp>(
1652 rewriter, op, {op.getOperand().getType()}, {op.getType()});
1656 return buildLibraryOp<calyx::CombGroupOp, calyx::PadLibOp>(
1657 rewriter, op, {op.getOperand().getType()}, {op.getType()});
1662 return buildLibraryOp<calyx::CombGroupOp, calyx::ExtSILibOp>(
1663 rewriter, op, {op.getOperand().getType()}, {op.getType()});
1667 IndexCastOp op)
const {
1670 unsigned targetBits = targetType.getIntOrFloatBitWidth();
1671 unsigned sourceBits = sourceType.getIntOrFloatBitWidth();
1672 LogicalResult res = success();
1674 if (targetBits == sourceBits) {
1677 op.getResult().replaceAllUsesWith(op.getOperand());
1680 if (sourceBits > targetBits)
1681 res = buildLibraryOp<calyx::CombGroupOp, calyx::SliceLibOp>(
1682 rewriter, op, {sourceType}, {targetType});
1684 res = buildLibraryOp<calyx::CombGroupOp, calyx::PadLibOp>(
1685 rewriter, op, {sourceType}, {targetType});
1687 rewriter.eraseOp(op);
1694 BitcastOp op)
const {
1695 rewriter.replaceAllUsesWith(op.getOut(), op.getIn());
1700 scf::WhileOp whileOp)
const {
1704 getState<ComponentLoweringState>().addBlockScheduleable(
1710 scf::ForOp forOp)
const {
1716 std::optional<uint64_t> bound = scfForOp.
getBound();
1717 if (!bound.has_value()) {
1719 <<
"Loop bound not statically known. Should "
1720 "transform into while loop using `--scf-for-to-while` before "
1721 "running --lower-scf-to-calyx.";
1723 getState<ComponentLoweringState>().addBlockScheduleable(
1732 scf::IfOp ifOp)
const {
1733 getState<ComponentLoweringState>().addBlockScheduleable(
1739 scf::ReduceOp reduceOp)
const {
1747 scf::ParallelOp parOp)
const {
1750 "AffineParallelUnroll must be run in order to lower scf.parallel");
1753 getState<ComponentLoweringState>().addBlockScheduleable(
1760 scf::ExecuteRegionOp executeRegionOp)
const {
1768 CallOp callOp)
const {
1770 calyx::InstanceOp instanceOp =
1771 getState<ComponentLoweringState>().getInstance(instanceName);
1772 SmallVector<Value, 4> outputPorts;
1773 auto portInfos = instanceOp.getReferencedComponent().getPortInfo();
1774 for (
auto [idx, portInfo] : enumerate(portInfos)) {
1776 outputPorts.push_back(instanceOp.getResult(idx));
1780 for (
auto [idx, result] : llvm::enumerate(callOp.getResults()))
1781 rewriter.replaceAllUsesWith(result, outputPorts[idx]);
1785 getState<ComponentLoweringState>().addBlockScheduleable(
1799 using OpRewritePattern::OpRewritePattern;
1802 PatternRewriter &rewriter)
const override {
1803 if (
auto parOp = dyn_cast_or_null<scf::ParallelOp>(execOp->getParentOp())) {
1804 if (
auto boolAttr = dyn_cast_or_null<mlir::BoolAttr>(
1812 TypeRange yieldTypes = execOp.getResultTypes();
1816 rewriter.setInsertionPointAfter(execOp);
1817 auto *sinkBlock = rewriter.splitBlock(
1819 execOp.getOperation()->getIterator()->getNextNode()->getIterator());
1820 sinkBlock->addArguments(
1822 SmallVector<Location, 4>(yieldTypes.size(), rewriter.getUnknownLoc()));
1823 for (
auto res : enumerate(execOp.getResults()))
1824 res.value().replaceAllUsesWith(sinkBlock->getArgument(res.index()));
1828 make_early_inc_range(execOp.getRegion().getOps<scf::YieldOp>())) {
1829 rewriter.setInsertionPointAfter(yieldOp);
1830 rewriter.replaceOpWithNewOp<BranchOp>(yieldOp, sinkBlock,
1831 yieldOp.getOperands());
1835 auto *preBlock = execOp->getBlock();
1836 auto *execOpEntryBlock = &execOp.getRegion().front();
1837 auto *postBlock = execOp->getBlock()->splitBlock(execOp);
1838 rewriter.inlineRegionBefore(execOp.getRegion(), postBlock);
1839 rewriter.mergeBlocks(postBlock, preBlock);
1840 rewriter.eraseOp(execOp);
1843 rewriter.mergeBlocks(execOpEntryBlock, preBlock);
1851 using FuncOpPartialLoweringPattern::FuncOpPartialLoweringPattern;
1855 PatternRewriter &rewriter)
const override {
1858 DenseMap<Value, unsigned> funcOpArgRewrites;
1862 DenseMap<unsigned, unsigned> funcOpResultMapping;
1870 DenseMap<Value, std::pair<unsigned, unsigned>> extMemoryCompPortIndices;
1874 SmallVector<calyx::PortInfo> inPorts, outPorts;
1875 FunctionType funcType = funcOp.getFunctionType();
1876 for (
auto arg : enumerate(funcOp.getArguments())) {
1877 if (!isa<MemRefType>(arg.value().getType())) {
1880 if (
auto portNameAttr = funcOp.getArgAttrOfType<StringAttr>(
1882 inName = portNameAttr.str();
1884 inName =
"in" + std::to_string(arg.index());
1885 funcOpArgRewrites[arg.value()] = inPorts.size();
1887 rewriter.getStringAttr(inName),
1890 DictionaryAttr::get(rewriter.getContext(), {})});
1893 for (
auto res : enumerate(funcType.getResults())) {
1894 std::string resName;
1895 if (
auto portNameAttr = funcOp.getResultAttrOfType<StringAttr>(
1897 resName = portNameAttr.str();
1899 resName =
"out" + std::to_string(res.index());
1900 funcOpResultMapping[res.index()] = outPorts.size();
1903 rewriter.getStringAttr(resName),
1905 DictionaryAttr::get(rewriter.getContext(), {})});
1910 auto ports = inPorts;
1911 llvm::append_range(ports, outPorts);
1915 auto compOp = rewriter.create<calyx::ComponentOp>(
1916 funcOp.getLoc(), rewriter.getStringAttr(funcOp.getSymName()), ports);
1918 std::string funcName =
"func_" + funcOp.getSymName().str();
1919 rewriter.modifyOpInPlace(funcOp, [&]() { funcOp.setSymName(funcName); });
1924 compOp->setAttr(
"toplevel", rewriter.getUnitAttr());
1931 unsigned extMemCounter = 0;
1932 for (
auto arg : enumerate(funcOp.getArguments())) {
1933 if (isa<MemRefType>(arg.value().getType())) {
1934 std::string memName =
1935 llvm::join_items(
"_",
"arg_mem", std::to_string(extMemCounter++));
1937 rewriter.setInsertionPointToStart(compOp.getBodyBlock());
1938 MemRefType memtype = cast<MemRefType>(arg.value().getType());
1939 SmallVector<int64_t> addrSizes;
1940 SmallVector<int64_t> sizes;
1941 for (int64_t dim : memtype.getShape()) {
1942 sizes.push_back(dim);
1945 if (sizes.empty() && addrSizes.empty()) {
1947 addrSizes.push_back(1);
1949 auto memOp = rewriter.create<calyx::SeqMemoryOp>(
1950 funcOp.getLoc(), memName,
1951 memtype.getElementType().getIntOrFloatBitWidth(), sizes, addrSizes);
1954 compState->registerMemoryInterface(arg.value(),
1960 for (
auto &mapping : funcOpArgRewrites)
1961 mapping.getFirst().replaceAllUsesWith(
1962 compOp.getArgument(mapping.getSecond()));
1973 using FuncOpPartialLoweringPattern::FuncOpPartialLoweringPattern;
1977 PatternRewriter &rewriter)
const override {
1978 LogicalResult res = success();
1979 funcOp.walk([&](Operation *op) {
1981 if (!isa<scf::WhileOp>(op))
1982 return WalkResult::advance();
1984 auto scfWhileOp = cast<scf::WhileOp>(op);
1987 getState<ComponentLoweringState>().setUniqueName(whileOp.
getOperation(),
1997 enumerate(scfWhileOp.getBefore().front().getArguments())) {
1998 auto condOp = scfWhileOp.getConditionOp().getArgs()[barg.index()];
1999 if (barg.value() != condOp) {
2003 <<
"do-while loops not supported; expected iter-args to "
2004 "remain untransformed in the 'before' region of the "
2006 return WalkResult::interrupt();
2015 for (
auto arg : enumerate(whileOp.
getBodyArgs())) {
2016 std::string name = getState<ComponentLoweringState>()
2019 "_arg" + std::to_string(arg.index());
2021 createRegister(arg.value().getLoc(), rewriter,
getComponent(),
2022 arg.value().getType().getIntOrFloatBitWidth(), name);
2023 getState<ComponentLoweringState>().addWhileLoopIterReg(whileOp, reg,
2025 arg.value().replaceAllUsesWith(reg.getOut());
2029 ->getArgument(arg.index())
2030 .replaceAllUsesWith(reg.getOut());
2034 SmallVector<calyx::GroupOp> initGroups;
2035 auto numOperands = whileOp.
getOperation()->getNumOperands();
2036 for (
size_t i = 0; i < numOperands; ++i) {
2038 getState<ComponentLoweringState>().buildWhileLoopIterArgAssignments(
2040 getState<ComponentLoweringState>().getComponentOp(),
2041 getState<ComponentLoweringState>().getUniqueName(
2043 "_init_" + std::to_string(i),
2045 initGroups.push_back(initGroupOp);
2048 getState<ComponentLoweringState>().setWhileLoopInitGroups(whileOp,
2051 return WalkResult::advance();
2061 using FuncOpPartialLoweringPattern::FuncOpPartialLoweringPattern;
2065 PatternRewriter &rewriter)
const override {
2066 LogicalResult res = success();
2067 funcOp.walk([&](Operation *op) {
2069 if (!isa<scf::ForOp>(op))
2070 return WalkResult::advance();
2072 auto scfForOp = cast<scf::ForOp>(op);
2075 getState<ComponentLoweringState>().setUniqueName(forOp.
getOperation(),
2080 auto inductionVar = forOp.
getOperation().getInductionVar();
2081 SmallVector<std::string, 3> inductionVarIdentifiers = {
2082 getState<ComponentLoweringState>()
2085 "induction",
"var"};
2086 std::string name = llvm::join(inductionVarIdentifiers,
"_");
2088 createRegister(inductionVar.getLoc(), rewriter,
getComponent(),
2089 inductionVar.getType().getIntOrFloatBitWidth(), name);
2090 getState<ComponentLoweringState>().addForLoopIterReg(forOp, reg, 0);
2091 inductionVar.replaceAllUsesWith(reg.getOut());
2095 getState<ComponentLoweringState>().getComponentOp();
2096 SmallVector<calyx::GroupOp> initGroups;
2097 SmallVector<std::string, 4> groupIdentifiers = {
2099 getState<ComponentLoweringState>()
2102 "induction",
"var"};
2103 std::string groupName = llvm::join(groupIdentifiers,
"_");
2104 auto groupOp = calyx::createGroup<calyx::GroupOp>(
2106 buildAssignmentsForRegisterWrite(rewriter, groupOp,
componentOp, reg,
2108 initGroups.push_back(groupOp);
2109 getState<ComponentLoweringState>().setForLoopInitGroups(forOp,
2112 return WalkResult::advance();
2119 using FuncOpPartialLoweringPattern::FuncOpPartialLoweringPattern;
2123 PatternRewriter &rewriter)
const override {
2124 LogicalResult res = success();
2125 funcOp.walk([&](Operation *op) {
2126 if (!isa<scf::IfOp>(op))
2127 return WalkResult::advance();
2129 auto scfIfOp = cast<scf::IfOp>(op);
2134 if (scfIfOp.getResults().empty())
2135 return WalkResult::advance();
2138 getState<ComponentLoweringState>().getComponentOp();
2140 std::string thenGroupName =
2141 getState<ComponentLoweringState>().getUniqueName(
"then_br");
2142 auto thenGroupOp = calyx::createGroup<calyx::GroupOp>(
2143 rewriter,
componentOp, scfIfOp.getLoc(), thenGroupName);
2144 getState<ComponentLoweringState>().setThenGroup(scfIfOp, thenGroupOp);
2146 if (!scfIfOp.getElseRegion().empty()) {
2147 std::string elseGroupName =
2148 getState<ComponentLoweringState>().getUniqueName(
"else_br");
2149 auto elseGroupOp = calyx::createGroup<calyx::GroupOp>(
2150 rewriter,
componentOp, scfIfOp.getLoc(), elseGroupName);
2151 getState<ComponentLoweringState>().setElseGroup(scfIfOp, elseGroupOp);
2154 for (
auto ifOpRes : scfIfOp.getResults()) {
2155 auto reg = createRegister(
2157 ifOpRes.getType().getIntOrFloatBitWidth(),
2158 getState<ComponentLoweringState>().getUniqueName(
"if_res"));
2159 getState<ComponentLoweringState>().setResultRegs(
2160 scfIfOp, reg, ifOpRes.getResultNumber());
2163 return WalkResult::advance();
2175 using FuncOpPartialLoweringPattern::FuncOpPartialLoweringPattern;
2179 PatternRewriter &rewriter)
const override {
2180 auto *entryBlock = &funcOp.getBlocks().front();
2181 rewriter.setInsertionPointToStart(
2183 auto topLevelSeqOp = rewriter.create<calyx::SeqOp>(funcOp.getLoc());
2184 DenseSet<Block *> path;
2186 nullptr, entryBlock);
2193 const DenseSet<Block *> &path,
2194 mlir::Block *parentCtrlBlock,
2195 mlir::Block *block)
const {
2196 auto compBlockScheduleables =
2197 getState<ComponentLoweringState>().getBlockScheduleables(block);
2198 auto loc = block->front().getLoc();
2200 if (compBlockScheduleables.size() > 1 &&
2201 !isa<scf::ParallelOp>(block->getParentOp())) {
2202 auto seqOp = rewriter.create<calyx::SeqOp>(loc);
2203 parentCtrlBlock = seqOp.getBodyBlock();
2206 for (
auto &group : compBlockScheduleables) {
2207 rewriter.setInsertionPointToEnd(parentCtrlBlock);
2208 if (
auto groupPtr = std::get_if<calyx::GroupOp>(&group); groupPtr) {
2209 rewriter.create<calyx::EnableOp>(groupPtr->getLoc(),
2210 groupPtr->getSymName());
2211 }
else if (
auto whileSchedPtr = std::get_if<WhileScheduleable>(&group);
2213 auto &whileOp = whileSchedPtr->whileOp;
2217 getState<ComponentLoweringState>().getWhileLoopInitGroups(whileOp),
2219 rewriter.setInsertionPointToEnd(whileCtrlOp.getBodyBlock());
2221 rewriter.create<calyx::SeqOp>(whileOp.getOperation()->getLoc());
2222 auto *whileBodyOpBlock = whileBodyOp.getBodyBlock();
2226 if (LogicalResult result =
2228 whileOp.getBodyBlock());
2233 rewriter.setInsertionPointToEnd(whileBodyOpBlock);
2234 calyx::GroupOp whileLatchGroup =
2235 getState<ComponentLoweringState>().getWhileLoopLatchGroup(whileOp);
2236 rewriter.create<calyx::EnableOp>(whileLatchGroup.getLoc(),
2237 whileLatchGroup.getName());
2238 }
else if (
auto *parSchedPtr = std::get_if<ParScheduleable>(&group)) {
2239 auto parOp = parSchedPtr->parOp;
2240 auto calyxParOp = rewriter.create<calyx::ParOp>(parOp.getLoc());
2242 WalkResult walkResult =
2243 parOp.walk([&](scf::ExecuteRegionOp execRegion) {
2244 rewriter.setInsertionPointToEnd(calyxParOp.getBodyBlock());
2245 auto seqOp = rewriter.create<calyx::SeqOp>(execRegion.getLoc());
2246 rewriter.setInsertionPointToEnd(seqOp.getBodyBlock());
2248 for (
auto &execBlock : execRegion.getRegion().getBlocks()) {
2250 rewriter, path, seqOp.getBodyBlock(), &execBlock);
2252 return WalkResult::interrupt();
2255 return WalkResult::advance();
2258 if (walkResult.wasInterrupted())
2260 }
else if (
auto *forSchedPtr = std::get_if<ForScheduleable>(&group);
2262 auto forOp = forSchedPtr->forOp;
2266 getState<ComponentLoweringState>().getForLoopInitGroups(forOp),
2267 forSchedPtr->bound, rewriter);
2268 rewriter.setInsertionPointToEnd(forCtrlOp.getBodyBlock());
2270 rewriter.create<calyx::SeqOp>(forOp.getOperation()->getLoc());
2271 auto *forBodyOpBlock = forBodyOp.getBodyBlock();
2274 if (LogicalResult res =
buildCFGControl(path, rewriter, forBodyOpBlock,
2275 block, forOp.getBodyBlock());
2280 rewriter.setInsertionPointToEnd(forBodyOpBlock);
2281 calyx::GroupOp forLatchGroup =
2282 getState<ComponentLoweringState>().getForLoopLatchGroup(forOp);
2283 rewriter.create<calyx::EnableOp>(forLatchGroup.getLoc(),
2284 forLatchGroup.getName());
2285 }
else if (
auto *ifSchedPtr = std::get_if<IfScheduleable>(&group);
2287 auto ifOp = ifSchedPtr->ifOp;
2289 Location loc = ifOp->getLoc();
2291 auto cond = ifOp.getCondition();
2293 FlatSymbolRefAttr symbolAttr =
nullptr;
2294 auto condReg = getState<ComponentLoweringState>().getCondReg(ifOp);
2296 auto condGroup = getState<ComponentLoweringState>()
2297 .getEvaluatingGroup<calyx::CombGroupOp>(cond);
2299 symbolAttr = FlatSymbolRefAttr::get(
2300 StringAttr::get(getContext(), condGroup.getSymName()));
2303 bool initElse = !ifOp.getElseRegion().empty();
2304 auto ifCtrlOp = rewriter.create<calyx::IfOp>(
2305 loc, cond, symbolAttr, initElse);
2307 rewriter.setInsertionPointToEnd(ifCtrlOp.getBodyBlock());
2310 rewriter.create<calyx::SeqOp>(ifOp.getThenRegion().getLoc());
2311 auto *thenSeqOpBlock = thenSeqOp.getBodyBlock();
2313 auto *thenBlock = &ifOp.getThenRegion().front();
2321 if (!ifOp.getResults().empty()) {
2322 rewriter.setInsertionPointToEnd(thenSeqOpBlock);
2323 calyx::GroupOp thenGroup =
2324 getState<ComponentLoweringState>().getThenGroup(ifOp);
2325 rewriter.create<calyx::EnableOp>(thenGroup.getLoc(),
2326 thenGroup.getName());
2329 if (!ifOp.getElseRegion().empty()) {
2330 rewriter.setInsertionPointToEnd(ifCtrlOp.getElseBody());
2333 rewriter.create<calyx::SeqOp>(ifOp.getElseRegion().getLoc());
2334 auto *elseSeqOpBlock = elseSeqOp.getBodyBlock();
2336 auto *elseBlock = &ifOp.getElseRegion().front();
2342 if (!ifOp.getResults().empty()) {
2343 rewriter.setInsertionPointToEnd(elseSeqOpBlock);
2344 calyx::GroupOp elseGroup =
2345 getState<ComponentLoweringState>().getElseGroup(ifOp);
2346 rewriter.create<calyx::EnableOp>(elseGroup.getLoc(),
2347 elseGroup.getName());
2350 }
else if (
auto *callSchedPtr = std::get_if<CallScheduleable>(&group)) {
2351 auto instanceOp = callSchedPtr->instanceOp;
2352 OpBuilder::InsertionGuard g(rewriter);
2353 auto callBody = rewriter.create<calyx::SeqOp>(instanceOp.getLoc());
2354 rewriter.setInsertionPointToStart(callBody.getBodyBlock());
2356 auto callee = callSchedPtr->callOp.getCallee();
2357 auto *calleeOp = SymbolTable::lookupNearestSymbolFrom(
2358 callSchedPtr->callOp.getOperation()->getParentOp(),
2359 StringAttr::get(rewriter.getContext(),
"func_" + callee.str()));
2360 FuncOp calleeFunc = dyn_cast_or_null<FuncOp>(calleeOp);
2362 auto instanceOpComp =
2363 llvm::cast<calyx::ComponentOp>(instanceOp.getReferencedComponent());
2364 auto *instanceOpLoweringState =
2367 SmallVector<Value, 4> instancePorts;
2368 SmallVector<Value, 4> inputPorts;
2369 SmallVector<Attribute, 4> refCells;
2370 for (
auto operandEnum : enumerate(callSchedPtr->callOp.getOperands())) {
2371 auto operand = operandEnum.value();
2372 auto index = operandEnum.index();
2373 if (!isa<MemRefType>(operand.getType())) {
2374 inputPorts.push_back(operand);
2378 auto memOpName = getState<ComponentLoweringState>()
2379 .getMemoryInterface(operand)
2381 auto memOpNameAttr =
2382 SymbolRefAttr::get(rewriter.getContext(), memOpName);
2383 Value argI = calleeFunc.getArgument(index);
2384 if (isa<MemRefType>(argI.getType())) {
2385 NamedAttrList namedAttrList;
2386 namedAttrList.append(
2387 rewriter.getStringAttr(
2388 instanceOpLoweringState->getMemoryInterface(argI)
2392 DictionaryAttr::get(rewriter.getContext(), namedAttrList));
2395 llvm::copy(instanceOp.getResults().take_front(inputPorts.size()),
2396 std::back_inserter(instancePorts));
2398 ArrayAttr refCellsAttr =
2399 ArrayAttr::get(rewriter.getContext(), refCells);
2401 rewriter.create<calyx::InvokeOp>(
2402 instanceOp.getLoc(), instanceOp.getSymName(), instancePorts,
2403 inputPorts, refCellsAttr, ArrayAttr::get(rewriter.getContext(), {}),
2404 ArrayAttr::get(rewriter.getContext(), {}));
2406 llvm_unreachable(
"Unknown scheduleable");
2417 const DenseSet<Block *> &path, Location loc,
2418 Block *from, Block *to,
2419 Block *parentCtrlBlock)
const {
2422 rewriter.setInsertionPointToEnd(parentCtrlBlock);
2423 auto preSeqOp = rewriter.create<calyx::SeqOp>(loc);
2424 rewriter.setInsertionPointToEnd(preSeqOp.getBodyBlock());
2426 getState<ComponentLoweringState>().getBlockArgGroups(from, to))
2427 rewriter.create<calyx::EnableOp>(barg.getLoc(), barg.getSymName());
2433 PatternRewriter &rewriter,
2434 mlir::Block *parentCtrlBlock,
2435 mlir::Block *preBlock,
2436 mlir::Block *block)
const {
2437 if (path.count(block) != 0)
2438 return preBlock->getTerminator()->emitError()
2439 <<
"CFG backedge detected. Loops must be raised to 'scf.while' or "
2440 "'scf.for' operations.";
2442 rewriter.setInsertionPointToEnd(parentCtrlBlock);
2443 LogicalResult bbSchedResult =
2445 if (bbSchedResult.failed())
2446 return bbSchedResult;
2449 auto successors = block->getSuccessors();
2450 auto nSuccessors = successors.size();
2451 if (nSuccessors > 0) {
2452 auto brOp = dyn_cast<BranchOpInterface>(block->getTerminator());
2454 if (nSuccessors > 1) {
2458 assert(nSuccessors == 2 &&
2459 "only conditional branches supported for now...");
2461 auto cond = brOp->getOperand(0);
2462 auto condGroup = getState<ComponentLoweringState>()
2463 .getEvaluatingGroup<calyx::CombGroupOp>(cond);
2464 auto symbolAttr = FlatSymbolRefAttr::get(
2465 StringAttr::get(getContext(), condGroup.getSymName()));
2467 auto ifOp = rewriter.create<calyx::IfOp>(
2468 brOp->getLoc(), cond, symbolAttr,
true);
2469 rewriter.setInsertionPointToStart(ifOp.getThenBody());
2470 auto thenSeqOp = rewriter.create<calyx::SeqOp>(brOp.getLoc());
2471 rewriter.setInsertionPointToStart(ifOp.getElseBody());
2472 auto elseSeqOp = rewriter.create<calyx::SeqOp>(brOp.getLoc());
2474 bool trueBrSchedSuccess =
2475 schedulePath(rewriter, path, brOp.getLoc(), block, successors[0],
2476 thenSeqOp.getBodyBlock())
2478 bool falseBrSchedSuccess =
true;
2479 if (trueBrSchedSuccess) {
2480 falseBrSchedSuccess =
2481 schedulePath(rewriter, path, brOp.getLoc(), block, successors[1],
2482 elseSeqOp.getBodyBlock())
2486 return success(trueBrSchedSuccess && falseBrSchedSuccess);
2489 return schedulePath(rewriter, path, brOp.getLoc(), block,
2490 successors.front(), parentCtrlBlock);
2500 const SmallVector<calyx::GroupOp> &initGroups)
const {
2501 PatternRewriter::InsertionGuard g(rewriter);
2502 auto parOp = rewriter.create<calyx::ParOp>(loc);
2503 rewriter.setInsertionPointToStart(parOp.getBodyBlock());
2504 for (calyx::GroupOp group : initGroups)
2505 rewriter.create<calyx::EnableOp>(group.getLoc(), group.getName());
2509 SmallVector<calyx::GroupOp> initGroups,
2510 PatternRewriter &rewriter)
const {
2511 Location loc = whileOp.
getLoc();
2518 auto condGroup = getState<ComponentLoweringState>()
2519 .getEvaluatingGroup<calyx::CombGroupOp>(cond);
2520 auto symbolAttr = FlatSymbolRefAttr::get(
2521 StringAttr::get(getContext(), condGroup.getSymName()));
2522 return rewriter.create<calyx::WhileOp>(loc, cond, symbolAttr);
2526 SmallVector<calyx::GroupOp>
const &initGroups,
2528 PatternRewriter &rewriter)
const {
2529 Location loc = forOp.
getLoc();
2535 return rewriter.create<calyx::RepeatOp>(loc, bound);
2542 using FuncOpPartialLoweringPattern::FuncOpPartialLoweringPattern;
2545 PatternRewriter &)
const override {
2546 funcOp.walk([&](scf::IfOp op) {
2547 for (
auto res : getState<ComponentLoweringState>().getResultRegs(op))
2548 op.getOperation()->getResults()[res.first].replaceAllUsesWith(
2549 res.second.getOut());
2552 funcOp.walk([&](scf::WhileOp op) {
2561 getState<ComponentLoweringState>().getWhileLoopIterRegs(whileOp))
2562 whileOp.
getOperation()->getResults()[res.first].replaceAllUsesWith(
2563 res.second.getOut());
2566 funcOp.walk([&](memref::LoadOp loadOp) {
2572 loadOp.getResult().replaceAllUsesWith(
2573 getState<ComponentLoweringState>()
2574 .getMemoryInterface(loadOp.getMemref())
2585 using FuncOpPartialLoweringPattern::FuncOpPartialLoweringPattern;
2588 PatternRewriter &rewriter)
const override {
2589 rewriter.eraseOp(funcOp);
2595 PatternRewriter &rewriter)
const override {
56namespace scftocalyx {
…}
2609class SCFToCalyxPass :
public circt::impl::SCFToCalyxBase<SCFToCalyxPass> {
2611 SCFToCalyxPass(std::string topLevelFunction)
2613 this->topLevelFunctionOpt = topLevelFunction;
2615 void runOnOperation()
override;
2617 LogicalResult setTopLevelFunction(mlir::ModuleOp moduleOp,
2618 std::string &topLevelFunction) {
2619 if (!topLevelFunctionOpt.empty()) {
2620 if (SymbolTable::lookupSymbolIn(moduleOp, topLevelFunctionOpt) ==
2622 moduleOp.emitError() <<
"Top level function '" << topLevelFunctionOpt
2623 <<
"' not found in module.";
2626 topLevelFunction = topLevelFunctionOpt;
2630 auto funcOps = moduleOp.getOps<FuncOp>();
2631 if (std::distance(funcOps.begin(), funcOps.end()) == 1)
2632 topLevelFunction = (*funcOps.begin()).getSymName().str();
2634 moduleOp.emitError()
2635 <<
"Module contains multiple functions, but no top level "
2636 "function was set. Please see --top-level-function";
2641 return createOptNewTopLevelFn(moduleOp, topLevelFunction);
2644 struct LoweringPattern {
2645 enum class Strategy { Once, Greedy };
2654 LogicalResult labelEntryPoint(StringRef topLevelFunction) {
2658 using OpRewritePattern::OpRewritePattern;
2659 LogicalResult matchAndRewrite(mlir::ModuleOp,
2660 PatternRewriter &)
const override {
2665 ConversionTarget target(getContext());
2666 target.addLegalDialect<calyx::CalyxDialect>();
2667 target.addLegalDialect<scf::SCFDialect>();
2668 target.addIllegalDialect<hw::HWDialect>();
2669 target.addIllegalDialect<comb::CombDialect>();
2672 target.addIllegalDialect<FuncDialect>();
2673 target.addIllegalDialect<ArithDialect>();
2675 AddIOp, SelectOp, SubIOp, CmpIOp, ShLIOp, ShRUIOp, ShRSIOp, AndIOp,
2676 XOrIOp, OrIOp, ExtUIOp, TruncIOp, CondBranchOp, BranchOp, MulIOp,
2677 DivUIOp, DivSIOp, RemUIOp, RemSIOp, ReturnOp, arith::ConstantOp,
2678 IndexCastOp, BitcastOp, FuncOp, ExtSIOp, CallOp, AddFOp, SubFOp, MulFOp,
2679 CmpFOp, FPToSIOp, SIToFPOp, DivFOp, math::SqrtOp>();
2681 RewritePatternSet legalizePatterns(&getContext());
2682 legalizePatterns.add<DummyPattern>(&getContext());
2683 DenseSet<Operation *> legalizedOps;
2684 if (applyPartialConversion(getOperation(), target,
2685 std::move(legalizePatterns))
2696 template <
typename TPattern,
typename... PatternArgs>
2697 void addOncePattern(SmallVectorImpl<LoweringPattern> &
patterns,
2698 PatternArgs &&...args) {
2699 RewritePatternSet ps(&getContext());
2702 LoweringPattern{std::move(ps), LoweringPattern::Strategy::Once});
2705 template <
typename TPattern,
typename... PatternArgs>
2706 void addGreedyPattern(SmallVectorImpl<LoweringPattern> &
patterns,
2707 PatternArgs &&...args) {
2708 RewritePatternSet ps(&getContext());
2709 ps.add<TPattern>(&getContext(), args...);
2711 LoweringPattern{std::move(ps), LoweringPattern::Strategy::Greedy});
2714 LogicalResult runPartialPattern(RewritePatternSet &
pattern,
bool runOnce) {
2716 "Should only apply 1 partial lowering pattern at once");
2722 GreedyRewriteConfig config;
2723 config.setRegionSimplificationLevel(
2724 mlir::GreedySimplifyRegionLevel::Disabled);
2726 config.setMaxIterations(1);
2731 (void)applyPatternsGreedily(getOperation(), std::move(
pattern), config);
2740 FuncOp createNewTopLevelFn(ModuleOp moduleOp, std::string &baseName) {
2741 std::string newName =
"main";
2743 if (
auto *existingMainOp = SymbolTable::lookupSymbolIn(moduleOp, newName)) {
2744 auto existingMainFunc = dyn_cast<FuncOp>(existingMainOp);
2745 if (existingMainFunc ==
nullptr) {
2746 moduleOp.emitError() <<
"Symbol 'main' exists but is not a function";
2749 unsigned counter = 0;
2750 std::string newOldName = baseName;
2751 while (SymbolTable::lookupSymbolIn(moduleOp, newOldName))
2752 newOldName = llvm::join_items(
"_", baseName, std::to_string(++counter));
2753 existingMainFunc.setName(newOldName);
2754 if (baseName ==
"main")
2755 baseName = newOldName;
2759 OpBuilder builder(moduleOp.getContext());
2760 builder.setInsertionPointToStart(moduleOp.getBody());
2762 FunctionType funcType = builder.getFunctionType({}, {});
2765 builder.create<FuncOp>(moduleOp.getLoc(), newName, funcType))
2775 void insertCallFromNewTopLevel(OpBuilder &builder, FuncOp caller,
2777 if (caller.getBody().empty()) {
2778 caller.addEntryBlock();
2781 Block *callerEntryBlock = &caller.getBody().front();
2782 builder.setInsertionPointToStart(callerEntryBlock);
2786 SmallVector<Type, 4> nonMemRefCalleeArgTypes;
2787 for (
auto arg : callee.getArguments()) {
2788 if (!isa<MemRefType>(arg.getType())) {
2789 nonMemRefCalleeArgTypes.push_back(arg.getType());
2793 for (Type type : nonMemRefCalleeArgTypes) {
2794 callerEntryBlock->addArgument(type, caller.getLoc());
2797 FunctionType callerFnType = caller.getFunctionType();
2798 SmallVector<Type, 4> updatedCallerArgTypes(
2799 caller.getFunctionType().getInputs());
2800 updatedCallerArgTypes.append(nonMemRefCalleeArgTypes.begin(),
2801 nonMemRefCalleeArgTypes.end());
2802 caller.setType(FunctionType::get(caller.getContext(), updatedCallerArgTypes,
2803 callerFnType.getResults()));
2805 Block *calleeFnBody = &callee.getBody().front();
2806 unsigned originalCalleeArgNum = callee.getArguments().size();
2808 SmallVector<Value, 4> extraMemRefArgs;
2809 SmallVector<Type, 4> extraMemRefArgTypes;
2810 SmallVector<Value, 4> extraMemRefOperands;
2811 SmallVector<Operation *, 4> opsToModify;
2812 for (
auto &op : callee.getBody().getOps()) {
2813 if (isa<memref::AllocaOp, memref::AllocOp, memref::GetGlobalOp>(op))
2814 opsToModify.push_back(&op);
2819 builder.setInsertionPointToEnd(callerEntryBlock);
2820 for (
auto *op : opsToModify) {
2823 TypeSwitch<Operation *>(op)
2824 .Case<memref::AllocaOp>([&](memref::AllocaOp allocaOp) {
2825 newOpRes = builder.create<memref::AllocaOp>(callee.getLoc(),
2826 allocaOp.getType());
2828 .Case<memref::AllocOp>([&](memref::AllocOp allocOp) {
2829 newOpRes = builder.create<memref::AllocOp>(callee.getLoc(),
2832 .Case<memref::GetGlobalOp>([&](memref::GetGlobalOp getGlobalOp) {
2833 newOpRes = builder.create<memref::GetGlobalOp>(
2834 caller.getLoc(), getGlobalOp.getType(), getGlobalOp.getName());
2836 .Default([&](Operation *defaultOp) {
2837 llvm::report_fatal_error(
"Unsupported operation in TypeSwitch");
2839 extraMemRefOperands.push_back(newOpRes);
2841 calleeFnBody->addArgument(newOpRes.getType(), callee.getLoc());
2842 BlockArgument newBodyArg = calleeFnBody->getArguments().back();
2843 op->getResult(0).replaceAllUsesWith(newBodyArg);
2845 extraMemRefArgs.push_back(newBodyArg);
2846 extraMemRefArgTypes.push_back(newBodyArg.getType());
2849 SmallVector<Type, 4> updatedCalleeArgTypes(
2850 callee.getFunctionType().getInputs());
2851 updatedCalleeArgTypes.append(extraMemRefArgTypes.begin(),
2852 extraMemRefArgTypes.end());
2853 callee.setType(FunctionType::get(callee.getContext(), updatedCalleeArgTypes,
2854 callee.getFunctionType().getResults()));
2856 unsigned otherArgsCount = 0;
2857 SmallVector<Value, 4> calleeArgFnOperands;
2858 builder.setInsertionPointToStart(callerEntryBlock);
2859 for (
auto arg : callee.getArguments().take_front(originalCalleeArgNum)) {
2860 if (isa<MemRefType>(arg.getType())) {
2861 auto memrefType = cast<MemRefType>(arg.getType());
2863 builder.create<memref::AllocOp>(callee.getLoc(), memrefType);
2864 calleeArgFnOperands.push_back(allocOp);
2866 auto callerArg = callerEntryBlock->getArgument(otherArgsCount++);
2867 calleeArgFnOperands.push_back(callerArg);
2871 SmallVector<Value, 4> fnOperands;
2872 fnOperands.append(calleeArgFnOperands.begin(), calleeArgFnOperands.end());
2873 fnOperands.append(extraMemRefOperands.begin(), extraMemRefOperands.end());
2875 SymbolRefAttr::get(builder.getContext(), callee.getSymName());
2876 auto resultTypes = callee.getResultTypes();
2878 builder.setInsertionPointToEnd(callerEntryBlock);
2879 builder.create<CallOp>(caller.getLoc(), calleeName, resultTypes,
2881 builder.create<ReturnOp>(caller.getLoc());
2887 LogicalResult createOptNewTopLevelFn(ModuleOp moduleOp,
2888 std::string &topLevelFunction) {
2889 auto hasMemrefArguments = [](FuncOp func) {
2891 func.getArguments().begin(), func.getArguments().end(),
2892 [](BlockArgument arg) { return isa<MemRefType>(arg.getType()); });
2898 auto funcOps = moduleOp.getOps<FuncOp>();
2899 bool hasMemrefArgsInTopLevel =
2900 std::any_of(funcOps.begin(), funcOps.end(), [&](
auto funcOp) {
2901 return funcOp.getName() == topLevelFunction &&
2902 hasMemrefArguments(funcOp);
2905 if (hasMemrefArgsInTopLevel) {
2906 auto newTopLevelFunc = createNewTopLevelFn(moduleOp, topLevelFunction);
2907 if (!newTopLevelFunc)
2910 OpBuilder builder(moduleOp.getContext());
2911 Operation *oldTopLevelFuncOp =
2912 SymbolTable::lookupSymbolIn(moduleOp, topLevelFunction);
2913 if (
auto oldTopLevelFunc = dyn_cast<FuncOp>(oldTopLevelFuncOp))
2914 insertCallFromNewTopLevel(builder, newTopLevelFunc, oldTopLevelFunc);
2916 moduleOp.emitOpError(
"Original top-level function not found!");
2919 topLevelFunction =
"main";
2926void SCFToCalyxPass::runOnOperation() {
2931 std::string topLevelFunction;
2932 if (failed(setTopLevelFunction(getOperation(), topLevelFunction))) {
2933 signalPassFailure();
2938 if (failed(labelEntryPoint(topLevelFunction))) {
2939 signalPassFailure();
2942 loweringState = std::make_shared<calyx::CalyxLoweringState>(getOperation(),
2953 DenseMap<FuncOp, calyx::ComponentOp> funcMap;
2954 SmallVector<LoweringPattern, 8> loweringPatterns;
2958 addOncePattern<FuncOpConversion>(loweringPatterns, patternState, funcMap,
2962 addGreedyPattern<InlineExecuteRegionOpPattern>(loweringPatterns);
2965 addOncePattern<calyx::ConvertIndexTypes>(loweringPatterns, patternState,
2969 addOncePattern<calyx::BuildBasicBlockRegs>(loweringPatterns, patternState,
2972 addOncePattern<calyx::BuildCallInstance>(loweringPatterns, patternState,
2976 addOncePattern<calyx::BuildReturnRegs>(loweringPatterns, patternState,
2982 addOncePattern<BuildWhileGroups>(loweringPatterns, patternState, funcMap,
2988 addOncePattern<BuildForGroups>(loweringPatterns, patternState, funcMap,
2991 addOncePattern<BuildIfGroups>(loweringPatterns, patternState, funcMap,
3001 addOncePattern<BuildOpGroups>(loweringPatterns, patternState, funcMap,
3007 addOncePattern<BuildControl>(loweringPatterns, patternState, funcMap,
3012 addOncePattern<calyx::InlineCombGroups>(loweringPatterns, patternState,
3017 addOncePattern<LateSSAReplacement>(loweringPatterns, patternState, funcMap,
3023 addGreedyPattern<calyx::EliminateUnusedCombGroups>(loweringPatterns);
3027 addOncePattern<calyx::RewriteMemoryAccesses>(loweringPatterns, patternState,
3032 addOncePattern<CleanupFuncOps>(loweringPatterns, patternState, funcMap,
3036 for (
auto &pat : loweringPatterns) {
3039 pat.strategy == LoweringPattern::Strategy::Once);
3042 signalPassFailure();
3049 RewritePatternSet cleanupPatterns(&getContext());
3053 applyPatternsGreedily(getOperation(), std::move(cleanupPatterns)))) {
3054 signalPassFailure();
3058 if (ciderSourceLocationMetadata) {
3061 SmallVector<Attribute, 16> sourceLocations;
3062 getOperation()->walk([&](calyx::ComponentOp component) {
3066 MLIRContext *context = getOperation()->getContext();
3067 getOperation()->setAttr(
"calyx.metadata",
3068 ArrayAttr::get(context, sourceLocations));
3077std::unique_ptr<OperationPass<ModuleOp>>
3079 return std::make_unique<SCFToCalyxPass>(topLevelFunction);
assert(baseType &&"element must be base type")
static Block * getBodyBlock(FModuleLike mod)
RewritePatternSet pattern
std::shared_ptr< calyx::CalyxLoweringState > loweringState
LogicalResult partialPatternRes
An interface for conversion passes that lower Calyx programs.
std::string irName(ValueOrBlock &v)
Returns a meaningful name for a value within the program scope.
std::string blockName(Block *b)
Returns a meaningful name for a block within the program scope (removes the ^ prefix from block names...
StringRef getTopLevelFunction() const
Returns the name of the top-level function in the source program.
T * getState(calyx::ComponentOp op)
Returns the component lowering state associated with op.
void setFuncOpResultMapping(const DenseMap< unsigned, unsigned > &mapping)
Assign a mapping between the source funcOp result indices and the corresponding output port indices o...
std::string getUniqueName(StringRef prefix)
Returns a unique name within compOp with the provided prefix.
calyx::ComponentOp component
The component which this lowering state is associated to.
void registerMemoryInterface(Value memref, const calyx::MemoryInterface &memoryInterface)
Registers a memory interface as being associated with a memory identified by 'memref'.
calyx::ComponentOp getComponentOp()
Returns the calyx::ComponentOp associated with this lowering state.
void setDataField(StringRef name, llvm::json::Array data)
ComponentLoweringStateInterface(calyx::ComponentOp component)
void setFormat(StringRef name, std::string numType, bool isSigned, unsigned width)
FuncOpPartialLoweringPatterns are patterns which intend to match on FuncOps and then perform their ow...
calyx::ComponentOp getComponent() const
Returns the component operation associated with the currently executing partial lowering.
DenseMap< mlir::func::FuncOp, calyx::ComponentOp > & functionMapping
CalyxLoweringState & loweringState() const
Return the calyx lowering state for this pattern.
FuncOpPartialLoweringPattern(MLIRContext *context, LogicalResult &resRef, PatternApplicationState &patternState, DenseMap< mlir::func::FuncOp, calyx::ComponentOp > &map, calyx::CalyxLoweringState &state)
calyx::GroupOp getLoopLatchGroup(ScfWhileOp op)
Retrieve the loop latch group registered for op.
void setLoopLatchGroup(ScfWhileOp op, calyx::GroupOp group)
Registers grp to be the loop latch group of op.
calyx::RegisterOp getLoopIterReg(ScfForOp op, unsigned idx)
Return a mapping of block argument indices to block argument.
void addLoopIterReg(ScfWhileOp op, calyx::RegisterOp reg, unsigned idx)
Register reg as being the idx'th iter_args register for 'op'.
void setLoopInitGroups(ScfWhileOp op, SmallVector< calyx::GroupOp > groups)
Registers groups to be the loop init groups of op.
SmallVector< calyx::GroupOp > getLoopInitGroups(ScfWhileOp op)
Retrieve the loop init groups registered for op.
calyx::GroupOp buildLoopIterArgAssignments(OpBuilder &builder, ScfWhileOp op, calyx::ComponentOp componentOp, Twine uniqueSuffix, MutableArrayRef< OpOperand > ops)
Creates a new group that assigns the 'ops' values to the iter arg registers of the loop operation.
const DenseMap< unsigned, calyx::RegisterOp > & getLoopIterRegs(ScfWhileOp op)
Return a mapping of block argument indices to block argument.
PatternApplicationState & patternState
scf::ForOp getOperation()
Location getLoc() override
RepeatOpInterface(scf::ForOp op)
Holds common utilities used for scheduling when lowering to Calyx.
scf::WhileOp getOperation()
WhileOpInterface(scf::WhileOp op)
Location getLoc() override
Builds a control schedule by traversing the CFG of the function and associating this with the previou...
calyx::RepeatOp buildForCtrlOp(ScfForOp forOp, SmallVector< calyx::GroupOp > const &initGroups, uint64_t bound, PatternRewriter &rewriter) const
LogicalResult partiallyLowerFuncToComp(FuncOp funcOp, PatternRewriter &rewriter) const override
LogicalResult schedulePath(PatternRewriter &rewriter, const DenseSet< Block * > &path, Location loc, Block *from, Block *to, Block *parentCtrlBlock) const
Schedules a block by inserting a branch argument assignment block (if any) before recursing into the ...
calyx::WhileOp buildWhileCtrlOp(ScfWhileOp whileOp, SmallVector< calyx::GroupOp > initGroups, PatternRewriter &rewriter) const
LogicalResult scheduleBasicBlock(PatternRewriter &rewriter, const DenseSet< Block * > &path, mlir::Block *parentCtrlBlock, mlir::Block *block) const
Sequentially schedules the groups that registered themselves with 'block'.
LogicalResult buildCFGControl(DenseSet< Block * > path, PatternRewriter &rewriter, mlir::Block *parentCtrlBlock, mlir::Block *preBlock, mlir::Block *block) const
void insertParInitGroups(PatternRewriter &rewriter, Location loc, const SmallVector< calyx::GroupOp > &initGroups) const
In BuildForGroups, a register is created for the iteration argument of the for op.
LogicalResult partiallyLowerFuncToComp(FuncOp funcOp, PatternRewriter &rewriter) const override
LogicalResult partiallyLowerFuncToComp(FuncOp funcOp, PatternRewriter &rewriter) const override
Iterate through the operations of a source function and instantiate components or primitives based on...
BuildOpGroups(MLIRContext *context, LogicalResult &resRef, calyx::PatternApplicationState &patternState, DenseMap< mlir::func::FuncOp, calyx::ComponentOp > &map, calyx::CalyxLoweringState &state, mlir::Pass::Option< std::string > &writeJsonOpt)
LogicalResult buildCmpIOpHelper(PatternRewriter &rewriter, CmpIOp op) const
void setupCmpIOp(PatternRewriter &rewriter, CmpIOp cmpIOp, Operation *group, calyx::RegisterOp &condReg, calyx::RegisterOp &resReg, TCalyxLibOp calyxOp) const
LogicalResult buildFpIntTypeCastOp(PatternRewriter &rewriter, TSrcOp op, unsigned inputWidth, unsigned outputWidth, StringRef signedPort) const
TGroupOp createGroupForOp(PatternRewriter &rewriter, Operation *op) const
Creates a group named by the basic block which the input op resides in.
LogicalResult buildLibraryOp(PatternRewriter &rewriter, TSrcOp op) const
buildLibraryOp which provides in- and output types based on the operands and results of the op argume...
LogicalResult buildOp(PatternRewriter &rewriter, scf::YieldOp yieldOp) const
Op builder specializations.
calyx::RegisterOp createSignalRegister(PatternRewriter &rewriter, Value signal, bool invert, StringRef nameSuffix, calyx::CompareFOpIEEE754 calyxCmpFOp, calyx::GroupOp group) const
void assignAddressPorts(PatternRewriter &rewriter, Location loc, calyx::GroupInterface group, calyx::MemoryInterface memoryInterface, Operation::operand_range addressValues) const
Creates assignments within the provided group to the address ports of the memoryOp based on the provi...
LogicalResult buildLibraryOp(PatternRewriter &rewriter, TSrcOp op, TypeRange srcTypes, TypeRange dstTypes) const
buildLibraryOp will build a TCalyxLibOp inside a TGroupOp based on the source operation TSrcOp.
LogicalResult partiallyLowerFuncToComp(FuncOp funcOp, PatternRewriter &rewriter) const override
LogicalResult buildLibraryBinaryPipeOp(PatternRewriter &rewriter, TSrcOp op, TOpType opPipe, Value out) const
buildLibraryBinaryPipeOp will build a TCalyxLibBinaryPipeOp, to deal with MulIOp, DivUIOp and RemUIOp...
mlir::Pass::Option< std::string > & writeJson
In BuildWhileGroups, a register is created for each iteration argumenet of the while op.
LogicalResult partiallyLowerFuncToComp(FuncOp funcOp, PatternRewriter &rewriter) const override
Erases FuncOp operations.
LogicalResult matchAndRewrite(FuncOp funcOp, PatternRewriter &rewriter) const override
LogicalResult partiallyLowerFuncToComp(FuncOp funcOp, PatternRewriter &rewriter) const override
Handles the current state of lowering of a Calyx component.
ComponentLoweringState(calyx::ComponentOp component)
void setForLoopInitGroups(ScfForOp op, SmallVector< calyx::GroupOp > groups)
calyx::GroupOp buildForLoopIterArgAssignments(OpBuilder &builder, ScfForOp op, calyx::ComponentOp componentOp, Twine uniqueSuffix, MutableArrayRef< OpOperand > ops)
void setForLoopLatchGroup(ScfForOp op, calyx::GroupOp group)
SmallVector< calyx::GroupOp > getForLoopInitGroups(ScfForOp op)
void addForLoopIterReg(ScfForOp op, calyx::RegisterOp reg, unsigned idx)
calyx::GroupOp getForLoopLatchGroup(ScfForOp op)
calyx::RegisterOp getForLoopIterReg(ScfForOp op, unsigned idx)
const DenseMap< unsigned, calyx::RegisterOp > & getForLoopIterRegs(ScfForOp op)
DenseMap< Operation *, calyx::GroupOp > elseGroup
DenseMap< Operation *, calyx::GroupOp > thenGroup
void setCondReg(scf::IfOp op, calyx::RegisterOp regOp)
const DenseMap< unsigned, calyx::RegisterOp > & getResultRegs(scf::IfOp op)
void setElseGroup(scf::IfOp op, calyx::GroupOp group)
void setResultRegs(scf::IfOp op, calyx::RegisterOp reg, unsigned idx)
void setThenGroup(scf::IfOp op, calyx::GroupOp group)
DenseMap< Operation *, DenseMap< unsigned, calyx::RegisterOp > > resultRegs
calyx::RegisterOp getResultRegs(scf::IfOp op, unsigned idx)
calyx::RegisterOp getCondReg(scf::IfOp op)
calyx::GroupOp getThenGroup(scf::IfOp op)
DenseMap< Operation *, calyx::RegisterOp > condReg
calyx::GroupOp getElseGroup(scf::IfOp op)
Inlines Calyx ExecuteRegionOp operations within their parent blocks.
LogicalResult matchAndRewrite(scf::ExecuteRegionOp execOp, PatternRewriter &rewriter) const override
LateSSAReplacement contains various functions for replacing SSA values that were not replaced during ...
LogicalResult partiallyLowerFuncToComp(FuncOp funcOp, PatternRewriter &) const override
std::optional< int64_t > getBound() override
Block::BlockArgListType getBodyArgs() override
Block * getBodyBlock() override
Block * getBodyBlock() override
ScfWhileOp(scf::WhileOp op)
Block::BlockArgListType getBodyArgs() override
Value getConditionValue() override
std::optional< int64_t > getBound() override
Block * getConditionBlock() override
Stores the state information for condition checks involving sequential computation.
void setSeqResReg(Operation *op, calyx::RegisterOp reg)
calyx::RegisterOp getSeqResReg(Operation *op)
DenseMap< Operation *, calyx::RegisterOp > resultRegs
calyx::GroupOp buildWhileLoopIterArgAssignments(OpBuilder &builder, ScfWhileOp op, calyx::ComponentOp componentOp, Twine uniqueSuffix, MutableArrayRef< OpOperand > ops)
void setWhileLoopInitGroups(ScfWhileOp op, SmallVector< calyx::GroupOp > groups)
SmallVector< calyx::GroupOp > getWhileLoopInitGroups(ScfWhileOp op)
void addWhileLoopIterReg(ScfWhileOp op, calyx::RegisterOp reg, unsigned idx)
void setWhileLoopLatchGroup(ScfWhileOp op, calyx::GroupOp group)
const DenseMap< unsigned, calyx::RegisterOp > & getWhileLoopIterRegs(ScfWhileOp op)
calyx::GroupOp getWhileLoopLatchGroup(ScfWhileOp op)
bool parentIsSeqCell(Value value)
void addMandatoryComponentPorts(PatternRewriter &rewriter, SmallVectorImpl< calyx::PortInfo > &ports)
void buildAssignmentsForRegisterWrite(OpBuilder &builder, calyx::GroupOp groupOp, calyx::ComponentOp componentOp, calyx::RegisterOp ®, Value inputValue)
Creates register assignment operations within the provided groupOp.
DenseMap< const mlir::RewritePattern *, SmallPtrSet< Operation *, 16 > > PatternApplicationState
Extra state that is passed to all PartialLoweringPatterns so they can record when they have run on an...
PredicateInfo getPredicateInfo(mlir::arith::CmpFPredicate pred)
Type normalizeType(OpBuilder &builder, Type type)
LogicalResult applyModuleOpConversion(mlir::ModuleOp, StringRef topLevelFunction)
Helper to update the top-level ModuleOp to set the entrypoing function.
WalkResult getCiderSourceLocationMetadata(calyx::ComponentOp component, SmallVectorImpl< Attribute > &sourceLocations)
bool matchConstantOp(Operation *op, APInt &value)
unsigned handleZeroWidth(int64_t dim)
hw::ConstantOp createConstant(Location loc, OpBuilder &builder, ComponentOp component, size_t width, size_t value)
A helper function to create constants in the HW dialect.
bool noStoresToMemory(Value memoryReference)
bool singleLoadFromMemory(Value memoryReference)
Type toBitVector(T type)
Performs a bit cast from a non-signless integer type value, such as a floating point value,...
std::string getInstanceName(mlir::func::CallOp callOp)
A helper function to get the instance name.
Value createOrFoldNot(Location loc, Value value, OpBuilder &builder, bool twoState=false)
Create a `‘Not’' gate on a value.
static constexpr std::string_view sPortNameAttr
static constexpr std::string_view unrolledParallelAttr
static LogicalResult buildAllocOp(ComponentLoweringState &componentState, PatternRewriter &rewriter, TAllocOp allocOp)
std::variant< calyx::GroupOp, WhileScheduleable, ForScheduleable, IfScheduleable, CallScheduleable, ParScheduleable > Scheduleable
A variant of types representing scheduleable operations.
The InstanceGraph op interface, see InstanceGraphInterface.td for more details.
std::unique_ptr< OperationPass< ModuleOp > > createSCFToCalyxPass(std::string topLevelFunction="")
Create an SCF to Calyx conversion pass.
When building groups which contain accesses to multiple sequential components, a group_done op is cre...
GroupDoneOp's are terminator operations and should therefore be the last operator in a group.
This holds information about the port for either a Component or Cell.
Predicate information for the floating point comparisons.
calyx::InstanceOp instanceOp
Instance for invoking.
ScfForOp forOp
For operation to schedule.
Creates a new Calyx component for each FuncOp in the program.
LogicalResult partiallyLowerFuncToComp(FuncOp funcOp, PatternRewriter &rewriter) const override
scf::ParallelOp parOp
Parallel operation to schedule.
ScfWhileOp whileOp
While operation to schedule.