14 #include "../PassDetail.h"
27 #include "mlir/IR/Builders.h"
28 #include "mlir/IR/DialectImplementation.h"
29 #include "mlir/IR/ImplicitLocOpBuilder.h"
30 #include "mlir/IR/Threading.h"
31 #include "mlir/Pass/Pass.h"
32 #include "mlir/Transforms/DialectConversion.h"
33 #include "llvm/ADT/IntervalMap.h"
34 #include "llvm/ADT/TypeSwitch.h"
35 #include "llvm/Support/Mutex.h"
37 #define DEBUG_TYPE "lower-seq-to-sv"
39 using namespace circt;
42 using llvm::MapVector;
45 #define GEN_PASS_DEF_LOWERSEQTOSV
46 #include "circt/Conversion/Passes.h.inc"
48 struct SeqToSVPass :
public impl::LowerSeqToSVBase<SeqToSVPass> {
50 void runOnOperation()
override;
52 using LowerSeqToSVBase<SeqToSVPass>::lowerToAlwaysFF;
53 using LowerSeqToSVBase<SeqToSVPass>::disableRegRandomization;
54 using LowerSeqToSVBase<SeqToSVPass>::emitSeparateAlwaysBlocks;
55 using LowerSeqToSVBase<SeqToSVPass>::LowerSeqToSVBase;
56 using LowerSeqToSVBase<SeqToSVPass>::numSubaccessRestored;
63 template <
typename OpTy>
66 CompRegLower(TypeConverter &typeConverter, MLIRContext *context,
69 lowerToAlwaysFF(lowerToAlwaysFF) {}
74 matchAndRewrite(OpTy
reg, OpAdaptor adaptor,
75 ConversionPatternRewriter &rewriter)
const final {
76 Location loc =
reg.getLoc();
79 ConversionPattern::getTypeConverter()->convertType(
reg.getType());
81 auto svReg = rewriter.create<
sv::RegOp>(loc, regTy,
reg.getNameAttr(),
82 reg.getInnerSymAttr(),
83 reg.getPowerOnValue());
84 svReg->setDialectAttrs(
reg->getDialectAttrs());
90 auto assignValue = [&] {
91 createAssign(rewriter,
reg.getLoc(), svReg,
reg);
93 auto assignReset = [&] {
94 rewriter.create<sv::PAssignOp>(loc, svReg, adaptor.getResetValue());
97 if (adaptor.getReset() && adaptor.getResetValue()) {
98 if (lowerToAlwaysFF) {
99 rewriter.create<sv::AlwaysFFOp>(
100 loc, sv::EventControl::AtPosEdge, adaptor.getClk(),
101 ResetType::SyncReset, sv::EventControl::AtPosEdge,
102 adaptor.getReset(), assignValue, assignReset);
104 rewriter.create<sv::AlwaysOp>(
105 loc, sv::EventControl::AtPosEdge, adaptor.getClk(), [&] {
106 rewriter.create<sv::IfOp>(loc, adaptor.getReset(), assignReset,
111 if (lowerToAlwaysFF) {
112 rewriter.create<sv::AlwaysFFOp>(loc, sv::EventControl::AtPosEdge,
113 adaptor.getClk(), assignValue);
115 rewriter.create<sv::AlwaysOp>(loc, sv::EventControl::AtPosEdge,
116 adaptor.getClk(), assignValue);
120 rewriter.replaceOp(
reg, regVal);
125 void createAssign(ConversionPatternRewriter &rewriter, Location loc,
129 bool lowerToAlwaysFF;
134 void CompRegLower<CompRegOp>::createAssign(ConversionPatternRewriter &rewriter,
136 OpAdaptor
reg)
const {
137 rewriter.create<sv::PAssignOp>(loc, svReg,
reg.getInput());
141 void CompRegLower<CompRegClockEnabledOp>::createAssign(
142 ConversionPatternRewriter &rewriter, Location loc,
sv::RegOp svReg,
143 OpAdaptor
reg)
const {
144 rewriter.create<sv::IfOp>(loc,
reg.getClockEnable(), [&]() {
145 rewriter.create<sv::PAssignOp>(loc, svReg,
reg.getInput());
156 matchAndRewrite(ClockGateOp clockGate, OpAdaptor adaptor,
157 ConversionPatternRewriter &rewriter)
const final {
158 auto loc = clockGate.getLoc();
159 Value
clk = adaptor.getInput();
162 Value enable = adaptor.getEnable();
163 if (
auto te = adaptor.getTestEnable())
164 enable = rewriter.create<
comb::OrOp>(loc, enable, te);
167 Value enableLatch = rewriter.create<
sv::RegOp>(
168 loc, rewriter.getI1Type(), rewriter.getStringAttr(
"cg_en_latch"));
171 rewriter.create<sv::AlwaysOp>(
172 loc, llvm::SmallVector<sv::EventControl>{}, llvm::SmallVector<Value>{},
174 rewriter.create<sv::IfOp>(
176 rewriter.create<sv::PAssignOp>(loc, enableLatch, enable);
194 matchAndRewrite(ClockInverterOp op, OpAdaptor adaptor,
195 ConversionPatternRewriter &rewriter)
const final {
196 auto loc = op.getLoc();
197 Value
clk = adaptor.getInput();
199 StringAttr name = op->getAttrOfType<StringAttr>(
"sv.namehint");
201 auto newOp = rewriter.replaceOpWithNewOp<
comb::XorOp>(op,
clk, one);
203 rewriter.modifyOpInPlace(newOp,
204 [&] { newOp->setAttr(
"sv.namehint", name); });
217 matchAndRewrite(ClockMuxOp clockMux, OpAdaptor adaptor,
218 ConversionPatternRewriter &rewriter)
const final {
219 rewriter.replaceOpWithNewOp<
comb::MuxOp>(clockMux, adaptor.getCond(),
220 adaptor.getTrueClock(),
221 adaptor.getFalseClock(),
true);
227 struct SeqToSVTypeConverter :
public TypeConverter {
228 SeqToSVTypeConverter() {
229 addConversion([&](Type type) {
return type; });
230 addConversion([&](seq::ClockType type) {
233 addConversion([&](hw::StructType structTy) {
234 bool changed =
false;
236 SmallVector<hw::StructType::FieldInfo> newFields;
237 for (
auto field : structTy.getElements()) {
238 auto &newField = newFields.emplace_back();
239 newField.name = field.name;
240 newField.type = convertType(field.type);
241 if (field.type != newField.type)
250 addConversion([&](hw::ArrayType arrayTy) {
251 auto elementTy = arrayTy.getElementType();
253 if (elementTy != newElementTy)
258 addTargetMaterialization(
259 [&](mlir::OpBuilder &
builder, mlir::Type resultType,
261 mlir::Location loc) -> std::optional<mlir::Value> {
267 addSourceMaterialization(
268 [&](mlir::OpBuilder &
builder, mlir::Type resultType,
270 mlir::Location loc) -> std::optional<mlir::Value> {
279 template <
typename T>
285 matchAndRewrite(T op,
typename T::Adaptor adaptor,
286 ConversionPatternRewriter &rewriter)
const final {
288 if (Operation *inputOp = adaptor.getInput().getDefiningOp())
289 if (!isa<mlir::UnrealizedConversionCastOp>(inputOp))
291 rewriter.modifyOpInPlace(
292 inputOp, [&] { inputOp->setAttr(
"sv.namehint", name); });
294 rewriter.replaceOp(op, adaptor.getInput());
307 matchAndRewrite(ConstClockOp clockConst, OpAdaptor adaptor,
308 ConversionPatternRewriter &rewriter)
const final {
310 clockConst, APInt(1, clockConst.getValue() == ClockConst::High));
323 matchAndRewrite(ClockDividerOp clockDiv, OpAdaptor adaptor,
324 ConversionPatternRewriter &rewriter)
const final {
325 Location loc = clockDiv.getLoc();
328 if (clockDiv.getPow2()) {
332 Value output = clockDiv.getInput();
334 SmallVector<Value> regs;
335 for (
unsigned i = 0; i < clockDiv.getPow2(); ++i) {
337 loc, rewriter.getI1Type(),
338 rewriter.getStringAttr(
"clock_out_" + std::to_string(i)));
341 rewriter.create<sv::AlwaysOp>(
342 loc, sv::EventControl::AtPosEdge, output, [&] {
345 rewriter.create<sv::BPAssignOp>(loc,
reg, inverted);
353 rewriter.
create<sv::InitialOp>(loc, [&] {
354 for (Value
reg : regs) {
355 rewriter.
create<sv::BPAssignOp>(loc,
reg, zero);
360 rewriter.replaceOp(clockDiv, output);
369 if (hw::type_isa<ClockType>(ty))
372 if (
auto arrayTy = hw::type_dyn_cast<hw::ArrayType>(ty))
375 if (
auto structTy = hw::type_dyn_cast<hw::StructType>(ty)) {
376 for (
auto field : structTy.getElements())
387 if (
auto module = dyn_cast<hw::HWModuleLike>(op)) {
388 for (
auto port : module.getHWModuleType().getPorts())
393 bool allOperandsLowered = llvm::all_of(
394 op->getOperands(), [](
auto op) { return isLegalType(op.getType()); });
395 bool allResultsLowered = llvm::all_of(op->getResults(), [](
auto result) {
396 return isLegalType(result.getType());
398 return allOperandsLowered && allResultsLowered;
401 void SeqToSVPass::runOnOperation() {
402 auto circuit = getOperation();
403 MLIRContext *context = &getContext();
405 auto modules = llvm::to_vector(circuit.getOps<
HWModuleOp>());
410 auto uniqueMems = memLowering.collectMemories(modules);
411 MapVector<HWModuleOp, SmallVector<FirMemLowering::MemoryConfig>> memsByModule;
412 for (
auto &[config, memOps] : uniqueMems) {
414 auto genOp = memLowering.createMemoryModule(config, memOps);
417 for (
auto memOp : memOps) {
418 auto parent = memOp->getParentOfType<
HWModuleOp>();
419 memsByModule[parent].emplace_back(&config, genOp, memOp);
424 bool needsRegRandomization =
false;
425 bool needsMemRandomization =
false;
427 struct FragmentInfo {
428 bool needsRegFragment;
429 bool needsMemFragment;
431 DenseMap<HWModuleOp, FragmentInfo> moduleFragmentInfo;
432 llvm::sys::SmartMutex<true> fragmentsMutex;
434 mlir::parallelForEach(&getContext(), modules, [&](
HWModuleOp module) {
435 SeqToSVTypeConverter typeConverter;
436 FirRegLowering regLowering(typeConverter, module, disableRegRandomization,
437 emitSeparateAlwaysBlocks);
439 if (regLowering.needsRegRandomization()) {
440 if (!disableRegRandomization) {
441 llvm::sys::SmartScopedLock<true> lock(fragmentsMutex);
442 moduleFragmentInfo[module].needsRegFragment =
true;
444 needsRegRandomization =
true;
446 numSubaccessRestored += regLowering.numSubaccessRestored;
448 if (
auto *it = memsByModule.find(module); it != memsByModule.end()) {
449 memLowering.lowerMemoriesInModule(module, it->second);
450 if (!disableMemRandomization) {
451 llvm::sys::SmartScopedLock<true> lock(fragmentsMutex);
452 moduleFragmentInfo[module].needsMemFragment =
true;
454 needsMemRandomization =
true;
458 auto randomInitFragmentName =
460 auto randomInitRegFragmentName =
462 auto randomInitMemFragmentName =
465 for (
auto &[module, info] : moduleFragmentInfo) {
466 assert((info.needsRegFragment || info.needsMemFragment) &&
467 "module should use memories or registers");
469 SmallVector<Attribute> fragmentAttrs;
472 fragmentAttrs = llvm::to_vector(others);
474 if (info.needsRegFragment)
475 fragmentAttrs.push_back(randomInitRegFragmentName);
476 if (info.needsMemFragment)
477 fragmentAttrs.push_back(randomInitMemFragmentName);
478 fragmentAttrs.push_back(randomInitFragmentName);
485 SeqToSVTypeConverter typeConverter;
486 ConversionTarget target(*context);
487 target.addIllegalDialect<SeqDialect>();
488 target.markUnknownOpDynamicallyLegal(
isLegalOp);
490 RewritePatternSet
patterns(context);
491 patterns.add<CompRegLower<CompRegOp>>(typeConverter, context,
493 patterns.add<CompRegLower<CompRegClockEnabledOp>>(typeConverter, context,
495 patterns.add<ClockCastLowering<seq::FromClockOp>>(typeConverter, context);
496 patterns.add<ClockCastLowering<seq::ToClockOp>>(typeConverter, context);
497 patterns.add<ClockGateLowering>(typeConverter, context);
498 patterns.add<ClockInverterLowering>(typeConverter, context);
499 patterns.add<ClockMuxLowering>(typeConverter, context);
500 patterns.add<ClockDividerLowering>(typeConverter, context);
501 patterns.add<ClockConstLowering>(typeConverter, context);
504 if (failed(applyPartialConversion(circuit, target, std::move(
patterns))))
508 auto b = ImplicitLocOpBuilder::atBlockBegin(loc, circuit.getBody());
509 if (needsRegRandomization || needsMemRandomization) {
510 b.create<sv::MacroDeclOp>(
"ENABLE_INITIAL_REG_");
511 b.create<sv::MacroDeclOp>(
"ENABLE_INITIAL_MEM_");
512 if (needsRegRandomization) {
513 b.create<sv::MacroDeclOp>(
"FIRRTL_BEFORE_INITIAL");
514 b.create<sv::MacroDeclOp>(
"FIRRTL_AFTER_INITIAL");
516 if (needsMemRandomization)
517 b.create<sv::MacroDeclOp>(
"RANDOMIZE_MEM_INIT");
518 b.create<sv::MacroDeclOp>(
"RANDOMIZE_REG_INIT");
519 b.create<sv::MacroDeclOp>(
"RANDOMIZE");
520 b.create<sv::MacroDeclOp>(
"RANDOMIZE_DELAY");
521 b.create<sv::MacroDeclOp>(
"RANDOM");
522 b.create<sv::MacroDeclOp>(
"INIT_RANDOM");
523 b.create<sv::MacroDeclOp>(
"INIT_RANDOM_PROLOG_");
526 bool hasRegRandomization = needsRegRandomization && !disableRegRandomization;
527 bool hasMemRandomization = needsMemRandomization && !disableMemRandomization;
528 if (!hasRegRandomization && !hasMemRandomization)
533 for (Operation &op : *circuit.getBody()) {
534 if (!isa<sv::VerbatimOp, sv::IfDefOp>(&op)) {
535 b.setInsertionPoint(&op);
543 for (
auto sym : circuit.getOps<sv::MacroDeclOp>())
544 symbols.insert(sym.getName());
545 if (!symbols.count(
"SYNTHESIS"))
546 b.create<sv::MacroDeclOp>(
"SYNTHESIS");
547 if (!symbols.count(
"VERILATOR"))
548 b.create<sv::MacroDeclOp>(
"VERILATOR");
553 auto emitGuardedDefine = [&](StringRef guard, StringRef defName,
554 StringRef defineTrue =
"",
555 StringRef defineFalse = StringRef()) {
556 if (!defineFalse.data()) {
557 assert(defineTrue.data() &&
"didn't define anything");
559 guard, [&]() { b.create<sv::MacroDefOp>(defName, defineTrue); });
564 if (defineTrue.data())
565 b.create<sv::MacroDefOp>(defName, defineTrue);
567 [&]() { b.create<sv::MacroDefOp>(defName, defineFalse); });
572 auto emitGuard = [&](
const char *guard, llvm::function_ref<void(
void)> body) {
574 guard, []() {}, body);
577 b.create<emit::FragmentOp>(randomInitFragmentName.getAttr(), [&] {
578 b.create<sv::VerbatimOp>(
579 "// Standard header to adapt well known macros for "
580 "register randomization.");
582 b.create<sv::VerbatimOp>(
583 "\n// RANDOM may be set to an expression that produces a 32-bit "
584 "random unsigned value.");
585 emitGuardedDefine(
"RANDOM",
"RANDOM", StringRef(),
"$random");
587 b.create<sv::VerbatimOp>(
588 "\n// Users can define INIT_RANDOM as general code that gets "
590 "into the\n// initializer block for modules with registers.");
591 emitGuardedDefine(
"INIT_RANDOM",
"INIT_RANDOM", StringRef(),
"");
593 b.create<sv::VerbatimOp>(
594 "\n// If using random initialization, you can also define "
595 "RANDOMIZE_DELAY to\n// customize the delay used, otherwise 0.002 "
597 emitGuardedDefine(
"RANDOMIZE_DELAY",
"RANDOMIZE_DELAY", StringRef(),
600 b.create<sv::VerbatimOp>(
601 "\n// Define INIT_RANDOM_PROLOG_ for use in our modules below.");
602 emitGuard(
"INIT_RANDOM_PROLOG_", [&]() {
606 emitGuardedDefine(
"VERILATOR",
"INIT_RANDOM_PROLOG_",
608 "`INIT_RANDOM #`RANDOMIZE_DELAY begin end");
610 [&]() { b.create<sv::MacroDefOp>(
"INIT_RANDOM_PROLOG_",
""); });
614 if (hasMemRandomization) {
615 b.create<emit::FragmentOp>(randomInitMemFragmentName.getAttr(), [&] {
616 b.create<sv::VerbatimOp>(
"\n// Include rmemory initializers in init "
617 "blocks unless synthesis is set");
618 emitGuard(
"RANDOMIZE", [&]() {
619 emitGuardedDefine(
"RANDOMIZE_MEM_INIT",
"RANDOMIZE");
621 emitGuard(
"SYNTHESIS", [&] {
622 emitGuardedDefine(
"ENABLE_INITIAL_MEM_",
"ENABLE_INITIAL_MEM_",
625 b.create<sv::VerbatimOp>(
"");
629 if (hasRegRandomization) {
630 b.create<emit::FragmentOp>(randomInitRegFragmentName.getAttr(), [&] {
631 b.create<sv::VerbatimOp>(
"\n// Include register initializers in init "
632 "blocks unless synthesis is set");
633 emitGuard(
"RANDOMIZE", [&]() {
634 emitGuardedDefine(
"RANDOMIZE_REG_INIT",
"RANDOMIZE");
636 emitGuard(
"SYNTHESIS", [&] {
637 emitGuardedDefine(
"ENABLE_INITIAL_REG_",
"ENABLE_INITIAL_REG_",
640 b.create<sv::VerbatimOp>(
"");
645 std::unique_ptr<Pass>
647 return std::make_unique<SeqToSVPass>(options);
assert(baseType &&"element must be base type")
static FIRRTLBaseType convertType(FIRRTLBaseType type)
Returns null type if no conversion is needed.
llvm::SmallVector< StringAttr > inputs
static bool isLegalType(Type ty)
static bool isLegalOp(Operation *op)
FIR memory lowering helper.
Lower FirRegOp to sv.reg and sv.always.
def create(data_type, value)
Direction get(bool isOutput)
Returns an output direction if isOutput is true, otherwise returns an input direction.
Value createOrFoldNot(Location loc, Value value, OpBuilder &builder, bool twoState=false)
Create a `‘Not’' gate on a value.
StringRef getFragmentsAttrName()
Return the name of the fragments array attribute.
mlir::ArrayAttr getSVAttributes(mlir::Operation *op)
Return all the SV attributes of an operation, or null if there are none.
void setSVAttributes(mlir::Operation *op, mlir::ArrayAttr attrs)
Set the SV attributes of an operation.
The InstanceGraph op interface, see InstanceGraphInterface.td for more details.
std::unique_ptr< mlir::Pass > createLowerSeqToSVPass(const LowerSeqToSVOptions &options={})
StringRef chooseName(StringRef a, StringRef b)
Choose a good name for an item from two options.
def reg(value, clock, reset=None, reset_value=None, name=None, sym_name=None)
Generic pattern which replaces an operation by one of the same operation name, but with converted att...