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| static bool | circt::hw::operator== (const ModulePort &a, const ModulePort &b) |
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| static llvm::hash_code | circt::hw::hash_value (const ModulePort &port) |
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| ModuleType | circt::hw::detail::fnToMod (Operation *op, ArrayRef< Attribute > inputNames, ArrayRef< Attribute > outputNames) |
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| ModuleType | circt::hw::detail::fnToMod (FunctionType fn, ArrayRef< Attribute > inputNames, ArrayRef< Attribute > outputNames) |
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| mlir::Type | circt::hw::getCanonicalType (mlir::Type type) |
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| bool | circt::hw::isHWIntegerType (mlir::Type type) |
| | Return true if the specified type is a value HW Integer type.
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| bool | circt::hw::isHWEnumType (mlir::Type type) |
| | Return true if the specified type is a HW Enum type.
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| bool | circt::hw::isHWValueType (mlir::Type type) |
| | Return true if the specified type can be used as an HW value type, that is the set of types that can be composed together to represent synthesized, hardware but not marker types like InOutType or unknown types from other dialects.
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| int64_t | circt::hw::getBitWidth (mlir::Type type) |
| | Return the hardware bit width of a type.
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| bool | circt::hw::hasHWInOutType (mlir::Type type) |
| | Return true if the specified type contains known marker types like InOutType.
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| LogicalResult | circt::hw::apIntToAggregateAttr (mlir::Type aggregateType, const APInt &intVal, ArrayAttr &result) |
| | Convert an APInt value into a nested aggregate attribute matching the given HWAggregateType.
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| LogicalResult | circt::hw::aggregateAttrToAPInt (mlir::Type type, ArrayAttr attr, APInt &result) |
| | Convert an ArrayAttr into an APInt value matching the given type.
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| template<typename... BaseTy> |
| bool | circt::hw::type_isa (Type type) |
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| template<typename... BaseTy> |
| bool | circt::hw::type_isa_and_nonnull (Type type) |
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| template<typename BaseTy > |
| BaseTy | circt::hw::type_cast (Type type) |
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| template<typename BaseTy > |
| BaseTy | circt::hw::type_dyn_cast (Type type) |
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