14#include "mlir/Transforms/GreedyPatternRewriteDriver.h"
20#define GEN_PASS_DEF_LOWERFORMALTOHWPASS
21#include "circt/Dialect/Verif/Passes.h.inc"
29struct LowerFormalToHWPass
30 : verif::impl::LowerFormalToHWPassBase<LowerFormalToHWPass> {
31 void runOnOperation()
override;
34static LogicalResult lowerFormalToHW(FormalOp op) {
35 IRRewriter rewriter(op);
38 SmallVector<hw::PortInfo> ports;
39 for (
auto symOp : op.getBody().front().getOps<
verif::SymbolicValueOp>()) {
41 hw::PortInfo({{rewriter.getStringAttr(
"symbolic_value_" +
42 std::to_string(ports.size())),
47 rewriter.create<
hw::HWModuleOp>(op.getLoc(), op.getNameAttr(), ports);
49 rewriter.inlineBlockBefore(&op.getBody().front(),
50 &moduleOp.getBodyBlock()->front(),
51 op.getBody().getArguments());
55 for (
auto symOp : make_early_inc_range(
57 rewriter.replaceAllUsesWith(symOp.getResult(),
58 moduleOp.getArgumentForInput(i));
60 rewriter.eraseOp(symOp);
68void LowerFormalToHWPass::runOnOperation() {
71 llvm::make_early_inc_range(getOperation().getOps<FormalOp>())) {
72 if (failed(lowerFormalToHW(op)))
73 return signalPassFailure();
77 return markAllAnalysesPreserved();
static Block * getBodyBlock(FModuleLike mod)
The InstanceGraph op interface, see InstanceGraphInterface.td for more details.
This holds the name, type, direction of a module's ports.