Here is a list of all variables with links to the classes they belong to:
- l -
- language : esiaccel.codegen.CppGenerator, esiaccel.codegen.Generator
- latency : circt::scheduling::Problem
- layerBlockGlobals : LowerLayersPass
- leftTotal : circt::pretty::PrettyPrinter
- legacyWiringProblems : circt::firrtl::ApplyState
- len : circt::pretty::Token::StringInfo
- length : aig.LongestPathCollection, circt::ExportVerilog::StringOrOpToEmit
- level : circt::VerbosePassInstrumentation< LoggedOpTypes >
- libDirs : circt::ImportVerilogOptions, circt::lsp::VerilogServerOptions
- libExts : circt::ImportVerilogOptions
- librariesInheritMacros : circt::ImportVerilogOptions
- libraryFiles : circt::ImportVerilogOptions
- libraryName : circt::scheduling::Problem
- limit : circt::scheduling::SharedOperatorsProblem
- line : circt::ExportVerilog::OpLocMap::LineColPair
- linkedOperatorType : circt::scheduling::Problem
- linkedResourceTypes : circt::scheduling::Problem
- lintStaticAsserts : circt::firtool::FirtoolOptions
- lintXmrsInDesign : circt::firtool::FirtoolOptions
- listener : circt::pretty::PrettyPrinter
- listeners : esi::AcceleratorServiceThread::Impl
- loc : circt::BackedgeBuilder, circt::DIVariable, circt::firrtl::FirMemory, circt::firrtl::PortInfo, circt::hw::PortInfo, circt::ImportVerilog::PortLowering, circt::om::evaluator::EvaluatorValue, Python.support.BackedgeBuilder.Edge
- localVisitors : Context
- locationInfoStyle : circt::LoweringOptions
- locked : circt::Namespace
- locOp : circt::msft::PlacementDB::PlacementCell
- logger : esi::Context
- logic : circt::calyx::PredicateInfo
- long_description : Python.setup.NoopBuildExtension
- loopInitGroups : circt::calyx::LoopLoweringStateInterface< Loop >
- loopIterRegs : circt::calyx::LoopLoweringStateInterface< Loop >
- loopLatchGroups : circt::calyx::LoopLoweringStateInterface< Loop >
- loopStack : circt::ImportVerilog::Context
- lowerAlwaysAtStarAsComb : circt::ImportVerilogOptions
- lowerAnnotationsNoRefTypePorts : circt::firtool::FirtoolOptions
- loweredInputs : circt::hw::PortConverterImpl
- loweredOutputs : circt::hw::PortConverterImpl
- loweringRes : PartialLowerRegion
- loweringState : circt::pipelinetocalyx::LoopScheduleToCalyxPass
- lowerMemories : circt::firtool::FirtoolOptions
- lvalueStack : circt::ImportVerilog::Context