- b -

• b : circt::hw::PortConverterImpl , Equivalence::ModuleData
• backedge_owner : Python.support.OpOperand
• backedges : Python.support.NamedValueOpView
• backendRegistry : esi::registry::internal::BackendRegistry
• bag : BagValue
• bankingFactor : BankAffineLoadPattern , BankAffineStorePattern
• base : esi::services::MMIO::RegionDescriptor
• bb : circt::ValueMapper
• begin : circt::ExportVerilog::OpLocMap::LocationRange
• beginInfo : circt::pretty::Token
• binary : circt::python::PyFileAccumulator
• blackBoxRootPath : circt::firtool::FirtoolOptions
• block : circt::sv::CaseInfo
• blockArgGroups : circt::calyx::ComponentLoweringStateInterface
• blockArgRegs : circt::calyx::ComponentLoweringStateInterface
• blockEntryControlMap : circt::handshake::HandshakeLowering
• blockMap : circt::llhd::TemporalRegionAnalysis
• blockScheduleables : circt::calyx::SchedulerInterface< T >
• body : circt::hw::PortConversion , circt::hw::PortConverterImpl
• bound : circt::scftocalyx::ForScheduleable
• breakBlock : circt::ImportVerilog::LoopFrame
• breakInfo : circt::pretty::Token
• breaks : circt::pretty::PrettyPrinter::PrintEntry , circt::pretty::Token::BeginInfo
• bufferFilePaths : circt::ImportVerilog::Context
• bufferNameIdentifier : circt::firrtl::FIRLexer
• builder : circt::BackedgeBuilder , circt::firrtl::HierPathCache , circt::ImportVerilog::Context
• buildMode : circt::firtool::FirtoolOptions
• bval : TVpiVecval