- g -

• genericAsmResultNames() : FIRRTLOps.cpp
• genValueName() : KanagawaOps.cpp
• genValueNameAttr() : KanagawaOps.cpp
• getAccessPath() : FreezePaths.cpp
• getAddressWidth() : FIRRTLOps.cpp
• getAllEnableOpsInImmediateBody() : CalyxOps.cpp
• getAllFieldAccesses() : LowerMemory.cpp , LowerToHW.cpp
• getAllPortLocs() : HWOps.cpp
• getAllSubelementIndexMap() : MooreTypes.cpp
• getAmbientLayersAt() : FIRRTLOps.cpp
• getAmbientLayersFor() : FIRRTLOps.cpp
• getAnnotationHandler() : LowerAnnotations.cpp
• getAnnotationsFrom() : FIRRTLAnnotations.cpp , LowerAnnotations.cpp
• getArgName() : PrepareForEmission.cpp , Analysis.cpp
• getArrayElements() : MooreOps.cpp
• getAsmBlockArgumentNamesImpl() : FIRRTLOps.cpp , HWOps.cpp
• getBackwardSlice() : SVExtractTestCode.cpp
• getBackwardSliceSimple() : SVExtractTestCode.cpp
• getBareSubModuleName() : HandshakeToHW.cpp
• getBitWidthFromVectorSize() : LowerToHW.cpp
• getBlockArgumentWithName() : CalyxOps.cpp
• getBlockControlTerminator() : CFToHandshake.cpp
• getBlockDepth() : PrettifyVerilog.cpp
• getBlockPredecessorCount() : CFToHandshake.cpp
• getBodyBlock() : ProbesToSignals.cpp
• getBranchCount() : CFToHandshake.cpp
• getBranchDecisionsFromDominatorToTarget() : TemporalCodeMotionPass.cpp
• getCallName() : HandshakeToHW.cpp
• getCellAsmResultNames() : CalyxOps.cpp
• getClassLikeAsmBlockArgumentNames() : OMOps.cpp
• getClassLikeFieldType() : OMOps.cpp
• getCommonOperand() : CombFolds.cpp
• getConcatOperands() : CombFolds.cpp
• getConstant() : FIRRTLFolds.cpp
• getConstantValue() : FirRegLowering.cpp
• getControlCondBranch() : CFToHandshake.cpp
• getControlMerge() : CFToHandshake.cpp
• getControlOrWiresFrom() : CalyxOps.cpp
• getControlTerminators() : CFToHandshake.cpp
• getConversionInfo() : MuxToControlFlow.cpp
• getCostEstimate() : MuxToControlFlow.cpp
• getCycleTime() : Schedule.cpp
• getDeclName() : InferResets.cpp , FIRRTLUtils.cpp
• getDefiningBlock() : MaximizeSSA.cpp
• getDematerialized() : HandshakeOps.cpp
• getDFClosure() : MemoryToBlockArgumentPass.cpp
• getDirection() : SystemCOps.cpp
• getDominanceFrontier() : MemoryToBlockArgumentPass.cpp
• getDominatingAttachUser() : FIRRTLFolds.cpp
• getElementTypeOfWidth() : SVOps.cpp
• getEsiDataType() : ESIOps.cpp
• getExplicitlyReturnedValueImpl() : SVOps.cpp
• getExtendedConstant() : FIRRTLFolds.cpp
• getFieldAllIndex() : MooreTypes.cpp
• getFieldID() : InferResets.cpp
• getFieldIDOffset() : IMConstProp.cpp
• getFieldIDsStruct() : HWTypes.cpp
• getFieldName() : InferResets.cpp
• getFilteredPorts() : CalyxOps.cpp
• getFirstOp() : CFToHandshake.cpp
• getFlattenedMemRefName() : FlattenMemRefs.cpp
• getFlattenedMemRefType() : FlattenMemRefs.cpp
• getFuncOpNames() : HandshakeOps.cpp
• getHandshakeDiscriminatingTypes() : HandshakeToHW.cpp
• getHwModuleExtGoOrDonePortNumber() : CalyxOps.cpp
• getHWModuleOpType() : HWOps.cpp
• getHWParameters() : LowerToHW.cpp
• getIfAndBasedReset() : InferStateProperties.cpp
• getIfMuxBasedDisable() : InferStateProperties.cpp
• getIfMuxBasedEnable() : InferStateProperties.cpp
• getIfMuxBasedReset() : InferStateProperties.cpp
• getIndexForFieldID() : InferResets.cpp
• getInnerTypes() : FlattenIO.cpp
• getInputPortVerilogName() : ExportVerilog.cpp
• getInt() : PrettifyVerilog.cpp
• getInt32Attr() : ExportVerilog.cpp
• getIntAttr() : ExportVerilog.cpp , CombFolds.cpp
• getLastEnableOp() : CalyxOps.cpp
• getLastOp() : Schedule.cpp
• getLayersFor() : FIRRTLOps.cpp
• getLoadPorts() : HandshakeOps.cpp
• getLocalName() : Analysis.cpp
• getLowered() : LowerDPI.cpp
• getLowestBitAndHighestBitRequired() : CombFolds.cpp
• getMachinePortInfo() : FSMToSV.cpp
• getMainBufferNameIdentifier() : FIRLexer.cpp
• getMaxFieldID() : InferResets.cpp
• getMaxSignedValue() : FIRRTLFolds.cpp
• getMaxUnsignedValue() : FIRRTLFolds.cpp
• getMemoryOperandName() : HandshakeOps.cpp
• getMemoryRead() : HWMemSimImpl.cpp
• getMemoryResultName() : HandshakeOps.cpp
• getMemPortKindFromType() : FIRRTLOps.cpp
• getMemTypeForExtmem() : LowerExtmemToHW.cpp
• getMergeOperand() : CFToHandshake.cpp
• getMinSignedValue() : FIRRTLFolds.cpp
• getModuleArgumentName() : ModuleImplementation.cpp
• getModulePort() : ArcOps.cpp
• getModuleResultName() : ModuleImplementation.cpp
• getMuxChainCondConstant() : CombFolds.cpp
• getNameForPort() : SVExtractTestCode.cpp
• getNameOrHint() : Naming.cpp
• getNecessaryBitWidth() : CompileControl.cpp
• getNonOverlappingConcatSubrange() : ExportVerilog.cpp
• getOneOfType() : HWAttributes.cpp
• getOperandDataType() : HandshakeToHW.cpp
• getOperandFromBlock() : CFToHandshake.cpp
• getOperandName() : ESILowerPorts.cpp
• getOpMemRef() : CFToHandshake.cpp
• getOrderedStagesFailable() : PipelineOps.cpp
• getOutputFile() : AssignOutputDirs.cpp
• getPatternBitsForValue() : SVOps.cpp
• getPhysLocationAttr() : MSFTModule.cpp
• getPipelineAsmBlockArgumentNames() : PipelineOps.cpp
• getPipelineAsmResultNames() : PipelineOps.cpp
• getPointerReadByOp() : MergeIfs.cpp
• getPointerWrittenByOp() : MergeIfs.cpp
• getPort() : HWOps.cpp
• getPortFieldValue() : FIRRTLFolds.cpp
• getPortImpl() : FIRRTLOps.cpp
• getPortInfoForOp() : HandshakeToHW.cpp
• getPortList() : HWOps.cpp
• getPortListImpl() : FIRRTLOps.cpp
• getPortVerilogName() : ExportVerilog.cpp
• getPyType() : esiCppAccel.cpp
• getRead() : Services.cpp
• getReferencedMacro() : SVOps.cpp
• getResetName() : InferResets.cpp
• getResetNameAndModule() : InferResets.cpp
• getResName() : Analysis.cpp , PrepareForEmission.cpp
• getResultsToMemory() : CFToHandshake.cpp
• getSAWritePath() : LowerTypes.cpp
• getServiceDecl() : ESIOps.cpp
• getServicePortInfo() : ESIOps.cpp
• getSignedInheritedSignedness() : HWArithOps.cpp
• getSingleAssignAndCheckUsers() : ExportVerilog.cpp
• getSingleNonInstanceOperand() : LowerToHW.cpp
• getSortedInputs() : CFToHandshake.cpp
• getSortedPtrs() : LLHDOps.cpp
• getStorePorts() : HandshakeOps.cpp
• getStringAttributeOr() : ESILowerPorts.cpp
• getStructFieldIndex() : MooreOps.cpp
• getStructFieldType() : MooreOps.cpp
• getStructMembers() : MooreOps.cpp
• getStructType() : FlattenIO.cpp
• getSubModuleName() : HandshakeToHW.cpp
• getSuccResult() : CFToHandshake.cpp
• getSummary() : LowerMemory.cpp
• getSupportedModuleOp() : ArcOps.cpp
• getTotalWidth() : CombOps.cpp , CombFolds.cpp
• getTwoStateIntegerAtomType() : ExportVerilog.cpp
• getTypeAtAllIndex() : MooreTypes.cpp
• getTypeDims() : ExportVerilog.cpp
• getTypeName() : HandshakeToHW.cpp
• getUIntFromValue() : HWOps.cpp
• getUniformlyInRange() : ElaborationPass.cpp
• getUniqueArgName() : Analysis.cpp
• getUniqueResName() : Analysis.cpp
• getValueAtIndex() : LLHDOps.cpp
• getVectorWidth() : ArcOps.cpp
• getVerbatimExprAsmResultNames() : SVOps.cpp
• getVerilogDeclWord() : ExportVerilog.cpp
• getVerilogInstanceName() : EmitHGLDD.cpp
• getVerilogModuleName() : EmitHGLDD.cpp
• getVerilogValueName() : ExportVerilog.cpp
• getWidestIntType() : LowerToHW.cpp
• getWrite() : Services.cpp
• globalCounter() : FlattenMemRefs.cpp
• guessNamespacePrefix() : Structure.cpp