Here is a list of all functions with links to the files they belong to:
- g -
- genericAsmResultNames() : FIRRTLOps.cpp
- genValueName() : KanagawaOps.cpp
- genValueNameAttr() : KanagawaOps.cpp
- getAccessPath() : FreezePaths.cpp
- getAddressWidth() : FIRRTLOps.cpp
- getAllEnableOpsInImmediateBody() : CalyxOps.cpp
- getAllFieldAccesses() : LowerMemory.cpp, LowerToHW.cpp
- getAllPortLocs() : HWOps.cpp
- getAllSubelementIndexMap() : MooreTypes.cpp
- getAmbientLayersAt() : FIRRTLOps.cpp
- getAmbientLayersFor() : FIRRTLOps.cpp
- getAnnotationHandler() : LowerAnnotations.cpp
- getAnnotationsFrom() : FIRRTLAnnotations.cpp, LowerAnnotations.cpp
- getArgName() : Analysis.cpp, PrepareForEmission.cpp
- getArrayElements() : MooreOps.cpp
- getAsmBlockArgumentNamesImpl() : FIRRTLOps.cpp, HWOps.cpp
- getBackwardSlice() : SVExtractTestCode.cpp
- getBackwardSliceSimple() : SVExtractTestCode.cpp
- getBareSubModuleName() : HandshakeToHW.cpp
- getBitWidth() : ExportAIGER.cpp, LongestPathAnalysis.cpp
- getBitWidthFromVectorSize() : LowerToHW.cpp
- getBlockArgumentWithName() : CalyxOps.cpp
- getBlockControlTerminator() : CFToHandshake.cpp
- getBlockDepth() : PrettifyVerilog.cpp
- getBlockPredecessorCount() : CFToHandshake.cpp
- getBodyBlock() : ProbesToSignals.cpp
- getBranchCount() : CFToHandshake.cpp
- getBranchDecisionsFromDominatorToTarget() : RemoveControlFlow.cpp, TemporalCodeMotionPass.cpp
- getCallName() : HandshakeToHW.cpp
- getCellAsmResultNames() : CalyxOps.cpp
- getChannelConsumers() : ESITypes.cpp
- getClassLikeAsmBlockArgumentNames() : OMOps.cpp
- getClassLikeFieldType() : OMOps.cpp
- getCommonOperand() : CombFolds.cpp
- getConcatOperands() : CombFolds.cpp
- getConstant() : FIRRTLFolds.cpp
- getConstantValue() : FirRegLowering.cpp
- getControlCondBranch() : CFToHandshake.cpp
- getControlMerge() : CFToHandshake.cpp
- getControlOrWiresFrom() : CalyxOps.cpp
- getControlTerminators() : CFToHandshake.cpp
- getConversionInfo() : MuxToControlFlow.cpp
- getCostEstimate() : MuxToControlFlow.cpp
- getCurrBankingInfo() : MemoryBanking.cpp
- getCycleTime() : Schedule.cpp
- getDeclName() : FIRRTLUtils.cpp, InferResets.cpp
- getDefiningBlock() : MaximizeSSA.cpp
- getDematerialized() : HandshakeOps.cpp
- getDFClosure() : MemoryToBlockArgumentPass.cpp
- getDirection() : SystemCOps.cpp
- getDominanceFrontier() : MemoryToBlockArgumentPass.cpp
- getDominatingAttachUser() : FIRRTLFolds.cpp
- getElementTypeOfWidth() : SVOps.cpp
- getEsiDataType() : ESIOps.cpp
- getExplicitlyReturnedValueImpl() : SVOps.cpp
- getExtendedConstant() : FIRRTLFolds.cpp
- getFieldAllIndex() : MooreTypes.cpp
- getFieldID() : InferResets.cpp
- getFieldIDOffset() : IMConstProp.cpp
- getFieldIDsStruct() : HWTypes.cpp
- getFieldName() : InferResets.cpp
- getFilteredPorts() : CalyxOps.cpp
- getFirstOp() : CFToHandshake.cpp
- getFlattenedMemRefName() : FlattenMemRefs.cpp
- getFlattenedMemRefType() : FlattenMemRefs.cpp
- getFPBitWidth() : CalyxEmitter.cpp
- getFuncOpNames() : HandshakeOps.cpp
- getHandshakeDiscriminatingTypes() : HandshakeToHW.cpp
- getHwModuleExtGoOrDonePortNumber() : CalyxOps.cpp
- getHWModuleOpType() : HWOps.cpp
- getHWParameters() : LowerToHW.cpp
- getIfAndBasedReset() : InferStateProperties.cpp
- getIfMuxBasedDisable() : InferStateProperties.cpp
- getIfMuxBasedEnable() : InferStateProperties.cpp
- getIfMuxBasedReset() : InferStateProperties.cpp
- getIndexForFieldID() : InferResets.cpp
- getInnerTypes() : FlattenIO.cpp
- getInputPortVerilogName() : ExportVerilog.cpp
- getInt() : PrettifyVerilog.cpp
- getInt32Attr() : ExportVerilog.cpp
- getIntAttr() : ExportVerilog.cpp, CombFolds.cpp
- getIntWidth() : CalyxEmitter.cpp
- getLastEnableOp() : CalyxOps.cpp
- getLastOp() : Schedule.cpp
- getLayersFor() : FIRRTLOps.cpp
- getLength() : CombineDrives.cpp
- getLoadPorts() : HandshakeOps.cpp
- getLoc() : Mem2Reg.cpp
- getLocalName() : Analysis.cpp
- getLowered() : LowerDPI.cpp
- getLowestBitAndHighestBitRequired() : CombFolds.cpp
- getMachinePortInfo() : FSMToSV.cpp
- getMainBufferNameIdentifier() : FIRLexer.cpp
- getMaxFieldID() : InferResets.cpp
- getMaxSignedValue() : FIRRTLFolds.cpp
- getMaxUnsignedValue() : FIRRTLFolds.cpp
- getMemoryOperandName() : HandshakeOps.cpp
- getMemoryRead() : HWMemSimImpl.cpp
- getMemoryResultName() : HandshakeOps.cpp
- getMemPortKindFromType() : FIRRTLOps.cpp
- getMemRefBankingConfig() : MemoryBanking.cpp
- getMemTypeForExtmem() : LowerExtmemToHW.cpp
- getMergeOperand() : CFToHandshake.cpp
- getMinSignedValue() : FIRRTLFolds.cpp
- getModuleArgumentName() : ModuleImplementation.cpp
- getModulePort() : ArcOps.cpp
- getModuleResultName() : ModuleImplementation.cpp
- getMuxChainCondConstant() : CombFolds.cpp
- getNameForPort() : SVExtractTestCode.cpp
- getNameImpl() : LongestPathAnalysis.cpp
- getNameOrHint() : Naming.cpp
- getNecessaryBitWidth() : CompileControl.cpp
- getNonOverlappingConcatSubrange() : ExportVerilog.cpp
- getNumUnknownBitsAndPopulateValues() : CombToAIG.cpp
- getOneOfType() : HWAttributes.cpp
- getOperandDataType() : HandshakeToHW.cpp
- getOperandFromBlock() : CFToHandshake.cpp
- getOperandName() : ESILowerPorts.cpp
- getOpMemRef() : CFToHandshake.cpp
- getOrderedStagesFailable() : PipelineOps.cpp
- getOutputFile() : AssignOutputDirs.cpp
- getPatternBitsForValue() : SVOps.cpp
- getPhysLocationAttr() : MSFTModule.cpp
- getPipelineAsmBlockArgumentNames() : PipelineOps.cpp
- getPipelineAsmResultNames() : PipelineOps.cpp
- getPointerReadByOp() : MergeIfs.cpp
- getPointerWrittenByOp() : MergeIfs.cpp
- getPort() : HWOps.cpp
- getPortFieldValue() : FIRRTLFolds.cpp
- getPortImpl() : FIRRTLOps.cpp
- getPortInfoForOp() : HandshakeToHW.cpp
- getPortList() : HWOps.cpp
- getPortListImpl() : FIRRTLOps.cpp
- getPortVerilogName() : ExportVerilog.cpp
- getProjections() : Mem2Reg.cpp
- getPyType() : esiCppAccel.cpp
- getReferencedMacro() : SVOps.cpp
- getRemainingBankingInfo() : MemoryBanking.cpp
- getResetName() : InferResets.cpp
- getResetNameAndModule() : InferResets.cpp
- getResName() : PrepareForEmission.cpp, Analysis.cpp
- getResultsToMemory() : CFToHandshake.cpp
- getSAWritePath() : LowerTypes.cpp
- getSelectIndex() : Expressions.cpp
- getServiceDecl() : ESIOps.cpp
- getServicePortInfo() : ESIOps.cpp
- getSeverity() : VerilogServer.cpp
- getSignedInheritedSignedness() : HWArithOps.cpp
- getSingleAssignAndCheckUsers() : ExportVerilog.cpp
- getSingleNonInstanceOperand() : LowerToHW.cpp
- getSlot() : Mem2Reg.cpp
- getSortedInputs() : CFToHandshake.cpp
- getSortedPtrs() : LLHDOps.cpp
- getSpecifiedOrDefaultBankingDim() : MemoryBanking.cpp
- getStoredType() : Mem2Reg.cpp
- getStorePorts() : HandshakeOps.cpp
- getStringAttributeOr() : ESILowerPorts.cpp
- getStructFieldIndex() : MooreOps.cpp
- getStructFieldType() : MooreOps.cpp
- getStructMembers() : MooreOps.cpp
- getStructType() : FlattenIO.cpp
- getSubModuleName() : HandshakeToHW.cpp
- getSuccResult() : CFToHandshake.cpp
- getSummary() : LowerMemory.cpp
- getSupportedModuleOp() : ArcOps.cpp
- getTotalWidth() : CombFolds.cpp, CombOps.cpp
- getTwoStateIntegerAtomType() : ExportVerilog.cpp
- getTypeAtAllIndex() : MooreTypes.cpp
- getTypeDims() : ExportVerilog.cpp
- getTypeName() : HandshakeToHW.cpp
- getUIntFromValue() : HWOps.cpp
- getUniformlyInRange() : ElaborationPass.cpp
- getUniqueArgName() : Analysis.cpp
- getUniqueResName() : Analysis.cpp
- getValueAtIndex() : LLHDOps.cpp
- getVectorWidth() : ArcOps.cpp
- getVerbatimExprAsmResultNames() : SVOps.cpp
- getVerilogDeclWord() : ExportVerilog.cpp
- getVerilogInstanceName() : EmitHGLDD.cpp
- getVerilogModuleName() : EmitHGLDD.cpp
- getVerilogValueName() : ExportVerilog.cpp
- getWidestIntType() : LowerToHW.cpp
- globalCounter() : FlattenMemRefs.cpp
- guardMacroNameForLayer() : LowerLayers.cpp
- guessNamespacePrefix() : Structure.cpp