CIRCT  19.0.0git
ExportVerilog.h
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1 //===- ExportVerilog.h - Verilog Exporter -----------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Defines the interface to the Verilog emitter.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef CIRCT_TRANSLATION_EXPORTVERILOG_H
14 #define CIRCT_TRANSLATION_EXPORTVERILOG_H
15 
16 #include "mlir/IR/BuiltinOps.h"
17 #include "mlir/Pass/Pass.h"
18 
19 namespace circt {
20 
21 std::unique_ptr<mlir::Pass>
22 createTestApplyLoweringOptionPass(llvm::StringRef options);
23 std::unique_ptr<mlir::Pass> createTestApplyLoweringOptionPass();
24 
25 std::unique_ptr<mlir::Pass> createHWLowerInstanceChoicesPass();
26 std::unique_ptr<mlir::Pass> createPrepareForEmissionPass();
27 std::unique_ptr<mlir::Pass> createLegalizeAnonEnumsPass();
28 
29 std::unique_ptr<mlir::Pass>
30 createExportVerilogPass(std::unique_ptr<llvm::raw_ostream> os);
31 std::unique_ptr<mlir::Pass> createExportVerilogPass(llvm::raw_ostream &os);
32 std::unique_ptr<mlir::Pass> createExportVerilogPass();
33 
34 std::unique_ptr<mlir::Pass>
35 createExportSplitVerilogPass(llvm::StringRef directory = "./");
36 
37 /// Export a module containing HW, and SV dialect code. Requires that the SV
38 /// dialect is loaded in to the context.
39 mlir::LogicalResult exportVerilog(mlir::ModuleOp module, llvm::raw_ostream &os);
40 
41 /// Export a module containing HW, and SV dialect code, as one file per SV
42 /// module. Requires that the SV dialect is loaded in to the context.
43 ///
44 /// Files are created in the directory indicated by \p dirname.
45 mlir::LogicalResult exportSplitVerilog(mlir::ModuleOp module,
46  llvm::StringRef dirname);
47 
48 } // namespace circt
49 
50 #endif // CIRCT_TRANSLATION_EXPORTVERILOG_H
This file defines an intermediate representation for circuits acting as an abstraction for constraint...
Definition: DebugAnalysis.h:21
std::unique_ptr< mlir::Pass > createHWLowerInstanceChoicesPass()
mlir::LogicalResult exportVerilog(mlir::ModuleOp module, llvm::raw_ostream &os)
Export a module containing HW, and SV dialect code.
std::unique_ptr< mlir::Pass > createExportVerilogPass(std::unique_ptr< llvm::raw_ostream > os)
std::unique_ptr< mlir::Pass > createExportSplitVerilogPass(llvm::StringRef directory="./")
std::unique_ptr< mlir::Pass > createTestApplyLoweringOptionPass(llvm::StringRef options)
mlir::LogicalResult exportSplitVerilog(mlir::ModuleOp module, llvm::StringRef dirname)
Export a module containing HW, and SV dialect code, as one file per SV module.
std::unique_ptr< mlir::Pass > createLegalizeAnonEnumsPass()
std::unique_ptr< mlir::Pass > createPrepareForEmissionPass()