CIRCT  20.0.0git
ExportVerilog.h
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1 //===- ExportVerilog.h - Verilog Exporter -----------------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Defines the interface to the Verilog emitter.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 #ifndef CIRCT_TRANSLATION_EXPORTVERILOG_H
14 #define CIRCT_TRANSLATION_EXPORTVERILOG_H
15 
16 #include "mlir/IR/BuiltinOps.h"
17 #include "mlir/Pass/Pass.h"
18 
19 namespace circt {
20 
21 #define GEN_PASS_DECL_TESTAPPLYLOWERINGOPTION
22 #define GEN_PASS_DECL_HWLOWERINSTANCECHOICES
23 #define GEN_PASS_DECL_PREPAREFOREMISSION
24 #define GEN_PASS_DECL_LEGALIZEANONENUMS
25 #define GEN_PASS_DECL_EXPORTSPLITVERILOG
26 #define GEN_PASS_DECL_EXPORTVERILOG
27 #include "circt/Conversion/Passes.h.inc"
28 namespace hw {
29 class HWModuleLike;
30 class HWEmittableModuleLike;
31 } // namespace hw
32 
33 std::unique_ptr<mlir::Pass>
34 createTestApplyLoweringOptionPass(llvm::StringRef options);
35 std::unique_ptr<mlir::Pass> createTestApplyLoweringOptionPass();
36 
37 std::unique_ptr<mlir::Pass> createHWLowerInstanceChoicesPass();
38 std::unique_ptr<mlir::Pass> createPrepareForEmissionPass();
39 std::unique_ptr<mlir::Pass> createLegalizeAnonEnumsPass();
40 
41 std::unique_ptr<mlir::Pass>
42 createExportVerilogPass(std::unique_ptr<llvm::raw_ostream> os);
43 std::unique_ptr<mlir::Pass> createExportVerilogPass(llvm::raw_ostream &os);
44 std::unique_ptr<mlir::Pass> createExportVerilogPass();
45 
46 std::unique_ptr<mlir::Pass>
47 createExportSplitVerilogPass(llvm::StringRef directory = "./");
48 
49 /// Export a module containing HW, and SV dialect code. Requires that the SV
50 /// dialect is loaded in to the context.
51 mlir::LogicalResult exportVerilog(mlir::ModuleOp module, llvm::raw_ostream &os);
52 
53 /// Export a module containing HW, and SV dialect code, as one file per SV
54 /// module. Requires that the SV dialect is loaded in to the context.
55 ///
56 /// Files are created in the directory indicated by \p dirname.
57 mlir::LogicalResult exportSplitVerilog(mlir::ModuleOp module,
58  llvm::StringRef dirname);
59 
60 } // namespace circt
61 
62 #endif // CIRCT_TRANSLATION_EXPORTVERILOG_H
The InstanceGraph op interface, see InstanceGraphInterface.td for more details.
Definition: DebugAnalysis.h:21
std::unique_ptr< mlir::Pass > createHWLowerInstanceChoicesPass()
mlir::LogicalResult exportVerilog(mlir::ModuleOp module, llvm::raw_ostream &os)
Export a module containing HW, and SV dialect code.
std::unique_ptr< mlir::Pass > createExportVerilogPass(std::unique_ptr< llvm::raw_ostream > os)
std::unique_ptr< mlir::Pass > createExportSplitVerilogPass(llvm::StringRef directory="./")
std::unique_ptr< mlir::Pass > createTestApplyLoweringOptionPass(llvm::StringRef options)
mlir::LogicalResult exportSplitVerilog(mlir::ModuleOp module, llvm::StringRef dirname)
Export a module containing HW, and SV dialect code, as one file per SV module.
std::unique_ptr< mlir::Pass > createLegalizeAnonEnumsPass()
std::unique_ptr< mlir::Pass > createPrepareForEmissionPass()
Definition: hw.py:1