18 #include "mlir/IR/BuiltinTypes.h"
19 #include "mlir/IR/OperationSupport.h"
20 #include "mlir/Transforms/DialectConversion.h"
21 #include "mlir/Transforms/GreedyPatternRewriteDriver.h"
23 using namespace circt;
24 using namespace calyx;
31 static void doPortPassthrough(ComponentOp comp, Value fromPort,
33 MLIRContext *ctx = comp.getContext();
35 builder.setInsertionPointToStart(comp.getWiresOp().getBodyBlock());
37 for (
auto cell : comp.getOps<CellInterface>()) {
38 for (
auto port : cell.getInputPorts()) {
39 if (!cell.portInfo(port).hasAttribute(portID))
41 builder.create<AssignOp>(cell.getLoc(), port, fromPort);
46 struct ClkInsertionPass :
public ClkInsertionBase<ClkInsertionPass> {
47 void runOnOperation()
override {
48 doPortPassthrough(getOperation(), getOperation().getClkPort(),
"clk");
52 struct ResetInsertionPass :
public ResetInsertionBase<ResetInsertionPass> {
53 void runOnOperation()
override {
54 doPortPassthrough(getOperation(), getOperation().getResetPort(),
"reset");
61 return std::make_unique<ClkInsertionPass>();
65 return std::make_unique<ResetInsertionPass>();
std::unique_ptr< mlir::Pass > createResetInsertionPass()
std::unique_ptr< mlir::Pass > createClkInsertionPass()
This file defines an intermediate representation for circuits acting as an abstraction for constraint...