16 #ifndef DIALECT_ESI_PASSDETAILS_H
17 #define DIALECT_ESI_PASSDETAILS_H
30 #include "mlir/IR/DialectRegistry.h"
31 #include "mlir/Pass/Pass.h"
36 #define GEN_PASS_CLASSES
37 #include "circt/Dialect/ESI/ESIPasses.h.inc"
Assist the lowering steps for conversions which need to create auxiliary IR.
const StringAttr dataOutValid
hw::HWModuleExternOp declareCosimEndpointFromHostModule(Operation *symTable)
static constexpr char validStr[]
const StringAttr dataInValid
const StringAttr dataOutReady
static constexpr char sinkStr[]
std::optional< hw::HWModuleExternOp > declaredCosimEndpointToHostModule
llvm::DenseMap< Type, sv::InterfaceOp > portTypeLookup
static constexpr char readyStr[]
hw::HWModuleExternOp declareCosimEndpointToHostModule(Operation *symTable)
Write an 'ExternModuleOp' to use a hand-coded SystemVerilog module.
static constexpr char dataStr[]
StringAttr constructInterfaceName(ChannelType)
Construct a type-appropriate name for the interface, making sure it's not taken in the symbol table.
sv::InterfaceOp constructInterface(ChannelType)
ESIHWBuilder(Operation *top)
sv::InterfaceOp getOrConstructInterface(ChannelType)
Return the InterfaceType which corresponds to an ESI port type.
std::optional< hw::HWModuleExternOp > declaredCosimEndpointFromHostModule
llvm::DenseMap< Type, hw::HWModuleExternOp > declaredStage
static constexpr char sourceStr[]
hw::HWModuleExternOp declareStage(Operation *symTable, PipelineStageOp)
Write an 'ExternModuleOp' to use a hand-coded SystemVerilog module.
const StringAttr dataInReady
ArrayAttr getStageParameterList(Attribute value)
Return a parameter list for the stage module with the specified value.
uint64_t getWidth(Type t)
StringAttr getTypeID(Type t)
This file defines an intermediate representation for circuits acting as an abstraction for constraint...