CIRCT  18.0.0git
PassDetails.h
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1 //===- PassDetails.h - ESI pass class details -----------------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // Stuff shared between the different ESI passes.
10 //
11 //===----------------------------------------------------------------------===//
12 
13 // clang-tidy seems to expect the absolute path in the header guard on some
14 // systems, so just disable it.
15 // NOLINTNEXTLINE(llvm-header-guard)
16 #ifndef DIALECT_ESI_PASSDETAILS_H
17 #define DIALECT_ESI_PASSDETAILS_H
18 
24 #include "circt/Dialect/HW/HWOps.h"
26 #include "circt/Dialect/SV/SVOps.h"
28 #include "circt/Support/LLVM.h"
29 
30 #include "mlir/IR/DialectRegistry.h"
31 #include "mlir/Pass/Pass.h"
32 
33 namespace circt {
34 namespace esi {
35 
36 #define GEN_PASS_CLASSES
37 #include "circt/Dialect/ESI/ESIPasses.h.inc"
38 
39 } // namespace esi
40 } // namespace circt
41 
42 namespace circt {
43 namespace esi {
44 namespace detail {
45 
46 StringAttr getTypeID(Type t);
47 uint64_t getWidth(Type t);
48 
49 /// Assist the lowering steps for conversions which need to create auxiliary IR.
50 class ESIHWBuilder : public circt::ImplicitLocOpBuilder {
51 public:
52  ESIHWBuilder(Operation *top);
53 
54  ArrayAttr getStageParameterList(Attribute value);
55 
56  hw::HWModuleExternOp declareStage(Operation *symTable, PipelineStageOp);
59  sv::InterfaceOp getOrConstructInterface(ChannelType);
60  sv::InterfaceOp constructInterface(ChannelType);
61 
62  // A bunch of constants for use in various places below.
63  const StringAttr a, aValid, aReady, x, xValid, xReady;
66  const StringAttr clk, rst;
67  const StringAttr width;
68 
69  // Various identifier strings. Keep them all here in case we rename them.
70  static constexpr char dataStr[] = "data", validStr[] = "valid",
71  readyStr[] = "ready", sourceStr[] = "source",
72  sinkStr[] = "sink";
73 
74 private:
75  /// Construct a type-appropriate name for the interface, making sure it's not
76  /// taken in the symbol table.
77  StringAttr constructInterfaceName(ChannelType);
78 
79  Type getClockType();
80 
81  std::optional<hw::HWModuleExternOp> declaredCosimEndpointToHostModule;
82  std::optional<hw::HWModuleExternOp> declaredCosimEndpointFromHostModule;
83  llvm::DenseMap<Type, hw::HWModuleExternOp> declaredStage;
84  llvm::DenseMap<Type, sv::InterfaceOp> portTypeLookup;
85 };
86 } // namespace detail
87 } // namespace esi
88 } // namespace circt
89 
90 #endif // DIALECT_ESI_PASSDETAILS_H
lowerAnnotationsNoRefTypePorts FirtoolPreserveValuesMode value
Definition: Firtool.cpp:95
Assist the lowering steps for conversions which need to create auxiliary IR.
Definition: PassDetails.h:50
hw::HWModuleExternOp declareCosimEndpointFromHostModule(Operation *symTable)
Definition: ESIPasses.cpp:204
static constexpr char validStr[]
Definition: PassDetails.h:70
static constexpr char sinkStr[]
Definition: PassDetails.h:72
std::optional< hw::HWModuleExternOp > declaredCosimEndpointToHostModule
Definition: PassDetails.h:81
llvm::DenseMap< Type, sv::InterfaceOp > portTypeLookup
Definition: PassDetails.h:84
static constexpr char readyStr[]
Definition: PassDetails.h:71
hw::HWModuleExternOp declareCosimEndpointToHostModule(Operation *symTable)
Write an 'ExternModuleOp' to use a hand-coded SystemVerilog module.
Definition: ESIPasses.cpp:178
static constexpr char dataStr[]
Definition: PassDetails.h:70
StringAttr constructInterfaceName(ChannelType)
Construct a type-appropriate name for the interface, making sure it's not taken in the symbol table.
Definition: ESIPasses.cpp:100
sv::InterfaceOp constructInterface(ChannelType)
Definition: ESIPasses.cpp:241
sv::InterfaceOp getOrConstructInterface(ChannelType)
Return the InterfaceType which corresponds to an ESI port type.
Definition: ESIPasses.cpp:232
std::optional< hw::HWModuleExternOp > declaredCosimEndpointFromHostModule
Definition: PassDetails.h:82
llvm::DenseMap< Type, hw::HWModuleExternOp > declaredStage
Definition: PassDetails.h:83
static constexpr char sourceStr[]
Definition: PassDetails.h:71
hw::HWModuleExternOp declareStage(Operation *symTable, PipelineStageOp)
Write an 'ExternModuleOp' to use a hand-coded SystemVerilog module.
Definition: ESIPasses.cpp:139
ArrayAttr getStageParameterList(Attribute value)
Return a parameter list for the stage module with the specified value.
Definition: ESIPasses.cpp:129
uint64_t getWidth(Type t)
Definition: ESIPasses.cpp:34
StringAttr getTypeID(Type t)
Definition: ESIPasses.cpp:26
This file defines an intermediate representation for circuits acting as an abstraction for constraint...
Definition: DebugAnalysis.h:21
Definition: esi.py:1