Assist the lowering steps for conversions which need to create auxiliary IR. More...

#include <PassDetails.h>

Inheritance diagram for circt::esi::detail::ESIHWBuilder:

Collaboration diagram for circt::esi::detail::ESIHWBuilder:

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Public Member Functions
	ESIHWBuilder (Operation *top)
ArrayAttr	getStageParameterList (Attribute widthValue, Attribute dataDelayValue)
	Get the parameter list for the stage module.
hw::HWModuleExternOp	declareStage (Operation *symTable, PipelineStageOp)
	Write an 'ExternModuleOp' to use a hand-coded SystemVerilog module.
hw::HWModuleExternOp	declareCosimEndpointToHostModule (Operation *symTable)
	Write an 'ExternModuleOp' to use a hand-coded SystemVerilog module.
hw::HWModuleExternOp	declareCosimEndpointFromHostModule (Operation *symTable)

Public Attributes
const StringAttr	a
const StringAttr	aValid
const StringAttr	aReady
const StringAttr	x
const StringAttr	xValid
const StringAttr	xReady
const StringAttr	dataOutValid
const StringAttr	dataOutReady
const StringAttr	dataOut
const StringAttr	dataInValid
const StringAttr	dataInReady
const StringAttr	dataIn
const StringAttr	clk
const StringAttr	rst
const StringAttr	width
const StringAttr	dataDelay

Private Member Functions
Type	getClockType ()

Private Attributes
std::optional< hw::HWModuleExternOp >	declaredCosimEndpointToHostModule
std::optional< hw::HWModuleExternOp >	declaredCosimEndpointFromHostModule
llvm::DenseMap< Type, hw::HWModuleExternOp >	declaredStage

Detailed Description

Assist the lowering steps for conversions which need to create auxiliary IR.

Definition at line 56 of file PassDetails.h.

Constructor & Destructor Documentation

◆ ESIHWBuilder()

ESIHWBuilder::ESIHWBuilder ( Operation * top )

Definition at line 42 of file ESIPasses.cpp.

References a, aReady, aValid, clk, dataDelay, dataIn, dataInReady, dataInValid, dataOut, dataOutReady, dataOutValid, if(), rst, width, x, xReady, and xValid.

Member Function Documentation

◆ declareCosimEndpointFromHostModule()

HWModuleExternOp ESIHWBuilder::declareCosimEndpointFromHostModule ( Operation * symTable )

Definition at line 175 of file ESIPasses.cpp.

References clk, constructUniqueSymbol(), dataOut, dataOutReady, dataOutValid, declaredCosimEndpointFromHostModule, getClockType(), circt::hw::ModulePort::Input, circt::hw::ModulePort::Output, and rst.

◆ declareCosimEndpointToHostModule()

HWModuleExternOp ESIHWBuilder::declareCosimEndpointToHostModule ( Operation * symTable )

Write an 'ExternModuleOp' to use a hand-coded SystemVerilog module.

Said module contains a bi-directional Cosimulation DPI interface with valid/ready semantics.

Definition at line 147 of file ESIPasses.cpp.

References clk, constructUniqueSymbol(), dataIn, dataInReady, dataInValid, declaredCosimEndpointToHostModule, getClockType(), circt::hw::ModulePort::Input, circt::hw::ModulePort::Output, and rst.

◆ declareStage()

HWModuleExternOp ESIHWBuilder::declareStage	(	Operation *	symTable,
		PipelineStageOp	stage )

Write an 'ExternModuleOp' to use a hand-coded SystemVerilog module.

Said module implements pipeline stage, adding 1 cycle latency. This particular implementation is double-buffered and fully pipelines the reverse-flow ready signal.

Definition at line 108 of file ESIPasses.cpp.

References a, aReady, aValid, clk, constructUniqueSymbol(), declaredStage, getClockType(), getStageParameterList(), circt::hw::ModulePort::Input, circt::hw::ModulePort::Output, rst, x, xReady, and xValid.