17 #include "mlir/IR/BuiltinAttributes.h"
18 #include "mlir/IR/BuiltinTypes.h"
19 #include "llvm/ADT/SmallBitVector.h"
20 #include "llvm/ADT/SmallPtrSet.h"
21 #include "llvm/ADT/StringRef.h"
23 using namespace circt;
27 return attrs.getAs<::circt::hw::InnerSymAttr>(
28 hw::HWModuleLike::getPortSymbolAttrName());
35 NamedAttrList pattr(attrs);
38 oldValue = pattr.erase(portSymAttr);
40 oldValue = pattr.set(portSymAttr, sym);
41 if (oldValue != sym) {
42 attrs = pattr.getDictionary(ctx);
48 if (
auto updatedName = attrs.get(
"hw.verilogName"))
49 return cast<StringAttr>(updatedName).getValue();
50 return name.getValue();
54 auto innerSym = op.getInnerSymAttr();
60 return op->emitOpError(
"has empty list of inner symbols");
62 if (!op.supportsPerFieldSymbols()) {
64 if (innerSym.size() > 1 || !innerSym.getSymName()) {
65 op->emitOpError(
"does not support per-field inner symbols");
71 auto result = op.getTargetResult();
77 auto resultType = result.getType();
79 llvm::SmallBitVector indices(maxFields + 1);
80 llvm::SmallPtrSet<Attribute, 8> symNames;
82 auto uniqSyms = [&](InnerSymPropertiesAttr p) {
83 if (maxFields < p.getFieldID()) {
84 op->emitOpError(
"field id:'" + Twine(p.getFieldID()) +
85 "' is greater than the maximum field id:'" +
86 Twine(maxFields) +
"'");
89 if (indices.test(p.getFieldID())) {
90 op->emitOpError(
"cannot assign multiple symbol names to the field id:'" +
91 Twine(p.getFieldID()) +
"'");
94 indices.set(p.getFieldID());
95 auto it = symNames.insert(p.getName());
97 op->emitOpError(
"cannot reuse symbol name:'" + p.getName().getValue() +
104 if (!llvm::all_of(innerSym.getProps(), uniqSyms))
123 printer << dirstr <<
" " << port.
name <<
" : " << port.
type <<
" (argnum "
125 <<
", args " << port.
attrs <<
")";
129 #include "circt/Dialect/HW/HWOpInterfaces.cpp.inc"
Direction get(bool isOutput)
Returns an output direction if isOutput is true, otherwise returns an input direction.
uint64_t getMaxFieldID(Type)
OS & operator<<(OS &os, const InnerSymTarget &target)
Printing InnerSymTarget's.
LogicalResult verifyInnerSymAttr(InnerSymbolOpInterface op)
Verification hook for verifying InnerSym Attribute.
The InstanceGraph op interface, see InstanceGraphInterface.td for more details.
This holds the name, type, direction of a module's ports.
StringRef getVerilogName() const
DictionaryAttr attrs
The optional symbol for this port.
size_t argNum
This is the argument index or the result index depending on the direction.
void setSym(InnerSymAttr sym, MLIRContext *ctx)
InnerSymAttr getSym() const