13 #ifndef CIRCT_DIALECT_HW_OPS_H
14 #define CIRCT_DIALECT_HW_OPS_H
20 #include "mlir/IR/BuiltinOps.h"
21 #include "mlir/IR/ImplicitLocOpBuilder.h"
22 #include "mlir/IR/OpImplementation.h"
23 #include "mlir/IR/RegionKindInterface.h"
24 #include "mlir/IR/SymbolTable.h"
25 #include "mlir/Interfaces/ControlFlowInterfaces.h"
26 #include "mlir/Interfaces/FunctionInterfaces.h"
27 #include "mlir/Interfaces/InferTypeOpInterface.h"
28 #include "mlir/Interfaces/SideEffectInterfaces.h"
29 #include "llvm/ADT/StringExtras.h"
48 ArrayRef<std::pair<unsigned, PortInfo>> insertInputs,
49 ArrayRef<std::pair<unsigned, PortInfo>> insertOutputs,
50 ArrayRef<unsigned> removeInputs,
51 ArrayRef<unsigned> removeOutputs, Block *body =
nullptr);
86 bool disallowParamRefs =
false);
95 Attribute
value, ArrayAttr moduleParameters,
96 const std::function<
void(std::function<
bool(InFlightDiagnostic &)>)>
98 bool disallowParamRefs =
false);
101 bool isOffset(Value base, Value index, uint64_t offset);
138 #define GET_OP_CLASSES
139 #include "circt/Dialect/HW/HW.h.inc"
void setOutput(unsigned i, Value v)
Value getInput(unsigned i)
llvm::SmallVector< Value > outputOperands
llvm::SmallVector< Value > inputArgs
llvm::StringMap< unsigned > outputIdx
llvm::StringMap< unsigned > inputIdx
const ModulePortInfo & getPortList() const
HWModulePortAccessor(Location loc, const ModulePortInfo &info, Region &bodyRegion)
const llvm::SmallVector< Value > & getOutputOperands() const
bool isOffset(Value base, Value index, uint64_t offset)
llvm::function_ref< void(OpBuilder &, HWModulePortAccessor &)> HWModuleBuilder
bool isCombinational(Operation *op)
Return true if the specified operation is a combinational logic op.
void modifyModulePorts(Operation *op, ArrayRef< std::pair< unsigned, PortInfo >> insertInputs, ArrayRef< std::pair< unsigned, PortInfo >> insertOutputs, ArrayRef< unsigned > removeInputs, ArrayRef< unsigned > removeOutputs, Block *body=nullptr)
TODO: Move all these functions to a hw::ModuleLike interface.
StringRef getVerilogModuleName(Operation *module)
ModulePort::Direction flip(ModulePort::Direction direction)
Flip a port direction.
FunctionType getModuleType(Operation *module)
Return the signature for the specified module as a function type.
LogicalResult checkParameterInContext(Attribute value, Operation *module, Operation *usingOp, bool disallowParamRefs=false)
Check parameter specified by value to see if it is valid within the scope of the specified module mod...
bool isValidParameterExpression(Attribute attr, Operation *module)
Return true if the specified attribute tree is made up of nodes that are valid in a parameter express...
bool isValidIndexBitWidth(Value index, Value array)
bool isAnyModuleOrInstance(Operation *module)
Return true if isAnyModule or instance.
StringAttr getVerilogModuleNameAttr(Operation *module)
Returns the verilog module name attribute or symbol name of any module-like operations.
This file defines an intermediate representation for circuits acting as an abstraction for constraint...
This holds a decoded list of input/inout and output ports for a module or instance.