#include "mlir/Pass/Pass.h"#include "llvm/ADT/StringRef.h"#include "circt/Dialect/SV/SVPasses.h.inc"
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Namespaces | |
| circt | |
| This file defines an intermediate representation for circuits acting as an abstraction for constraints defined over an SMT's solver context. | |
| circt::sv | |
Macros | |
| #define | GEN_PASS_DECL_HWELIMINATEINOUTPORTS |
| #define | GEN_PASS_REGISTRATION |
| Generate the code for registering passes. More... | |
Functions | |
| std::unique_ptr< mlir::Pass > | circt::sv::createPrettifyVerilogPass () |
| std::unique_ptr< mlir::Pass > | circt::sv::createHWCleanupPass (bool mergeAlwaysBlocks=true) |
| std::unique_ptr< mlir::Pass > | circt::sv::createHWStubExternalModulesPass () |
| std::unique_ptr< mlir::Pass > | circt::sv::createHWLegalizeModulesPass () |
| std::unique_ptr< mlir::Pass > | circt::sv::createSVTraceIVerilogPass () |
| std::unique_ptr< mlir::Pass > | circt::sv::createHWGeneratorCalloutPass () |
| std::unique_ptr< mlir::Pass > | circt::sv::createHWEliminateInOutPortsPass (const HWEliminateInOutPortsOptions &options={}) |
| std::unique_ptr< mlir::Pass > | circt::sv::createSVExtractTestCodePass (bool disableInstanceExtraction=false, bool disableRegisterExtraction=false, bool disableModuleInlining=false) |
| std::unique_ptr< mlir::Pass > | circt::sv::createHWExportModuleHierarchyPass (std::optional< std::string > directory={}) |
Macro Definition Documentation
◆ GEN_PASS_DECL_HWELIMINATEINOUTPORTS
| #define GEN_PASS_DECL_HWELIMINATEINOUTPORTS |
Definition at line 22 of file SVPasses.h.
◆ GEN_PASS_REGISTRATION
| #define GEN_PASS_REGISTRATION |
Generate the code for registering passes.
Definition at line 40 of file SVPasses.h.
